CN101673253A - Realizing method of direct memory access (DMA) - Google Patents
Realizing method of direct memory access (DMA) Download PDFInfo
- Publication number
- CN101673253A CN101673253A CN200910091053A CN200910091053A CN101673253A CN 101673253 A CN101673253 A CN 101673253A CN 200910091053 A CN200910091053 A CN 200910091053A CN 200910091053 A CN200910091053 A CN 200910091053A CN 101673253 A CN101673253 A CN 101673253A
- Authority
- CN
- China
- Prior art keywords
- buffer zone
- data
- write
- dma
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Bus Control (AREA)
Abstract
The invention provides a realizing method of direct memory access (DMA), comprising the steps: a DMA engine writes data into a buffer zone, and updates an initial address to be written in the buffer zone at the next time in a preset register after writing at each time; and the DMA engine reads the written data from the buffer zone, and updates the initial address to be read in the buffer zone at the next time in the register after reading at each time. The method prevents from the problem that huge amounts of CPU resources and bus bandwidth are occupied caused by the intervention of a computerside operation system and the transmission of a descriptor in correlative technologies, and can effectively save bus bandwidth resources and reduce CPU load and effectively remove the interrupt and the delay in processing, thereby effectively improving the process efficiency of the DMA operation.
Description
Technical field
The present invention relates to the communications field, relate in particular to the implementation method of a kind of direct memory visit (Direct MemoryAccess abbreviates DMA as).
Background technology
DMA is a kind of high-speed data transmission operation, it allows externally directly to carry out data write between the equipment and storer, CPU need do when data transmission begins and finish a bit and handle, and the process of whole read-write does not neither need CPU to intervene by CPU yet, and CPU can carry out other work in transmission course.That is to say that in the most of the time of dma operation, the processing that CPU carries out and the input-output operation of storer are in the executed in parallel state, therefore can improve the efficient of whole computer system greatly.
But traditional DMA pattern is based on descriptor mostly, needs the participation of operating system could to realize dma operation.In order to receive or send data; upper level applications must enter the core of operating system, operations such as the related register of the scene protection recovery that so just can be correlated with, the locking/unlocking that is operated the page, virtual/physical address conversion, read-write dma controller, Interrupt Process.These operations all need to take a large amount of cpu resources, cause system performance to be subjected to very big influence.
In addition, because traditional dma operation need carry out based on descriptor, therefore each dma operation all needs to be described the transmission of symbol, takies a large amount of bus bandwidths.
Take the problem of a large amount of cpu resources and bus bandwidth at dma operation, present DMA technology mainly adopts the descriptor quantity that increases each dma operation process, increase the mode of interrupting granularity reduces interruption frequency, interrupts taking the problem that a large amount of cpu resources and descriptor take bus bandwidth thereby solve.Delay on equipment increases but this mode that reduces interruption frequency can make data, can not fundamentally improve the treatment effeciency of dma operation.
Treatment effeciency at dma operation in the correlation technique is low, dma operation reduces system performance and can take the problem of a large amount of bus bandwidths, does not propose effective solution at present as yet.
Summary of the invention
Treatment effeciency at direct memory access operation in the correlation technique is low, direct memory access operation reduces system performance and can take the problem of a large amount of bus bandwidths, the object of the present invention is to provide the implementation of a kind of direct memory visit, with in addressing the above problem one of at least.
For achieving the above object, according to the present invention, provide a kind of implementation method of direct memory visit.
Implementation method according to direct memory visit of the present invention comprises:
The direct memory access engine is that the DMA engine writes buffer zone with data, and upgrades the start address that next time writes after finishing in default register in buffer zone writing at every turn; The DMA engine reads the data that write from buffer zone, and upgrades the start address next time read after finishing in register from buffer zone reading at every turn.
Preferably, this method can also comprise: the length of memory buffer and start address in register in advance.And the start address of upgrading in register after writing at every turn and/or reading is the offset address with respect to the start address of buffer zone.
In addition, the DMA engine with data write buffer zone mode can for: write with the order from the low level to a high position in the buffer zone.Correspondingly, the DMA engine from the mode of buffer zone reading of data can for: read with the order from the low level to a high position the buffer zone.
And, at the data occupancy that writes under the situation of most significant digit of buffer zone, the DMA engine can be proceeded to write from the lowest order of buffer zone, and covers the data that read with the data that write.
In addition, this method can further include: main frame is handled the data that read from buffer zone at every turn, and obtains each start address of upgrading that reads and write in the register.
By above-mentioned at least one technical scheme of the present invention, realize writing and reading of data by utilizing the DMA engine, dma operation is carried out on network interface card, avoided in the correlation technique because the transmission of the intervention of computer-side operating system and descriptor causes taking the problem of a large amount of cpu resources and bus bandwidth, can effectively save bus bandwidth resources and reduce cpu load, can also effectively eliminate and handle interruption and the delay that produces, thereby effectively improve the treatment effeciency of dma operation.
Description of drawings
Fig. 1 is the process flow diagram according to the implementation method of the direct memory visit of the embodiment of the invention;
Fig. 2 is according to the operation chart that reads and write of carrying out data in the implementation method of the direct memory visit of the embodiment of the invention at buffer zone.
Embodiment
Functional overview
At in the correlation technique owing to dma operation causes the dma operation treatment effeciency low based on descriptor, influence system performance and can take the problem of a large amount of bus bandwidths, it is the fixing buffer zone of DMA engine distribution of network interface card side in advance that the present invention proposes, the address that the DMA engine calculates dma operation voluntarily (for example, calculating is in address that buffer zone writes and reads), and carry out dma operation and carry out reading and writing of data at buffer zone in real time, main frame (CPU of the computing machine that links to each other with network interface card) obtains the information of finishing of dma operation by inquiry mode, dma operation is independently finished on network interface card, the transmission of descriptor and the intervention of application program have been avoided, thereby effectively reduce the bus bandwidth expense of system and the burden of CPU, and can improve the treatment effeciency of dma operation.
Describe embodiments of the invention in detail below in conjunction with accompanying drawing.
In implementation process of the present invention, at first need in response to the request of the driving preface of network card binding, one or more CPU allocation buffer for computing machine, the size of buffer zone can be several million, tens of million, hundreds of megabyte, the quantity of buffer zone can be one or more, the corresponding relation of buffer zone and CPU can be one-to-many or many-one, preferably, in order to guarantee higher treatment effeciency, can be for each CPU dispose a buffer zone one to one with it respectively, this buffer zone can be continuous buffer zone.And, in actual mechanical process, need in response to,
Except the allocation buffer, also need to be provided with a register, this register can independently be provided with, and also can be provided with in the DMA engine.
Fig. 1 is the process flow diagram according to the implementation method of the direct memory visit of the embodiment of the invention.As shown in Figure 1, the implementation method of visiting according to the direct memory of the embodiment of the invention comprises:
Step S102, the DMA engine writes buffer zone with data, and upgrades the start address next time write after finishing in register in buffer zone writing at every turn;
Step S104, the DMA engine reads the data that write from buffer zone, and upgrades the start address next time read after finishing in register from buffer zone reading at every turn.
Like this, main frame just can be handled the current DMA data that read, inquire about and obtain the information of finishing of dma operation in one or more buffer zones in the mode of poll, can also inquire about the buffer zone offset register in the DMA engine afterwards, obtain the information of new DMA data (the DMA data that next time will handle).
It should be noted that, show step S102 sequentially among Fig. 1 and step S104 gets logical relation, but this only is an example, in the middle of practical application, the writing of step S102 handle and step S104 read processing can executed in parallel, or after continuously execution repeatedly writes again external phase answer reading of number of times, be not limited to the order shown in Fig. 1.
As can be seen, by above-mentioned processing of the present invention, dma operation is carried out on network interface card, realize writing and reading of data by the DMA engine, the intervention of computer-side operating system and the transmission of descriptor have been avoided, can effectively save bus bandwidth resources and reduce cpu load, and, because reading in the such scheme can walk abreast with write operation and to carry out, and main frame can a plurality of buffer zones of poll inquiry dma operation finish information, therefore can effectively eliminate and handle interruption and the delay that produces, thereby effectively improve the treatment effeciency of dma operation.
Preferably, buffer zone is write with read operation before, the length of memory buffer and initial address message (IAM) in register in advance, thus make driver can lock (sign) buffer zone.
Writing at every turn and/or read the start address of upgrading in register the back can be a sufficient address section, preferably, consider and when storage, save storage space, each start address of upgrading also can be the offset address with respect to the start address of buffer zone, that is, can be relative value.
Write fashionablely buffer zone being carried out data, the DMA engine can write with the order from the low level to a high position in the buffer zone,, begins storage from the low level of buffer zone that is; Correspondingly, the DMA engine can buffer zone in order from the low level to a high position carry out reading of data.
Fig. 2 is according to carrying out the operation chart that data write and read at buffer zone in the processing procedure of the implementation method of DMA of the present invention.
As shown in Figure 2, suppose that the first address (StartPhyAddress) of buffer zone is addrS, end address (EndPhyAddress) is addrE.In implementation procedure of the present invention, can determine in buffer zone, to read and write the address by the sensing of pointer, and register (can be the hardware register that is adopted usually) also can be divided into a plurality of storage areas, as shown in Figure 2, can be divided into: the first address register is used for start address (start address) addrS of memory buffer; Read pointer register, be used to store the position of the current indication of read pointer, this position can be the off-set value offsetR with respect to the buffer zone start address, that is, and and the reference position during reading of data when finishing (also can be understood as this reading of data position) in buffer zone next time; The write pointer register, be used to store the position of the current indication of write pointer, this position can be the off-set value offsetW with respect to the buffer zone start address, that is, and and the reference position when next time in buffer zone, writing data when writing ED (also can be understood as this position); The buffer size register is used for the size of memory buffer, and its size equals addrE-addrS.
Write pointer can at first point to the low level of buffer zone, the DMA engine can carry out the position that reference position that data write is determined the write pointer indication according to current in the register, and begin to write data Packet x to the high position of buffer zone from the position of write pointers point, this write finish after, this writes the position of ED write pointers point, need to upgrade the position of the write pointer of storing in the write pointer register simultaneously, write fashionable reference next time for the DMA engine; Afterwards, write pointer can continue to write a plurality of data according to this mode.
Alternatively, finish after data write at every turn, the DMA engine can read the data that these write at once, also can write a plurality of data at first continuously, for example, 3, in the time will writing the 4th data, read the 1st data that at first write, in the time will writing the 5th data, read the 2nd data that at first write, by that analogy.
In an embodiment of the present invention, when supposing the reference position of the data Packet y that will write in write pointers point, the DMA engine carries out reading of data, at this moment, read pointer can point to the reference position of the data Packet x that at first writes, and after the DMA engine had read data Packet x, read pointer pointed to the position that this reading of data finishes, need to upgrade the position of the read pointer of storing in the read pointer register simultaneously, reference when next time reading for the DMA engine.
At the data occupancy that writes under the situation of most significant digit of buffer zone (for example, the data occupancy that writes the end address EndPhyAddress of buffer zone), the DMA engine can be proceeded to write from the lowest order of buffer zone, and cover the data that read with the data that write, at this moment, write pointer is got back to the low level of buffer zone again; Similarly, as the end address EndPhyAddress of read pointer arrival buffer zone) time, read pointer also needs to get back to the low level of buffer zone.
Wherein, get back to the low level of buffer zone again at write pointer after, because the data that store write pointer this moment position pointed are read by the DMA engine, therefore the DMA engine can write new data to this position, the legacy data that covering has been read (promptly, reduced data can the storage area that these data are shared be interpreted as the clear area).
It should be noted that, although be that example has been described according to carrying out a kind of mode that data write and read in the dma operation of the present invention with the order from the low level to a high position before, but, the order that writes and read of carrying out data in buffer zone also can be that the high position from buffer zone begins to carry out to low level, just the moving direction of pointer is opposite, and this paper is not described in detail.
In sum, by above-mentioned at least one technical scheme of the present invention, realize writing and reading of data by utilizing the DMA engine, dma operation is carried out on network interface card, avoided in the correlation technique can effectively saving bus bandwidth resources and reducing cpu load because the transmission of the intervention of computer-side operating system and descriptor causes taking the problem of a large amount of cpu resources and bus bandwidth; In addition, because reading in the such scheme can walk abreast with write operation and to carry out, main frame can a plurality of buffer zones of poll inquiry dma operation finish information, dma operation bypass operation system, therefore can effectively eliminate and handle interruption and the delay that produces, thereby effectively improve the treatment effeciency of dma operation.Obviously, those skilled in the art should be understood that, above-mentioned each module of the present invention or each step can realize with the general calculation device, they can concentrate on the single calculation element, perhaps be distributed on the network that a plurality of calculation element forms, alternatively, they can be realized with the executable program code of calculation element, thereby, they can be stored in the memory storage and carry out by calculation element, perhaps they are made into each integrated circuit modules respectively, perhaps a plurality of modules in them or step are made into the single integrated circuit module and realize.Like this, the present invention is not restricted to any specific hardware and software combination.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1. the implementation method of a direct memory visit is characterized in that, comprising:
The direct memory access engine is that the DMA engine writes buffer zone with data, and upgrades the start address that next time writes after finishing in default register in described buffer zone writing at every turn;
Described DMA engine reads the data that write from described buffer zone, and upgrades the start address next time read after finishing in described register from described buffer zone reading at every turn.
2. method according to claim 1 is characterized in that, also comprises: the length and the start address of storing described buffer zone in advance in described register.
3. method according to claim 2 is characterized in that, the start address of upgrading in described register after writing at every turn and/or reading is the offset address with respect to the start address of described buffer zone.
4. method according to claim 1 is characterized in that, described DMA engine with the mode that data write described buffer zone is: write with the order from the low level to a high position in the described buffer zone.
5. method according to claim 4 is characterized in that, described DMA engine from the mode of described buffer zone reading of data is: read with the order from the low level to a high position the described buffer zone.
6. method according to claim 4, it is characterized in that, at the data occupancy that writes under the situation of most significant digit of described buffer zone, described DMA engine is proceeded to write from the lowest order of described buffer zone, and covers the data that read with the data that write.
7. method according to claim 1 is characterized in that, further comprises: main frame is handled the data that read from described buffer zone at every turn, and obtains each start address of upgrading that reads and write in the described register.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910091053A CN101673253A (en) | 2009-08-21 | 2009-08-21 | Realizing method of direct memory access (DMA) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910091053A CN101673253A (en) | 2009-08-21 | 2009-08-21 | Realizing method of direct memory access (DMA) |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101673253A true CN101673253A (en) | 2010-03-17 |
Family
ID=42020483
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910091053A Pending CN101673253A (en) | 2009-08-21 | 2009-08-21 | Realizing method of direct memory access (DMA) |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101673253A (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102420749A (en) * | 2011-11-28 | 2012-04-18 | 曙光信息产业(北京)有限公司 | Device and method for realizing network card issuing function |
| CN102521179A (en) * | 2011-11-28 | 2012-06-27 | 曙光信息产业股份有限公司 | Achieving device and achieving method of direct memory access (DMA) reading operation |
| CN102541779A (en) * | 2011-11-28 | 2012-07-04 | 曙光信息产业(北京)有限公司 | System and method for improving direct memory access (DMA) efficiency of multi-data buffer |
| CN104123250A (en) * | 2013-04-25 | 2014-10-29 | 上海联影医疗科技有限公司 | Data transmission method based on DMA |
| CN106776393A (en) * | 2016-12-26 | 2017-05-31 | 北京旋极信息技术股份有限公司 | A kind of serial data method of reseptance and device without interruption |
| CN107589821A (en) * | 2016-07-07 | 2018-01-16 | 上海中兴软件有限责任公司 | A kind of time display method and intelligent watch |
| CN108572798A (en) * | 2017-03-10 | 2018-09-25 | 三星电子株式会社 | The storage device and its method of snoop-operations are executed for rapid data transmission |
| CN108595351A (en) * | 2018-05-11 | 2018-09-28 | 湖南华芯通网络科技有限公司 | A kind of DMA sending control methods of network-oriented forward process |
| CN109144906A (en) * | 2017-06-15 | 2019-01-04 | 北京忆芯科技有限公司 | Electronic equipment and its command dma processing method |
| CN110138553A (en) * | 2019-05-10 | 2019-08-16 | 郑州信大捷安信息技术股份有限公司 | A kind of IPSec vpn gateway data packet processing and method |
| CN110825674A (en) * | 2019-10-30 | 2020-02-21 | 北京计算机技术及应用研究所 | PCIE DMA (peripheral component interface express) interaction system and interaction method based on FPGA (field programmable Gate array) |
| CN113360077A (en) * | 2020-03-04 | 2021-09-07 | 华为技术有限公司 | Data storage method and computing node |
| CN115237353A (en) * | 2022-08-12 | 2022-10-25 | 青岛汉泰智能科技有限公司 | Method for querying FPGA length register by ARM |
-
2009
- 2009-08-21 CN CN200910091053A patent/CN101673253A/en active Pending
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102521179A (en) * | 2011-11-28 | 2012-06-27 | 曙光信息产业股份有限公司 | Achieving device and achieving method of direct memory access (DMA) reading operation |
| CN102541779A (en) * | 2011-11-28 | 2012-07-04 | 曙光信息产业(北京)有限公司 | System and method for improving direct memory access (DMA) efficiency of multi-data buffer |
| CN102541779B (en) * | 2011-11-28 | 2015-07-08 | 曙光信息产业(北京)有限公司 | System and method for improving direct memory access (DMA) efficiency of multi-data buffer |
| CN102420749A (en) * | 2011-11-28 | 2012-04-18 | 曙光信息产业(北京)有限公司 | Device and method for realizing network card issuing function |
| CN104123250B (en) * | 2013-04-25 | 2019-02-01 | 上海联影医疗科技有限公司 | Data transmission method based on DMA |
| CN104123250A (en) * | 2013-04-25 | 2014-10-29 | 上海联影医疗科技有限公司 | Data transmission method based on DMA |
| CN107589821A (en) * | 2016-07-07 | 2018-01-16 | 上海中兴软件有限责任公司 | A kind of time display method and intelligent watch |
| CN106776393A (en) * | 2016-12-26 | 2017-05-31 | 北京旋极信息技术股份有限公司 | A kind of serial data method of reseptance and device without interruption |
| CN106776393B (en) * | 2016-12-26 | 2020-01-31 | 北京旋极信息技术股份有限公司 | uninterrupted serial port data receiving method and device |
| CN108572798B (en) * | 2017-03-10 | 2023-02-21 | 三星电子株式会社 | Storage device and method for performing snoop operation for fast data transmission |
| CN108572798A (en) * | 2017-03-10 | 2018-09-25 | 三星电子株式会社 | The storage device and its method of snoop-operations are executed for rapid data transmission |
| CN109144906A (en) * | 2017-06-15 | 2019-01-04 | 北京忆芯科技有限公司 | Electronic equipment and its command dma processing method |
| CN109144906B (en) * | 2017-06-15 | 2019-11-26 | 北京忆芯科技有限公司 | Electronic equipment and its command dma processing method |
| CN110737614A (en) * | 2017-06-15 | 2020-01-31 | 北京忆芯科技有限公司 | Electronic equipment with DMA accelerator and DMA command processing method thereof |
| CN108595351A (en) * | 2018-05-11 | 2018-09-28 | 湖南华芯通网络科技有限公司 | A kind of DMA sending control methods of network-oriented forward process |
| CN110138553A (en) * | 2019-05-10 | 2019-08-16 | 郑州信大捷安信息技术股份有限公司 | A kind of IPSec vpn gateway data packet processing and method |
| CN110825674A (en) * | 2019-10-30 | 2020-02-21 | 北京计算机技术及应用研究所 | PCIE DMA (peripheral component interface express) interaction system and interaction method based on FPGA (field programmable Gate array) |
| CN113360077A (en) * | 2020-03-04 | 2021-09-07 | 华为技术有限公司 | Data storage method and computing node |
| CN113360077B (en) * | 2020-03-04 | 2023-03-03 | 华为技术有限公司 | Data storage method, computing node and storage system |
| CN115237353A (en) * | 2022-08-12 | 2022-10-25 | 青岛汉泰智能科技有限公司 | Method for querying FPGA length register by ARM |
| CN115237353B (en) * | 2022-08-12 | 2023-12-22 | 青岛汉泰智能科技有限公司 | ARM method for inquiring FPGA length register |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101673253A (en) | Realizing method of direct memory access (DMA) | |
| CN100590609C (en) | Method for managing dynamic internal memory base on discontinuous page | |
| CN101650698B (en) | Method for realizing direct memory access | |
| USRE47659E1 (en) | Memory system having high data transfer efficiency and host controller | |
| CN104424113A (en) | Storage device and data processing method | |
| CN100389420C (en) | Method and apparatus for accelerating file system operation by using coprocessor | |
| CN101504632B (en) | DMA data transmission method and system, DMA controller | |
| CN100565486C (en) | Data link and data communication system | |
| CN107870879A (en) | A kind of data-moving method, accelerator board, main frame and data-moving system | |
| CN103809922A (en) | Image forming system | |
| CN111783933A (en) | Hardware circuit design and method for data loading device combining main memory and accelerating deep convolution neural network calculation | |
| CN103577119A (en) | System and method for transferring data out of order in next generation solid state drive controller | |
| CN110059024B (en) | Memory space data caching method and device | |
| US20100257329A1 (en) | Apparatus and method for loading and storing multi-dimensional arrays of data in a parallel processing unit | |
| CN103559079A (en) | Shared memory based data access method and device | |
| CN101751338A (en) | Data access control device and data access method | |
| CN112988621A (en) | Data loading device and method for tensor data | |
| CN107861887B (en) | Control method of serial volatile memory | |
| CN102420749A (en) | Device and method for realizing network card issuing function | |
| CN115586943A (en) | Hardware marking implementation method for dirty pages of virtual machine of intelligent network card | |
| CN101794276B (en) | Discrete cosine transform (DCT)-inverse discrete cosine transform (IDCT) coprocessor suitable for system on chip (SOC) | |
| CN108196790B (en) | Data management method, storage device, and computer-readable storage medium | |
| CN113094170B (en) | Memory bus allocation method and terminal for 5G communication virtualization network element | |
| CN117991995B (en) | SD card file continuous reading or writing control method, system and storage device | |
| CN114840458B (en) | Read-write module, system on chip and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20100317 |