CN101673219A - Multi-task processor and task switching method thereof - Google Patents
Multi-task processor and task switching method thereof Download PDFInfo
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Abstract
The invention provides a multi-task processor and a task switching method thereof. The task switching method comprises the following steps: the multi-task processor executes a first task, and an execute instruction of the first task comprises a plurality of switching point instructions; an interrupt event occurs and enables the multi-task processor to postpone the execution of the current first task and change to execute a second task; the multi-task processor executes a processing program of the interrupt event and sets a task switching mark; and after the processing program of the interruptevent is finished, the multi-task processor does not perform task switching and still continues executing the first task, and until executing to a switching point instruction in the execute instruction of the first task, the multi-task processor performs the task switching and changes to execute the second task.
Description
Technical field
The present invention relates to a kind of multi-task processor and target switching method thereof.
Background technology
Flourish along with science and technology, make communication and multimedia standard constantly upgrade, many tame dealers are in order to deal with the renewal speed of communication and multimedia standardization, so replace traditional specific function integrated circuit (application specifiedintegrated circuit with programmable processor (programmable processor), ASIC), be incorporated in the embedded system.And the communication and the multimedia application of a new generation tend to improve the multi-task processor computational complexity, reach the function that the high image quality content is provided with low bit rate.The demand of handling for instant (real-time) that meets on communication and the multimedia (carry out a plurality of application programs simultaneously, in time react user's demand etc.), programmable processor (programmableprocessor) is in being to use the dynamically ability of instant management of operating system (operating system) or micro core (micro kernel), and realizes in the mode of timesharing (time slicing) multitask (multitasking).
Under the environment of TCM, programmable processor must usually switch performed work (or title task, task), whenever carrying out a subtask switches, then must carry out content and switch (contextswitch), the task status (comprising register and other mission bit streams) of carrying out is now all deposited stack in (stack).The development trend of programmable processor tends to increase the quantity of register now, and the word length (word-length) of lengthening register, so that by single instruction multiple data (singleinstruction multiple data, abbreviation SIMD) technology, utilize the data level depth of parallelism (data-levelparallelism is called for short DLP) to promote arithmetic capability.
The dynamically instant mode of managing of the micro core of product sorts based on the formula of trying to be the first (preemptive) mostly on the market.Fig. 1 is the decline task switching flow figure of core of trying to be the first of existing multi-task processor.When interrupting (interrupt) generation (as step S101), micro core can be controlled multi-task processor and suspend all tasks earlier.Then can execution in step S102, earlier the content of the needed part register of Interrupt Process (interrupt handler) is kept (backup) in stack.Step S103 can carry out the handling procedure of interrupt event, micro core can be controlled multi-task processor and stored earlier and stack some this moment, then all tasks (comprise in the execution, wait for being performed and interrupting being written into of task) was carried out again task scheduling (reschedule).When carrying out step S104, the meeting foundation is the result of task scheduling again, and whether comparison has than present executory task has the more task of high priority.If have, just can do once complete content and switch, make multi-task processor be written into the higher task of right of priority (step S110) earlier.So-called content is switched, and comprises all of original task are carried out contents (content of register) to back up to and stack, and then all of new task is carried out contents and deposits back in the register.After finishing the content switching, just can begin to carry out new task (step S111).If there is not the more task of high priority, then the content of registers that step S102 can be backed up is deposited back (step S120) in the register, so that allow original executory task continue to carry out (step S121).
Figure 1A is according to prior art, the task sequential chart of key diagram 1.Transverse axis express time t among the figure.In Fig. 1, be time T the time delay of trying to be the first
11And T
12With reference to Figure 1A, before time T 101, multi-task processor is carried out first task.After interrupt events took place for time T 101, multi-task processor suspends carried out first task, and carried out the handling procedure (comprise Interrupt Process with task scheduling) again of interrupt event in during time T 101～T102.Wherein, again task scheduling can to all etc. the rearrangement of pending task.
After finishing again task scheduling (just after time T 102), if task scheduling shows that the first task of originally carrying out is the task that override is handled again, then multi-task processor will continue to carry out first task; After finishing again task scheduling (just after time T 102), if when having a task (second task) to replace executory task (first task) to become the task that override handles, then multi-task processor switches task and changes aforesaid second task of execution, and carries out the content switching in during time T 102～T103.Between transfer period, multi-task processor is written into the second task executions content in the register in the execution content (contents of all registers) of first task can being backed up to and stacking then in content.Clearly, content is switched required time, need decide on the quantity of register and the word length of each register.Under the development trend of multi-task processor able to programme now, content is switched required time (be time T102～T103 during) can be more and more longer.In Figure 1A, its time T
1Be the time of the delay of trying to be the first (preemption latency), representative is switched institute's time spent from interrupt event takes place to finishing content.Switch back (being time T103) when finishing content, multi-task processor has been ready to and has begun to carry out second task at this moment.
In the instant system that handles, the time (T1) of the delay of trying to be the first is one and considers emphasis.Decline in the core existing trying to be the first, when carrying out content and switch, all registers (comprising in the use and untapped register) can be backed up, wherein also comprise the register that does not re-use.
Summary of the invention
The invention provides a kind of multi-task processor, this multi-task processor comprises processing unit and switching mark, and it can accept the task assignment more than two.Processing unit contains the instruction set of a switching point instructions in order to execution, and wherein this switching point instructions is specific processor instruction.Wherein, this processing unit is carried out the first task with at least one switching point instructions.When interrupt event takes place when, processing unit is carried out the handling procedure of interrupt event to judge whether needing task to switch, and after setting this switching mark according to judged result, this processing unit promptly continues to carry out first task, checks this switching mark when processing unit is carried out this at least one switching point instructions in this first task; If switching mark is represented this processing unit and judges that when carrying out the handling procedure of aforementioned interrupt event need carry out task switches that then processing unit promptly carries out the task switching and changes second task of execution.If this switching mark represents that processing unit is judged and does not need task switching that then processing unit then continues to carry out first task when carrying out the handling procedure of interrupt event.
The present invention also proposes a kind of target switching method of multi-task processor.This target switching method comprises the steps.At first carry out first task by multi-task processor.Suppose that this multi-task processor of a certain representations of events should carry out task and switch, so that switch to second task of execution by carrying out first task.When this incident takes place when, make this multi-task processor postpone carrying out this task and switch, and continue to carry out first task, carry out changeable point to the first task until this multi-task processor, footpath this task of row is switched to switch second task of execution.
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and be described with reference to the accompanying drawings as follows.
Description of drawings
Fig. 1 is the decline task switching flow figure of core of trying to be the first of existing multi-task processor.
Figure 1A is according to existing, the task sequential chart of key diagram 1.
Fig. 2 A is according to disconnected event handling process flow diagram among the target switching method of the multi-task processor of one embodiment of the invention.
Fig. 2 B is the task hand-off process process flow diagram according to the target switching method of the multi-task processor of one embodiment of the invention.
Fig. 2 C is switching point instructions configuration schematic diagram according to an embodiment of the invention.
Fig. 2 D is the sequential chart of the target switching method of multi-task processor according to an embodiment of the invention.
Fig. 3 is the calcspar according to the multi-task processor of one embodiment of the invention.
Fig. 3 A is according to one embodiment of the invention, key diagram 3 survival register tables synoptic diagram.
The reference numeral explanation
S101～S104, S110, S111, S120, S121, S210～S215, S221～S225: step
T120, T101, T103～T105, T110, T201～T204: time
201～204: the position of register minimum number
210: procedure code
211～214: switching point instructions
300: multi-task processor
350: switching mark
322: register cell
341: data-carrier store
342: the survival register tables
343_～343_n: survival register inventory
310: instruction fetch stage
320: instruction decode stage
321: demoder
330: execution level
340: the data access level
AND1: with door
Embodiment
Mentioned as described above, present multi-task processor designer trends tend to increase the quantity of register and the length of word, this makes existing trying to be the first decline core when carrying out a plurality of task with TCM, stores all registers in the time of task handoff procedure overspending.In view of this, the present invention will propose a multi-task processor, and utilizing increases a switching point instructions and all dehorn will, the target switching method of arranging in pairs or groups.
Below all embodiment will illustrate that when a certain incident (for example interrupt event) took place, how multi-task processor of the present invention carries out task switched.Aforementioned this multi-task processor of a certain representations of events should carry out " task switching ", so that switch carry out " second task " by carrying out " first task ".
When the interrupt event that aforementioned foot switches with the triggering task takes place when, the multi-task processor of present embodiment is postponed carrying out task and is switched, and present task (first task) is carried out in continuation, carry out changeable point to the first task until multi-task processor, just carry out task and switch to switch the new task (second task) of carrying out.Aforesaid changeable point can be in the first task, carries out task and switches the less place of required cost resource.In addition, this changeable point also can be in the first task, for satisfying the set task switching point of instantaneity demand (real-time requirements).Those skilled in the art can achieve in any way described changeable point.For example, task is switched the less place of required cost resource and is disposed a certain specific instruction (switching point instructions) in first task, with the position that indicates described changeable point and trigger multi-task processor and carry out " task switching ".
It should be noted that the alleged incident (or interrupt event) that is enough to trigger " task switching " of present embodiment and following all embodiment, can be any type of incident.For example, this incident can be outside or inner software interruption incident that takes place or a hardware interrupts incident of multi-task processor.Again for example, this incident can be the timer event (timer events) that takes place the fixed cycle.Below again for another embodiment, with the detailed implementation of explanation present embodiment.
Fig. 2 A is the interrupt event processing flow chart according to the target switching method of the multi-task processor of one embodiment of the invention.Fig. 2 B is the task hand-off process process flow diagram according to the target switching method of the multi-task processor of one embodiment of the invention.Fig. 2 C is changeable according to an embodiment of the invention point (or switching point instructions) configuration schematic diagram.Fig. 2 D is the sequential chart of the target switching method of multi-task processor according to an embodiment of the invention.Transverse axis express time t among Fig. 2 D.
With reference to Fig. 2 D, before time T 201, multi-task processor can be written into and carry out first task earlier, and wherein first task can comprise at least one switching point instructions.If this multi-task processor is carried out in the first task, do not take place to interrupt and do not carry out switching point instructions, then multi-task processor can continue to carry out first task.Please in the process that first task is carried out, suppose interrupt event to take place simultaneously with reference to Fig. 2 A and Fig. 2 D in time T 201.Multi-task processor meeting this moment suspends earlier carries out first task, and the content of backup part register, to keep the required part register (step S210) of handling procedure of interrupt event.The handling procedure (step S211) of then carrying out interrupt event carries out task scheduling again to all tasks (task of comprise in the execution, wait being performed and triggering interruption).
If the result of the task scheduling right of priority that shows first task is maximum (step S212) again, that is judged result is "No", and then directly execution in step S214 is not provided with switching mark with the register that handling procedure was kept of reduction interrupt event.Next multi-task processor can continue to carry out first task (step S215) after time T 202.Otherwise, if the result of task scheduling shows that first task is not the task (step S212) of right of priority maximum again; Representative has the more task of high priority (task at this hypothesis highest priority is second task); Behind completing steps S212, multi-task processor can be provided with switching mark (step S213) at multi-task processor, then reduces the register that handling procedure kept (step S214) of interrupt event before time T 202.After time T 202, supposed before time T 203, interrupt event does not take place and carries out switching point instructions in first task, multi-task processor does not carry out the task switching and can continue to carry out first task (step S215), and the switching point instructions in first task is performed (time T 203 that is Fig. 2 D).
Please refer to Fig. 2 B and Fig. 2 D, when multi-task processor was carried out switching point instructions, step S221 can check whether switching mark is set up.Do not carried out step S213 as multi-task processor, that is switching mark is not set, multi-task processor will continue execution first task (step S215) when carrying out switching point instructions in the first task.Otherwise if multi-task processor is provided with switching mark in step S213, then multi-task processor is then carrying out changing second task of execution after " content is switched (context switch) " operation behind the completing steps S221; That is to say, when multi-task processor is carried out switching point instructions, if in the handling procedure of interrupt event again the result of task scheduling represent that multi-task processor needs task to switch, then multi-task processor carries out changing second task of execution after content is switched.In the present embodiment, the content switching comprises step S222, S223 and S224.In step S222, multi-task processor can write down to stack a little and the execution content of first task deposited in and stack keeping with the backup desire of task and carry out content.After backup was finished, multi-task processor was removed switching mark (step S223), is written into the second task executions content (step S224) then.After finishing above-mentioned action, multi-task processor has just been finished the operation of content switching, and after time T 204, changes second task (step S225) of carrying out, and first task will be by idle to the interrupt event generation next time or second task termination simultaneously.In Fig. 2 D, be time T the time delay of trying to be the first
21And T
22
The position of above-mentioned switching point instructions in first task can be the less position of using system resource in the first task, that is multi-task processor carries out the position of the register negligible amounts that need keep when task is switched.Please refer to Fig. 2 C, its transverse axis is represented the program execution sequence of first task, and the longitudinal axis represents that multi-task processor carries out the register quantity that need keep when task is switched.Generally speaking, can utilize the program language compiler to carry out static analysis and obtain the curve shown in Fig. 2 C.Before the configuration switching point instructions, the program designer can utilize compiler that the procedure code 210 of first task is done static analysis, obtaining the user mode of procedure code to register, these registers that will use are exactly that multi-task processor carries out the register that need keep when task is switched.Then compiler can be configured in the place (for example switching point instructions 214 being configured in position 204) that needs to keep the register minimum number in the procedure code with switching point instructions according to staticaanalysis results, and whether test meets restriction time delay of trying to be the first.If can not meet restriction time delay of trying to be the first, compiler can relax the restriction of use resource and the procedure code target section (target section) that disposes the switching point instructions deficiency is further analyzed, and then switching point instructions is configured in the best replacement point in this target section; This best replacement point is in the target section, when multi-task processor carries out the task switching, needs to keep the place of register minimum number, as among Fig. 2 C switching point instructions 211,212 and 213 being configured in position 201,202 and 203 respectively.Carry out repeatedly with above-mentioned action that the time delay of trying to be the first between two adjacent switching point instructions can be not long in the first task procedure code.For fear of the too much switching point instructions of configuration in procedure code, the usefulness that makes first task carry out significantly reduces, to do analysis to procedure code more at last, merge the two too short adjacent switching point instructions of time delay of trying to be the first, can too much not reach switching point instructions 211～214 is configured in separately needs to keep the register minimum number in the target section place 201～204 with switching point instructions 211～214 quantity in the first task after guaranteeing to compile.
Above-mentioned switching point instructions configuration mode is first kind of configuration mode, in addition, proposes the mode of second kind of switching point instructions configuration at this.This mode is for being disposed at switching point instructions the ending end of each subroutine of first task (subtask) earlier; During factor EOP (end of program), only can keep result that end of subroutine operate to be passed to master routine or next subroutine, so its reservation register quantity (that is using system resource) is understood minimum.Whether the configuration of then testing two switching point instructions is satisfied and is tried to be the first time delay, and disposes extra switching point instructions in best replacement point according to test result.And employed test mode is identical with above-mentioned configuration mode, so repeat no more.
Yet the end of subroutine is not one to be decided to be the position that keeps the register minimum number, thus can be changed according to aforesaid way, to meet the restriction of the time delay of trying to be the first.The third configuration mode of switching point instructions is done static analysis for elder generation to each child code, and switching point instructions is disposed at the place that keeps the register minimum number, and this place not necessarily is the end of subtask.Then, whole procedure is done test time delay whether meet restriction time delay, as do not meet, then assign switching point instructions again with above-mentioned switching point instructions configuration mode with position and the density of understanding the switching point instructions configuration.And in other embodiment, the configuration mode of switching point instructions can be combination and other configuration modes of the configuration mode of above-mentioned first, second and third kind of switching point instructions.For example, the configuration mode of switching point instructions also can be in first task, for satisfying the set task switching point of instantaneity demand (real-time requirements).
By aforesaid embodiment as can be known, the multi-task processor of the present invention's proposition is when carrying out first task; When an interrupt event takes place, multi-task processor is promptly postponed the first task execution, changes the handling procedure of carrying out interrupt event.By this, the present invention still keeps the fast throughput for interrupt event.
By aforesaid embodiment as can be known, the multi-task processor that the present invention proposes, because of switching point instructions is disposed at the less place of using system resource in the first task, make the multi-task processor hand-off process of executing the task when the using system resource is less, it is also less relatively to carry out the time that task switches.
Fig. 3 is the calcspar according to the multi-task processor 300 of one embodiment of the invention.Please refer to Fig. 3, multi-task processor 300 comprises processing unit and switching mark 350.Processing unit contains the instruction set of a switching point instructions in order to execution, and wherein this switching point instructions is specific processor instruction.Wherein, this processing unit is carried out the first task with at least one switching point instructions.When interrupt event takes place when, this processing unit carries out the handling procedure of this interrupt event to judge whether needing task to switch, and according to after the judged result setting switching mark, this processing unit promptly continues to carry out first task, inspection switching mark when processing unit is carried out this at least one switching point instructions in the first task; If switching mark is represented this processing unit and judges the switching of the task of need that when carrying out the handling procedure of interrupt event then processing unit promptly carries out task and switches and change second task of execution; And if switching mark represents that this processing unit is judged and does not need task switching that then processing unit then continues to carry out first task when carrying out the handling procedure of interrupt event.
Those skilled in the art can achieve in any way processing unit.For example, processing unit shown in Figure 3 comprise instruction fetch stage 310, instruction decode stage 320, execution level 330, data access level 340, with door AND1 etc.Do not draw whole members and whole signal paths (for example control/setting signal path etc.) among Fig. 3, in order to avoid graphic too numerous and diverse.Instruction fetch stage 310 can be extracted the instruction in the task program sign indicating number in proper order, and instruction is sent to instruction decode stage 320 decodes.After decoding was finished, decoded instruction can be sent to execution level 330, to carry out this instruction.
In present embodiment, each instruction that instruction fetch stage 310 is understood in the procedure code that extract earlier first task in proper order.Wherein, be configured a plurality of switching point instructions in the procedure code of first task, the configuration mode of its switching point instructions can be with reference to Fig. 2 C and related description, so repeat no more.The instruction that instruction fetch stage 310 is extracted is sent to execution level 330 and carries out after demoder 321 decodings.
In present embodiment, when multi-task processor each switching point in first task carries out the task switching, the different execution content of all essential backup.In present embodiment, will set up exclusive survival register inventory (live register list) at each switching command, so that write down the register that need back up when multi-task processor carries out the task switching.Each self-contained address of each switching point instructions, the pairing survival register of this switching point inventory is pointed in this address.Below will utilize all survival register inventories of survival register tables (liveregister table) 342 records.
In the present embodiment, survival register tables 342 is to be disposed in the data-carrier store 341.Those skilled in the art can implement above-mentioned survival register tables 342 in any form.For example, Fig. 3 A is according to one embodiment of the invention, key diagram 3 survival register tables 342 synoptic diagram.With reference to Fig. 3 A, the execution content that will keep because of each switching point is not quite similar, so (the survival register inventory 343_1 of Fig. 3 A～343_n) for example is so that write down the register information that it need keep for each switching point instructions will to set up a plurality of survival register inventories 343.For example, the register information that switching point instructions 211 will retain among Fig. 2 C is recorded among the survival register inventory 343_1 of Fig. 3 A, and the survival register inventory 342_2 that the register information that switching point instructions 212 will retain is recorded in Fig. 3 A below analogizes.343_3 is an example with survival register inventory, among the survival register inventory 343_3, when its record switching point instructions 213 is carried out (position 203 of Fig. 2 C), when multi-task processor carries out the task switching, the register of required storage backup (0 expression does not store, and 1 indicates stores).For example, if the content of survival register inventory 343_3 is " 011... ", the content of register R0 does not store in the expression register cell 320, and the content of register R1 will store, and the content of register R2 will store, by that analogy.As shown in Figure 3A, all survival register inventory 343_1～343_n can be recorded in the survival register tables 342, the design that width m of the register tables of wherein surviving 342 (register number in the representative system) and length n (represent the switching point instructions number) can know the knowledgeable usually according to demand and this area of system environments and changing to some extent.
In sum, please refer to Fig. 3 and Fig. 3 A, instruction fetch stage 310 can be extracted the instruction in the first task procedure code in proper order, and instruction is offered demoder 321 decodings.When execution level 330 receives decoded instruction, then can produce different actions according to the requirement of instruction.Register cell 322 comprises a plurality of registers, in order to the execution content of record multi-task processor 300.As described in the previous embodiment, in the process that first task is carried out, when system (is to trigger with second task to interrupt at present embodiment) when interrupt event takes place time T 201, execution level 330 can be carried out the handling procedure of interrupt event at this moment.In the handling procedure of interrupt event, execution level 330 suspends the execution of first tasks earlier, and with in the register cell 322 partly the data backup of register to stacking (or data-carrier store 341), so that keep the required register of handling procedure of interrupt event.Then all tasks are carried out again task scheduling (step S211).Those skilled in the art can the aforementioned interrupt event of any technology implementation handling procedure and task scheduling again, for example use prior art and realize aforementioned Interrupt Process and task scheduling again.
After task scheduling again, whether multi-task processor 300 can be inspected first task is the task (step S212) of highest priority.When first task was not the task of highest priority, then multi-task processor 300 can be provided with switching mark 350 (step S213); Relative, when first task is the task of highest priority, 300 replacements of multi-task processor (reset) or removing switching mark 350.The aforementioned operation flow process can be with reference to Fig. 2 A and related description thereof.The operation of above-mentioned steps S211, S212, S213 can be by instruction decode stage 320 or execution level 330 or multi-task processor 300 inner other control circuits (not illustrating) implementations.
No matter whether switching mark is set up, after execution level 330 is finished again task scheduling, the multi-task processor reduction register (step S214) that Interrupt Process kept.After finishing the data answer of register cell 322, execution level 330 can continue to carry out first tasks.That is to say that multi-task processor 300 does not carry out after finishing the handling procedure of interrupt event that task is switched and continues to carry out first task, carry out switching point instructions to the first task up to multi-task processor 300.
When instruction fetch stage 310 is delivered to demoder 321 with the switching point instructions of first task (time T 203 of Fig. 2 D), demoder 321 can send the task switching signal to door AND1.Under the state that switching mark 350 is not set up as yet (that is switching mark 350 is logical zero), the task switching signal that demoder 321 sent can be stopped with door AND1 and can't be arrived instruction fetch stage 310.Under the state that switching mark 350 is set up (that is switching mark 350 is logical one), the task switching signal that demoder 321 sent can be via arriving instruction fetch stage 310 with door AND1.Instruction fetch stage 310 just can determine whether continuing to extract the instruction of first task procedure code according to this task switching signal, or changes the instruction of extraction task changeover program so that carry out second task program.
Therefore, when instruction decode stage 320 was carried out switching point instructions, if switching mark 350 is not set up, then multi-task processor 300 continued to carry out first task.Otherwise when instruction decode stage 320 was carried out switching point instructions, if switching mark 350 is set up, then multi-task processor 300 carried out content and switches (during the T203～T204 shown in Fig. 2 D) to carry out second task.When carrying out the content switching, multi-task processor 300 finds out the survival register inventory (corresponding to the register inventory 3433 of surviving in this hypothesis) of corresponding this switching point instructions according to present performed switching point instructions from survival register tables 342.Multi-task processor 300 can be according to the survival register inventory content of this switching point instructions correspondence, store the survival register in the back-up registers unit 322, and with the content of the register of these appointments deposit in stack in (or in data-carrier store 341), so just first task in the multi-task processor 300 can be backed up (step S222) in the execution content of time point T203.After backup was finished, multi-task processor 300 was removed switching mark (step S223), is written into the second task executions content (step S224) then, with the switching of finishing the work.Above-mentioned steps S222, S223, S224 and other operations can be undertaken by instruction decode stage 320 or execution level 330 or multi-task processor 300 inner other control circuits (not illustrating), need look the different application demand and adopt different design meanses.
After the switching of finishing the work, instruction fetch stage 310 can beginning be extracted the instruction of the second task program sign indicating number in proper order, and makes multi-task processor 300 begin to carry out second task.The aforementioned operation flow process can be with reference to Fig. 2 B and related description thereof.
At the multi-task processor of the embodiment of the invention described above, after finishing the handling procedure of interrupt event, do not carry out task and switch and continue to carry out first task, up to the switching point instructions of carrying out to the first task.Because switching point instructions all is configured in the position of using system resource less (that is the register negligible amounts that keeps) in the first task, so when multi-task processor is carried out the switching point instructions to first task and need be carried out task when switching, it is also less that content is switched the register quantity of required backup.Though the configuration switching point instructions can influence system's usefulness slightly, can't cause obvious influence for global procedures on the execution time.By this, present embodiment can reduce multi-task processor and carry out the time of task switching and the power of consumption, and can reduce multi-task processor and carry out the hardware cost (capacity that for example stacks) that task is switched to be increased between a plurality of tasks.
Be noted that especially switching mark that the foregoing description carries can in be built in the register cell, also can in multi-task processor, be provided with in addition.The meaning of The built-in in register cell realizes switching mark for register and the storage space that the present invention can also utilize multi-task processor not use.In addition, though be placed in the survival register set of listings that each switching point instructions is required in the survival register tables 342 in the foregoing description, its implementation should be not limited with this.For example, survival register inventory may be encoding in the corresponding switching point instructions in other embodiments, make survival register inventory to be extracted by instruction fetch stage 310, and do not need from data-carrier store 341, to extract in addition survival register inventory 343 along with switching point instructions.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; those skilled in the art can do some changes and retouching under the premise without departing from the spirit and scope of the present invention, so protection scope of the present invention is as the criterion with claim of the present invention.
Claims (26)
1. a multi-task processor can be accepted the task assignment more than two, it is characterized in that this multi-task processor comprises:
Switching mark; And
Processing unit, in order to carry out being made up of this multi-task processor instruction set of task, wherein this multi-task processor instruction set comprises switching point instructions, and this switching point instructions is disconnected event handling instruction among this switching mark correspondence;
Wherein this processing unit is carried out the first task with at least one this switching point instructions; When interrupt event takes place, after this processing unit carries out the handling procedure of this interrupt event and need to judge whether task to switch and set this switching mark according to judged result, this processing unit promptly continues to carry out this first task, carries out this at least one switching point instructions in this first task until this processing unit.
2. multi-task processor as claimed in claim 1 is characterized in that this multi-task processor also comprises:
If this switching mark is set, promptly this processing unit is judged the switching of the task of need when carrying out the handling procedure of this interrupt event, and this processing unit promptly carries out the task switching and changes second task of execution; And
If this switching mark is not set, promptly this processing unit is when carrying out the handling procedure of this interrupt event, and judging does not need task to switch, and this processing unit then continues to carry out this first task.
3. multi-task processor as claimed in claim 2 is characterized in that this multi-task processor also comprises:
Survival register inventory is in order to write down the pairing survival register of this switching point instructions; The register of wherein surviving is that this processing unit is carried out when this switching point instructions and the task of need are switched the register of required storage backup; And
The survival register tables, its content comprises pairing this survival register inventory of each switching point instructions.
4. multi-task processor as claimed in claim 3 is characterized in that wherein this switching point instructions comprises the address to point to the pairing survival register of this switching point inventory; If this processing unit execution is set to this at least one switching point instructions and this switching mark, this processing unit then carries out the task switching and changes second task of execution; Wherein, this task switching comprises according to the pairing survival register of this at least one switching point instructions inventory, stores all survival registers.
5. multi-task processor as claimed in claim 4 is characterized in that wherein the storage location of this survival register inventory and this survival register tables is the data-carrier store of system.
6. multi-task processor as claimed in claim 4, the handling procedure that it is characterized in that this interrupt event that this processing unit wherein carries out comprises carries out task scheduling again; If this again the result of task scheduling represent that this processing unit needs task to switch, this processing unit is promptly set this switching mark; And if this again the result of task scheduling represent that this processing unit does not need task to switch, this processing unit is then reset or is removed this switching mark.
7. multi-task processor as claimed in claim 6, it is characterized in that wherein this again task scheduling comprise the relatively right of priority of this first task and this second task.
8. multi-task processor as claimed in claim 1 is characterized in that wherein this interrupt event comprises the outside of this processor or software interruption incident or hardware interrupts incident that inside takes place.
9. multi-task processor as claimed in claim 1 is characterized in that wherein this interrupt event comprises the timer event that the fixed cycle takes place.
10. multi-task processor as claimed in claim 1 is characterized in that wherein this switching point instructions is ending place of the subtask in this first task in the position of this first task.
11. multi-task processor as claimed in claim 1 is characterized in that wherein this switching point instructions is the less position of using system resource in this first task in the position of this first task.
12. multi-task processor as claimed in claim 1 is characterized in that wherein this switching point instructions is for satisfying the set task switching point of instantaneity demand in this first task in the position of this first task.
13. the target switching method of a multi-task processor is characterized in that described target switching method comprises:
Multi-task processor is carried out a first task, and wherein this first task has at least one switching point;
If interrupt event takes place, this multi-task processor is at the handling procedure of finishing this interrupt event and need to judge whether task to switch the back to continue to carry out this first task, carries out this at least one switching point to this first task up to this multi-task processor;
Need task to switch if the result of the handling procedure of this interrupt event represents this multi-task processor, when this multi-task processor was carried out to this at least one switching point, this multi-task processor carried out task and switches and change execution second task; And
Do not need task to switch if the result of the handling procedure of this interrupt event represents this multi-task processor, when this multi-task processor was carried out to this at least one switching point, this multi-task processor continued to carry out this first task.
14. the target switching method of multi-task processor as claimed in claim 13 is characterized in that wherein the handling procedure of this interrupt event comprises:
Carry out task scheduling again; And
According to this result of task scheduling again, determine whether task is switched.
15. the target switching method of multi-task processor as claimed in claim 14, it is characterized in that wherein this again task scheduling comprise the relatively right of priority of this first task and this second task.
16. the target switching method of multi-task processor as claimed in claim 13 is characterized in that wherein this interrupt event comprises the outside of this processor or software interruption incident or hardware interrupts incident that inside takes place.
17. the target switching method of multi-task processor as claimed in claim 13 is characterized in that wherein this interrupt event comprises the timer event that the fixed cycle takes place.
18. the target switching method of multi-task processor as claimed in claim 13 is characterized in that wherein this switching point is ending place of the subtask in this first task in the position of this first task.
19. the target switching method of multi-task processor as claimed in claim 13 is characterized in that wherein this switching point is the less position of using system resource in this first task in the position of this first task.
20. the target switching method of multi-task processor as claimed in claim 13 is characterized in that wherein this switching point is for satisfying the set task switching point of instantaneity demand in this first task in the position of this first task.
21. the target switching method of a multi-task processor is characterized in that described target switching method comprises:
Multi-task processor is carried out first task;
One incident takes place, and wherein this multi-task processor of this representations of events should carry out the task switching so that switch to second task of execution by carrying out this first task; And
This processor is postponed carrying out this task and is switched, and continues to carry out this first task, carries out changeable point to this first task until this multi-task processor, and footpath this task of row is switched to carry out this second task.
22. the target switching method of multi-task processor as claimed in claim 21 is characterized in that wherein this incident is outside or inner software or the hardware interrupts incident that takes place.
23. the target switching method of multi-task processor as claimed in claim 21 is characterized in that wherein this incident is the timer event that takes place the fixed cycle.
24. the target switching method of multi-task processor as claimed in claim 21 is characterized in that wherein this switching point is ending place of the subtask in this first task in the position of this first task.
25. the target switching method of multi-task processor as claimed in claim 21 is characterized in that wherein this is changeable in the position of this first task, is the less position of using system resource in this first task.
26. the target switching method of multi-task processor as claimed in claim 21 is characterized in that wherein this switching point is for satisfying the set task switching point of instantaneity demand in this first task in the position of this first task.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102438062A (en) * | 2010-09-29 | 2012-05-02 | 联想移动通信科技有限公司 | Method, device and mobile terminal for switching multiple tasks |
| CN103782272A (en) * | 2011-09-06 | 2014-05-07 | 马维尔国际贸易有限公司 | Switching tasks between heterogeneous cores |
| CN104572133A (en) * | 2015-02-06 | 2015-04-29 | 莉莉丝科技（上海）有限公司 | Method and equipment for executing operation of plurality of users in calculation task |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102438062A (en) * | 2010-09-29 | 2012-05-02 | 联想移动通信科技有限公司 | Method, device and mobile terminal for switching multiple tasks |
| CN102438062B (en) * | 2010-09-29 | 2014-12-24 | 联想移动通信科技有限公司 | Method, device and mobile terminal for switching multiple tasks |
| CN103782272A (en) * | 2011-09-06 | 2014-05-07 | 马维尔国际贸易有限公司 | Switching tasks between heterogeneous cores |
| CN103782272B (en) * | 2011-09-06 | 2017-03-01 | 马维尔国际贸易有限公司 | Switch task between isomery core |
| CN104572133A (en) * | 2015-02-06 | 2015-04-29 | 莉莉丝科技（上海）有限公司 | Method and equipment for executing operation of plurality of users in calculation task |
| CN104572133B (en) * | 2015-02-06 | 2020-05-08 | 上海莉莉丝科技股份有限公司 | Method and equipment for executing multi-user operation in computing task |
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