CN101667986B - Base band demodulating chip circuit based on orthogonal frequency division multiplexing - Google Patents
Base band demodulating chip circuit based on orthogonal frequency division multiplexing Download PDFInfo
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Abstract
The invention discloses a band base chip based on orthogonal frequency division multiplexing (OFDM), a merge module and a mixer module are added at an internal input interface of the existing band base chip, after being converted into digital signal by an analogue digital converter, the signal of a tuner uniforms input signals into one-way base band signals which transmits cophase components and orthogonal components alternately by the merge module and the mixer module in turn. In the invention, the band base chip based on OFDM has the advantages that the base band chip can adapt to the interfaces of various tuners and analogue digital converters, and the flexibility of the base band chip is improved.
Description
[technical field]
The invention relates to a kind of baseband chip, be meant a kind of baseband chip especially based on OFDM.
[background technology]
The standard of mobile digital multi-media broadcast is various, like the CMMB of China, and the T-DMB of Korea S, the DVB in Europe, the ISDB of Japan etc.The kind of interface of tuner and analog to digital converter also has much, and tuner mainly is divided into zero intermediate frequency and two kinds of schemes of Low Medium Frequency.The zero intermediate frequency scheme converts the signal into base band, divides two-way output in-phase component and orthogonal component signal; The Low Medium Frequency scheme converts the signal into Low Medium Frequency, has only one tunnel output signal, and baseband chip also will transform to base band with it through mixing.For the zero intermediate frequency scheme, need with twin-channel analog to digital converter respectively to the two paths of signals sampling of tuner, can be that two-way is parallel export to baseband chip in its output, also can be that the single channel that is mixed into two data of a clock cycle biography is exported to baseband chip; For the Low Medium Frequency scheme, only need sample to it with single pass analog to digital converter, directly single channel is exported to baseband chip.In addition, no matter be single channel or double-channel analog/digital transducer, data format also is divided into complement code and offset code pattern, and clock can be provided by baseband chip, also can be provided by tuner or external crystal-controlled oscillation.
Existing baseband chip generally can not be supported above-mentioned all tuners and analog to digital converter, therefore, when using existing baseband chip, in the selection of devices such as tuner and analog to digital converter, has certain limitation.
[summary of the invention]
Technical problem to be solved by this invention is to provide a kind of baseband chip based on OFDM that can support various tuners (Tuner) and analog to digital converter (ADC).
The present invention solves the problems of the technologies described above through following technical scheme: a kind of baseband chip based on OFDM; The signal of tuner becomes digital signal through analog to digital converter and inputs to baseband chip; Input interface place, inside at existing baseband chip has added merging module and frequency mixing module; After the signal of tuner becomes digital signal through analog to digital converter, be the single channel baseband signal of in-phase component and quadrature component alternate transmission through said merging module and frequency mixing module with the input signal unification successively.
Said merging module comprises asynchronous FIFO memory, the one 2 path multiplexer, register, the 22 path multiplexer and complement code submodule;
The data of outside input divide two-way to get into asynchronous FIFO memory and the one 2 path multiplexer simultaneously; Sheet is given the input clock of the clock of analog to digital converter as asynchronous FIFO outward; The baseband chip internal clocking is as the output clock of asynchronous FIFO, and the output of asynchronous FIFO memory also is input to the one 2 path multiplexer;
The sheet external clock is selected the selection signal of signal as the one 2 path multiplexer; The output of selecting the one 2 path multiplexer is the data of the outer input of sheet; Or the data of asynchronous FIFO memory output, like this, the output signal of the one 2 path multiplexer is by the unified baseband chip clock internal territory of arriving;
In order not lose data, baseband chip clock internal frequency need be greater than the outer clock frequency of baseband chip; Asynchronous FIFO memory begins output when fast expiring, when fast sky, stop output; The signal of control asynchronous FIFO memory output is simultaneously as the data useful signal, and subsequent module is only handled data when data are effective; If the data of the outer input of selection sheet are not promptly used asynchronous FIFO memory as the output of the one 2 path multiplexer, then the data useful signal is 1 always;
The output signal of the one 2 path multiplexer gets into register and the 22 path multiplexer simultaneously; The output of register also gets into the 22 path multiplexer; Two divided-frequency with the baseband chip internal clocking produces a homophase, quadrature index signal iq_index, with this signal and enable signal merge_en that merges module and the selection signal of the selection signal merge_sel that produces as the 22 path multiplexer, when the input data of the 22 path multiplexer are 2 the tunnel; The 22 path multiplexer is merged into 1 the tunnel with 2 road signals; When the input data were 1 the tunnel, the input data need be received that road of in-phase component, and merge_en is put 0; Then merge_sel is 0, then imports data and directly exports;
Data after merging through the 22 path multiplexer become the single channel baseband signal of in-phase component and quadrature component alternate transmission, pass through the unification of complement code submodule again and become the complement code form.
Said complement code submodule is that the highest order of data and offset code flag bit are carried out XOR, if the input data are complement code, then to join be 0 to the offset code flag bit; Data remain unchanged behind the XOR; If the input data are offset code, then to join be 1 to the offset code flag bit, and data become complement code behind the XOR.
Said frequency mixing module is on existing general frequency mixing module basis, to have increased by one 2 path multiplexer, the input and output of general frequency mixing module is connected on the input of 2 path multiplexers respectively.
Select whether will carry out mixing by the zero intermediate frequency marking signal,, then need not carry out mixing, directly will import data output,, then need carry out mixing, with the dateout output of general frequency mixing module if zero intermediate frequency is masked as 0 if zero intermediate frequency is masked as 1.
For the data after guaranteeing to merge always in-phase component preceding; Quadrature component after, baseband chip is exported to homophase that two divided-frequency and the inner two divided-frequency of the internal clocking (CLK) of analog to digital converter produce, quadrature index signal iq_index all can be through its whether negate of register controlled.
The interface of said baseband chip based on OFDM is 10, supports binary channels, has 20 input data line, respectively 10 of corresponding in-phase component with quadrature component 10.
The advantage that the present invention is based on the baseband chip of OFDM is: make baseband chip can adapt to the interface of various tuners (Tuner) and analog to digital converter (ADC), increased the flexibility of baseband chip.
[description of drawings]
Combine embodiment that the present invention is done further description with reference to the accompanying drawings.
Fig. 1 is the system block diagram that the present invention is based on the baseband chip use of OFDM.
Fig. 2 is the structured flowchart that the present invention is based on the merging module in the baseband chip of OFDM.
Fig. 3 is that the merging module that the present invention is based in the baseband chip of OFDM is carried out the sequential chart that two paths of data merges.
Fig. 4 is the structured flowchart that the present invention is based on the frequency mixing module in the baseband chip of OFDM.
[embodiment]
Seeing also Fig. 1, is the system block diagram that the present invention is based on the baseband chip use of OFDM.The zero intermediate frequency of tuner or Low Medium Frequency signal become digital signal through analog to digital converter and input to baseband chip.The present invention is based on the baseband chip of OFDM and the difference of existing baseband chip is: the input interface place, inside at existing baseband chip has added merging module and frequency mixing module; After the zero intermediate frequency of tuner or Low Medium Frequency signal become digital signal through analog to digital converter, the input signal of various schemes is unified the single channel baseband signal for in-phase component and quadrature component alternate transmission through the merging module and the frequency mixing module of baseband chip.
The bit wide of general each passage of analog to digital converter that uses of mobile digital multimedia broadcasting receiver mainly contains 8 and 10 two kinds; In order to guarantee receptivity; Baseband chip of the present invention is done interface by 10; Owing to support binary channels, so baseband chip has 20 input data line, 10 and 10 of quadrature component of the corresponding in-phase component of difference.
See also Fig. 2; Be the structured flowchart that the present invention is based on the merging module in the baseband chip of OFDM, this merging module comprises asynchronous FIFO (FIFO) memory, the one 2 path multiplexer (MUX2), register, the 22 path multiplexer (MUX2) and complement code submodule.
Those skilled in the art know; The clock of analog to digital converter can be provided by the inner or outside miscellaneous part of baseband chip; In order the analog to digital converter clock to be provided supporting pieces outward, added an asynchronous FIFO (FIFO) memory at the input interface place that merges module.Give analog to digital converter if produce clock in the sheet, the clock that then produces is the two divided-frequency of the clock of the inner usefulness of baseband chip; If the clock of analog to digital converter is to be provided by the outside, the clock frequency that then need guarantee chip internal is greater than the outer clock frequency of sheet.
Among Fig. 2, adc_offchip_in is the data of the outer input of sheet, high ten corresponding in-phase components, low ten corresponding quadrature components; Clk_offchip is the clock that sheet is given analog to digital converter outward; Clk is the baseband chip internal clocking, and offchip_clk_sel selects signal for the sheet external clock; Data_in is the output signal of the one 2 path multiplexer; Merge_sel is as the selection signal of 2 road data_in signals; Merge_data_out is for merging the data output of module.
The operation principle of this merging module is described below:
The data adc_offchip_in of the outer input of sheet divides two-way to get into asynchronous FIFO memory and the one 2 path multiplexer simultaneously; Sheet is given the input clock of the clock clk_offchip of analog to digital converter as asynchronous FIFO outward, and baseband chip internal clocking clk is as the output clock of asynchronous FIFO memory; The output of asynchronous FIFO memory also is input to the one 2 path multiplexer;
The sheet external clock is selected the selection signal of signal offchip_clk_sel as the one 2 path multiplexer (MUX2), and the output of selecting the one 2 path multiplexer is the data of the outer input of sheet, or the data of asynchronous FIFO memory output; Like this, the output signal data_in of the one 2 path multiplexer is by the unified baseband chip clock internal territory of arriving;
In order not lose data, baseband chip clock internal frequency need be greater than the outer clock frequency of baseband chip; Asynchronous FIFO memory begins output when fast expiring, when fast sky, stop output; The signal of control asynchronous FIFO memory output is simultaneously as the data useful signal, and subsequent module is only handled data when data are effective; If the data of the outer input of selection sheet are not promptly used asynchronous FIFO memory as the output of the one 2 path multiplexer, then the data useful signal is 1 always;
The output signal data_in of the one 2 path multiplexer gets into register and the 22 path multiplexer simultaneously, and the output of register also gets into the 22 path multiplexer; Two divided-frequency with the baseband chip internal clocking produces a homophase, quadrature index signal iq_index; With this signal and enable signal merge_en that merges module and the selection signal of the selection signal merge_sel that produces as the 22 path multiplexer; When the input data of the 22 path multiplexer were 2 the tunnel, the 22 path multiplexer was merged into 1 the tunnel with 2 road signals, when the input data are 1 the tunnel; The input data need be received that road of in-phase component; Merge_en is put 0, and then merge_sel is 0, then imports data and directly exports;
For the data after guaranteeing to merge always in-phase component preceding; Quadrature component after, baseband chip is exported to homophase that two divided-frequency and the inner two divided-frequency of the internal clocking (CLK) of analog to digital converter produce, quadrature index signal iq_index all can be through its whether negate of register controlled.
Data through after the 22 path multiplexer (MUX2) merging become 10, and unification becomes the complement code form through the complement code submodule again, and the complement code submodule is exactly that the highest order of data and offset code flag bit are carried out XOR; If the input data are complement code; Then to join be 0 to the offset code flag bit, and data remain unchanged behind the XOR, if the input data are offset code; Then to join be 1 to the offset code flag bit, and data become complement code behind the XOR.
Seeing also Fig. 3, is that the merging module that the present invention is based in the baseband chip of OFDM is carried out the sequential chart that two paths of data merges.
Said frequency mixing module among the present invention is as shown in Figure 4, and input is an input signal, and output is the output signal, and zero_if_flag is the zero intermediate frequency marking signal.It is exactly on existing general frequency mixing module basis, to have increased by one 2 path multiplexer, and the input and output of general frequency mixing module are connected on the input of 2 path multiplexers respectively, is selected whether will carry out mixing by the zero intermediate frequency marking signal.If zero intermediate frequency is masked as 1, then need not carry out mixing, directly will import data output; If zero intermediate frequency is masked as 0, then need carry out mixing, with the dateout output of general frequency mixing module.General frequency mixing module is exactly that the input data are taken advantage of the inner digital local oscillation signal that generates of baseband chip.
Generally speaking,, then, merge_en is put 0, simultaneously zero_if_flag is put 0, to enable frequency mixing module as long as one tunnel input need not merge if external tuner is the non-zero if scheme; If external tuner is the zero intermediate frequency scheme and divides the two-way input, then need merge, merge_en is put 1, simultaneously zero_if_flag is put 1, do not carry out mixing; If external tuner is the zero intermediate frequency scheme and has been merged into one tunnel input; Then need not merge, merge_en is put 0, simultaneously zero_if_flag put 1; Do not carry out mixing, also will be according to the whether negate of the sequential of input signal configuration iq_index signal; If analog to digital converter output is the complement code form, then to join be 0 to the offset code flag bit; If analog to digital converter output is the offset code form, then to join be 1 to the offset code flag bit; If the clock of analog to digital converter is provided by baseband chip, then offchip_clk_sel being joined is 0, lets data directly import processing; If the clock of analog to digital converter is provided by the outside, then offchip_clk_sel being joined is 1, handles after letting data be transformed into the chip internal clock zone through asynchronous FIFO again.
The structure of existing baseband chip of being mentioned among the present invention and general frequency mixing module all can be used the structure of existing various common baseband chips and general frequency mixing module.Tuner and analog to digital converter can be two independent devices, also can be the individual devices that lumps together.
Claims (5)
1. baseband chip based on OFDM; The signal of tuner becomes digital signal through analog to digital converter and inputs to baseband chip; It is characterized in that: the input interface place, inside at existing baseband chip has added merging module and frequency mixing module; After the signal of tuner becomes digital signal through analog to digital converter, be the single channel baseband signal of in-phase component and quadrature component alternate transmission through said merging module and frequency mixing module with the input signal unification successively;
Said merging module comprises asynchronous FIFO memory, the one 2 path multiplexer, register, the 22 path multiplexer and complement code submodule;
The data of the outer input of sheet divide two-way to get into asynchronous FIFO memory and the one 2 path multiplexer simultaneously; Sheet is given the input clock of the clock of analog to digital converter as asynchronous FIFO outward; The baseband chip internal clocking is as the output clock of asynchronous FIFO, and the output of asynchronous FIFO memory also is input to the one 2 path multiplexer;
The sheet external clock is selected the selection signal of signal as the one 2 path multiplexer; The output of selecting the one 2 path multiplexer is the data of the outer input of sheet; Or the data of asynchronous FIFO memory output, like this, the output signal of the one 2 path multiplexer is by the unified baseband chip clock internal territory of arriving;
In order not lose data, baseband chip clock internal frequency need be greater than the outer clock frequency of baseband chip; Asynchronous FIFO memory begins output when fast expiring, when fast sky, stop output; The signal of control asynchronous FIFO memory output is simultaneously as the data useful signal, and subsequent module is only handled data when data are effective; If the data of the outer input of selection sheet are not promptly used asynchronous FIFO memory as the output of the one 2 path multiplexer, then the data useful signal is 1 always;
The output signal of the one 2 path multiplexer gets into register and the 22 path multiplexer simultaneously; The output of register also gets into the 22 path multiplexer; Two divided-frequency with the baseband chip internal clocking produces a homophase, quadrature index signal iq_index, with this signal and enable signal merge_en that merges module and the selection signal of the selection signal merge_sel that produces as the 22 path multiplexer, when the input data of the 22 path multiplexer are 2 the tunnel; The 22 path multiplexer is merged into 1 the tunnel with 2 road signals; When the input data were 1 the tunnel, the input data need be received that road of in-phase component, and merge_en is put 0; Then merge_sel is 0, then imports data and directly exports;
Data after merging through the 22 path multiplexer become the single channel baseband signal of in-phase component and quadrature component alternate transmission, pass through the unification of complement code submodule again and become the complement code form;
Said frequency mixing module is on existing general frequency mixing module basis, to have increased by one 2 path multiplexer, the input and output of general frequency mixing module is connected on the input of 2 path multiplexers respectively.
2. the baseband chip based on OFDM as claimed in claim 1; It is characterized in that: said complement code submodule is that the highest order of data and offset code flag bit are carried out XOR, if the input data are complement code, then to join be 0 to the offset code flag bit; Data remain unchanged behind the XOR; If the input data are offset code, then to join be 1 to the offset code flag bit, and data become complement code behind the XOR.
3. the baseband chip based on OFDM as claimed in claim 1; It is characterized in that: select whether will carry out mixing by the zero intermediate frequency marking signal,, then need not carry out mixing if zero intermediate frequency is masked as 1; Directly will import data output; If zero intermediate frequency is masked as 0, then need carry out mixing, with the dateout output of general frequency mixing module.
4. the baseband chip based on OFDM as claimed in claim 1 is characterized in that: said baseband chip is exported to homophase that the two divided-frequency of two divided-frequency and internal clocking of the internal clocking of analog to digital converter produces, quadrature index signal iq_index all through its whether negate of register controlled.
5. the baseband chip based on OFDM as claimed in claim 1; It is characterized in that: the interface of said baseband chip based on OFDM is 10; Support binary channels, have 20 input data line, 10 and 10 of quadrature component of the corresponding in-phase component of difference.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1345492A (en) * | 1999-02-24 | 2002-04-17 | 艾比奎蒂数字公司 | Audio blend method, transmitter and receiver for AM and FM in band on channel digital audio broadcasting |
| CN1933348A (en) * | 2006-10-10 | 2007-03-21 | 东南大学 | Zero intermediate frequency receiver and receiving method in electric line carrier communication |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1345492A (en) * | 1999-02-24 | 2002-04-17 | 艾比奎蒂数字公司 | Audio blend method, transmitter and receiver for AM and FM in band on channel digital audio broadcasting |
| CN1933348A (en) * | 2006-10-10 | 2007-03-21 | 东南大学 | Zero intermediate frequency receiver and receiving method in electric line carrier communication |
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Address after: 350000 Fuzhou Gulou District, Fujian, software Avenue, building 89, No. 18 Patentee after: FUZHOU ROCKCHIP ELECTRONICS CO., LTD. Address before: 350011, building 1, building 550, No. 601, industrial road, West Suburbs, Hongshan Town, Gulou District, Fujian, Fuzhou Patentee before: Fuzhou Rockchip Semiconductor Co., Ltd. |
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Address after: 350000 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee after: Ruixin Microelectronics Co., Ltd Address before: 350000 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee before: Fuzhou Rockchips Electronics Co.,Ltd. |