CN101662275A - Control method for alternating current solid-state power switch - Google Patents
Control method for alternating current solid-state power switch Download PDFInfo
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- CN101662275A CN101662275A CN200810042119A CN200810042119A CN101662275A CN 101662275 A CN101662275 A CN 101662275A CN 200810042119 A CN200810042119 A CN 200810042119A CN 200810042119 A CN200810042119 A CN 200810042119A CN 101662275 A CN101662275 A CN 101662275A
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Abstract
The invention discloses a control method for an alternating current solid-state power switch. The method comprises two solid-state switch MOSFETs which are in back-to-back connection, a load current polarity sampling circuit, a line voltage polarity sampling circuit, a D-type trigger, a logic gate circuit and an isolated power supply; and the control method is characterized by comprising the following steps: detecting the changes of the voltage polarity or the current polarity of a load circuit; latching opening/closing control signals by the D-type trigger; and switching on or off the two solid-state switches so as to switch on or off a power supply circuit of an alternating current load. The control method for the alternating current solid-state power switch has the advantages of achieving the switch-on and switch-off controls of an alternating current electric load and having the characteristics of one triggering, natural zero-crossing switch-on and switch-off, no generation of electromagnetic interferences, and low switch power consumption.
Description
Technical field
The present invention relates to a kind of control method that is used for the solid-state power switch of alternating-current electric load control.
Background technology
In current Electromechanical Control method and alternating-current system, control generally has dual mode to the switch of alternating-current electric load: a kind of is by traditional electromechanical electromagnetic relay, circuit breaker, contactor or mechanical electric switch; Another kind is to use solid state power electronic switch such as solid-state relay.In ac power supply system, in order to reduce the electromagnetic interference of switching on and off of solid-state power switch, require control method to have the function that makes solid-state power switch when the circuit voltage zero-cross, connect and disconnect during the line current zero passage to electric power system and environment.The solid-state power switch that generally uses at present is bidirectional triode thyristor, is equipped with special-purpose zero passage detection dedicated devices.Connect owing to this method exists controllable silicon that voltage drop is big, oneself power consumption is many, all need after each zero passage once to trigger and because of the time-delay reason of circuits for triggering does not have the disadvantage of the aspects such as zero passage connection of real meaning, so it has bigger limitation in the field that the middle low power load is controlled.
Summary of the invention
The present invention relates to a kind of control method of alternating current solid-state power switch, solved the controllable silicon that exists in the prior art and connected problems such as voltage drop is big, oneself power consumption is many, triggering times is many.The invention provides a kind of control method of alternating current solid-state power switch, comprise signal input end, two solid-state switch MOSFET, load current polarity sample circuit, load voltage polarity sample circuit, two D flip-flops, current sampling resistor and insulating power supplies, it is characterized in that, comprise the steps:
1) two solid-state switch MOSFET is connected on the AC power inlet side, makes the source S of two solid-state switch MOSFET connect together by current sampling resistor;
2) drain D with a solid-state switch MOSFET is connected with AC power inlet side Vin, and this solid-state switch MOSFET is negative control switch, controls it by the negative drive signal Drv-of controlling D flip-flop output and is switched on or switched off; The drain D of another solid-state switch MOSFET is connected with power take-off Vout, and this solid-state switch MOSFET controls it by the drive signal Drv+ of just controlling D flip-flop output and is switched on or switched off for just controlling switch; When the drive signal Drv-of just controlling D flip-flop and the output of negative control D flip-flop and Drv+ are zero level, just controlling switch and negative control switch all is in off state, the reverse barrier properties of the parasitic diode of their inside makes load circuit be in off-state; The two ends of bi-directional voltage transient suppressor are connected with the drain electrode of just controlling switch with negative control switch respectively;
3) be connected on the source S of negative control switch the auxiliary excitation power supply that insulating power supply is exported, signal input end is connected respectively to just controls D flip-flop and negative control D flip-flop FPDP, the switch controlling signal of signal input end output, the control load loop switches on and off;
4) the polarity of voltage sample circuit detects the alternating voltage polarity on ac power supply circuit or the solid-state power switch loop, when this AC voltage difference is timing, and output signal V+; When this AC voltage difference when negative, output signal V-;
5) the current polarity sample circuit detects the polarity of load circuit electric current, obtains the polarity of load circuit electric current by gathering voltage difference on the sampling resistor, when this voltage difference is the timing load circuit sense of current for just, and output signal I+; When this voltage difference when negative the load circuit sense of current for negative, output signal I-;
6) when the polarity of the voltage of the electric current of load circuit or electric power loop changes, the V+ of output, I+ signal are through logic gates output CLK+, and CLK+ is output into drive signal Drv+ to the switch controlling signal of just controlling on the D flip-flop FPDP D to just controlling switch; The V-of output, I-signal are through logic gates output CLK-, and CLK-is output into drive signal Drv-to the switch controlling signal on the negative control D flip-flop FPDP D to negative control switch;
7) the Drv+ signal becomes high level, makes that just to control switch open-minded, and the Drv+ signal becomes low level, makes just to control switch and close, and the Drv-signal becomes high level, makes negative control switch open-minded, and the Drv-signal becomes low level, and negative control switch cuts out.
The described switch of just controlling is an emos, and described just the control in switch and the negative control switch is respectively equipped with parasitic diode.Described negative control switch is an emos.Described logic gates can be a multiplier and an adder.Described logic gates can be an adder.
The invention has the advantages that: the present invention realizes once the effect that triggering, natural zero-crossing turn on and off by the control that switches on and off to alternating-current electric, and it is little, low in energy consumption disturbed by other factors.
Description of drawings
Accompanying drawing 1 is the control principle block diagram of the embodiment of the invention 1;
Accompanying drawing 2 is control waveform figure of the embodiment of the invention 1 control resistive load;
Accompanying drawing 3 is control waveform figure of the embodiment of the invention 1 control capacitive load;
Accompanying drawing 4 is control waveform figure of the embodiment of the invention 1 control inductive load;
Accompanying drawing 5 is control principle block diagrams of embodiments of the invention 2;
Accompanying drawing 6 is control waveform figure of embodiments of the invention 2 control inductive loads.
Embodiment
Below in conjunction with drawings and Examples the present invention is elaborated.
A kind of control method of alternating current solid-state power switch, comprise signal input end 1, two solid-state switch MOSFET, load current polarity sample circuit 2, load voltage polarity sample circuit 3, two D flip-flops, current sampling resistor 4 and insulating power supplies 5, it is characterized in that, comprise the steps:
1) two solid-state switch MOSFET is connected on the inlet side of AC power 6, makes the source S of two solid-state switch MOSFET connect together by current sampling resistor 4;
2) drain D with a solid-state switch MOSFET is connected with the inlet side Vin of AC power 6, and this solid-state switch MOSFET is negative control switch 7, controls it by the negative drive signal Drv-of controlling D flip-flop 8 outputs and is switched on or switched off; The drain D of another solid-state switch MOSFET is connected with AC load 9 (being power take-off Vout), and this solid-state switch MOSFET controls it by the drive signal Drv+ of just controlling D flip-flop 11 outputs and is switched on or switched off for just controlling switch 10; When the drive signal Drv-of just controlling D flip-flop and 8 outputs of negative control D flip-flop and Drv+ are zero level, just controlling switch and negative control switch all is in off state, the parasitic diode 12 reverse barrier properties of their inside make load circuit be in off-state; The two ends of bi-directional voltage transient suppressor 13 are connected with the drain electrode of just controlling switch with negative control switch respectively;
3) be connected on the source S of negative control switch the auxiliary excitation power supply that insulating power supply 5 is exported, signal input end is connected respectively to just controls D flip-flop and negative control D flip-flop FPDP, the switch controlling signal of signal input end output, the control load loop switches on and off;
4) polarity of voltage sample circuit 3 detects the alternating voltage polarity on ac power supply circuits or the solid-state power switch loop, when this AC voltage difference is timing, and output signal V+; When this AC voltage difference when negative, output signal V-;
5) the current polarity sample circuit detects the polarity of load circuit electric current, obtains the polarity of load circuit electric current by gathering voltage difference on the sampling resistor, when this voltage difference is the timing load circuit sense of current for just, and output signal I+; When this voltage difference when negative the load circuit sense of current for negative, output signal I-;
6) when the polarity of the voltage of the electric current of load circuit or electric power loop changes, the V+ of output, I+ signal are through logic gates output CLK+, and CLK+ is output into drive signal Drv+ to the switch controlling signal of just controlling on the D flip-flop FPDP D to just controlling switch; The V-of output, I-signal are through logic gates output CLK-, and CLK-is output into drive signal Drv-to the switch controlling signal on the negative control D flip-flop FPDP D to negative control switch;
7) the Drv+ signal becomes high level, makes that just to control switch open-minded, and the Drv+ signal becomes low level, makes just to control switch and close, and the Drv-signal becomes high level, makes negative control switch open-minded, and the Drv-signal becomes low level, and negative control switch cuts out.
In the operating process that load circuit is opened or closed, divide secondary respectively two solid-state switch MOSFET to be opened or shutoff operation.For the first time to a certain solid-state switch MOSFET carry out connect or shutoff operation after half AC power in the cycle, the state that is switched on or switched off of load circuit can not change, and is maintained to the voltage or the current over-zero time point of load circuit.When for the second time another solid-state switch MOSFET being carried out connection or shutoff operation, change has taken place in the state that is switched on or switched off of load circuit, promptly becomes disconnection or becomes connection from disconnection from connection.
The described switch of just controlling is an emos.Described negative control switch is an emos.Emos (Metal-Oxide Semiconductor Field-Effect Transistor) abbreviates MOSFET as.The two ends of bi-directional voltage transient suppressor are connected with the drain electrode of just controlling switch with negative control switch respectively, and MOSFET is worked the effect of protecting;
The drain D connection AC power inlet side Vin of negative control switch, being switched on or switched off of control switch born in the drive signal Drv-control of negative control D flip-flop output.The drain D of just controlling switch connects power take-off Vout, and switch connection or disconnection are just being controlled in the drive signal Drv+ control of just controlling D flip-flop output.When the drive signal Drv-of just controlling D flip-flop and the output of negative control D flip-flop and Drv+ are zero level, just controlling switch and negative control switch all is in off state, the parasitic diode of their inside is barrier properties in opposite directions, makes load circuit be in off-state.
Just controlling the output port of D flip-flop is connected with the grid of just controlling switch; the output port of negative control D flip-flop is connected with the grid of negative control switch; just controlling the drain electrode of switch and the drain electrode of negative control switch and be connected with the two ends of bi-directional voltage transient controller respectively, the bi-directional voltage transient suppressor plays protection MOSFET effect.
Just controlling the source electrode of switch and the source electrode of negative control switch and be connected with the two ends of current sampling resistor respectively, be connected on the source electrode of negative control switch insulating power supply, be connected on the source S of MOSFET the auxiliary excitation power supply of insulating power supply output.Described logic gates can be an adder, also can be the combination of a multiplier and an adder.Described just the control in switch and the negative control switch is respectively equipped with parasitic diode.Described line voltage distribution polarity sample circuit module has an end ground connection.
The specific embodiment design circuit is as follows:
Signal input end is set, is used to import the ON/OFF control signal; Insulating power supply is set;
Be provided with and just control switch and negative control switch, be connected on the source electrode of negative control switch insulating power supply, AC power is connected with the drain electrode of negative control switch, and the drain electrode of just controlling switch is by AC load ground connection;
Bi-directional voltage transient controller, current sampling resistor and load current polarity sample circuit module are set just controlling between switch and the negative control switch, the two ends of bi-directional voltage transient controller are connected with the drain electrode of the drain electrode of just controlling switch with negative control switch respectively, the two ends of current sampling resistor are connected with the source electrode of the source electrode of just controlling switch with negative control switch respectively, and load current polarity sample circuit module is connected with the source electrode of the source electrode of just controlling switch with negative control switch respectively;
Be provided with and just control D flip-flop and negative control D flip-flop, described FPDP and the negative FPDP of controlling D flip-flop of just controlling D flip-flop is connected with signal input end respectively, just controlling the output port of D flip-flop and be connected with the grid of just controlling switch, the output port of negative control D flip-flop is connected with the grid of negative control switch;
Line voltage distribution polarity sample circuit module and load current polarity sample circuit module are set, line voltage distribution polarity sample circuit module is connected with AC power, line voltage distribution polarity sample circuit detects the alternating voltage polarity (as accompanying drawing 1 embodiment 1) between AC power inlet side Vin and the alternating current seedbed, perhaps detects the alternating voltage polarity (as accompanying drawing 5 embodiment 2) between AC power inlet side Vin and the AC power output Vout;
Fig. 1 is the control principle block diagram of the embodiment of the invention 1.
Just controlling the source electrode of switch and the source electrode of negative control switch is connected with load current polarity sample circuit module respectively, load current polarity sample circuit module is connected with the input of two logic gates respectively, the output of two logic gates is connected with the interface clock signal of just controlling D flip-flop and is connected with the interface clock signal of negative control D flip-flop, AC power is connected with line voltage distribution polarity sample circuit module, and line voltage distribution polarity sample circuit module is connected with the input of two logic gates respectively.
Polarity of voltage sample circuit module detects the polarity of ac power supply circuit voltage, when alternating voltage Vin is a positive polarity, and output signal V+; Voltage Vin is a negative polarity, output signal V-.The current polarity sample circuit detects the polarity of load circuit electric current, by gathering the polarity of voltage difference (Va-Vb) the acquisition load circuit electric current on the sampling resistor.When the load circuit sense of current be timing (be Va＞Vb), output signal I+; As the load circuit sense of current (Va＜Vb), output signal I-when negative.
Described FPDP and the negative FPDP of controlling D flip-flop of just controlling D flip-flop is connected with the ON/OFF control signal respectively, and the triggering hour hands signal CLK of D flip-flop is that the high level rising edge triggers.When the polarity of the electric current of load circuit or line voltage distribution changes, V+, the I+ of output or V-, I-signal are through logic gates output CLK+ or CLK-, the ON/OFF control signal on its corresponding D D-flip flop FPDP D is output into drive signal Drv+ for CLK+ or CLK-and Drv-is controlled switch MOS FET to just controlling switch MOS FET or bearing, to reach the purpose that is switched on or switched off load circuit.
In embodiment 1,
CLK+＝I++V+·I-
CLK-＝I-+V-·I+
In expression formula, V+ and V-are suppressed when I-and I+ are arranged, and can guarantee when capacitive or inductive load, and under the dephased situation of electric current and voltage, CLK+ and CLK-are only in the zero current time trigger.
The assumed load loop is in off-state, and at a time, the ON/OFF control signal is changed to logic high, and purpose is that load circuit is connected in requirement.According to the requirement that no-voltage is connected, obtain the conversion opportunity of alternating current solid-state power switch by the polarity of voltage that detects load circuit.The polarity of AC supply voltage changes in time, supposes that polarity becomes negative polarity by positive polarity, and this moment, the polarity of voltage sample circuit was exported the V-signal, and load circuit does not also have electric current, i.e. I+=I-=0.CLK-will produce a high trigger pulses along with the V-signal changes, the rising edge of this trigger impulse makes the high level on the FPDP D that bears the control D flip-flop latch and export to its output port Q and goes up formation Drv-signal, the Drv-signal becomes high level, makes negative control switch MOS FET open-minded.Because this moment, supply voltage was a negative polarity, and it is also not open-minded just to control switch MOS FET, so although negative control switch MOS FET is open-minded, the load circuit of this moment does not have electric current to be passed through.Through the frequency period of half AC power, polarity of voltage changes, and becomes positive polarity from negative polarity, i.e. Vin＞Vout, and load circuit just begins to have forward current.Electric current from the AC power inlet side through the D-S raceway groove of negative control switch MOS FET (going up half period), sampling resistor constantly by open-minded, just controlling switch MOS FET built-in parasitic diode to Vout, the inflow AC load is to exchanging power supply ground.And then, forward current in this load circuit forms voltage difference (Va-Vb) and is detected by the current polarity sample circuit on sampling resistor, and output forward current signal I+, the I+ signal produces the CLK+ signal through logic gates, CLK+ makes the high level on the FPDP D of just controlling D flip-flop latch and export to its output port Q and goes up formation Drv+ signal, the Drv+ signal becomes high level, makes that just to control switch MOS FET open-minded.Because the D-S raceway groove of just controlling switch MOS FET by open-minded, was flowed through originally and is just being controlled electric current in the built-in parasitic diode of switch MOS FET and just be transferred to from the D-S raceway groove of just controlling switch and flow through.Because the resistance value between the D-S raceway groove is very little, so the power consumption of electric current on the D-S raceway groove is also very little.So far, just controlling switch and negative control switch has all finished and has opened operation, as long as the ON/OFF control signal remains logic high, Drv+ and the Drv-of just controlling D flip-flop and the output of negative control D flip-flop can not change, it is lasting open-minded with negative control switch just to control switch, and load circuit keeps normal on-state.
Through after the some time, need the disconnecting consumers loop, just the ON/OFF control signal is changed into logic low.This logic low is input on the FPDP D of just controlling and bear the control D flip-flop.According to the requirement of zero-current switching, obtain the conversion opportunity of alternating current solid-state power switch by the current polarity that detects load circuit.Promptly only when I+ or I-zero passage, just to carry out signal and pass and replace, logic gates wants to suppress the influence (if any) of V+ and V-, and at this moment, CLK+ and CLK-will be with the variations of I+ and I-.Suppose that current polarity becomes positive polarity from negative polarity after the ON/OFF control signal is changed into logic low, current polarity sample circuit output this moment I+ signal, the I+ signal makes the CLK+ signal effective.The rising edge of CLK+ makes the low level on the FPDP D of just controlling D flip-flop latch and export to its output port Q and goes up formation Drv+ signal, and the Drv+ signal becomes low level, makes just to control switch MOS FET disconnection, and the D-S raceway groove of just controlling switch is closed.Because electric current this moment is a forward current, under the effect of load circuit voltage, this forward current just is transferred to the parasitic diode of just controlling in the switch by the buttoned-up D-S raceway groove of just controlling switch, makes the electric current in the load circuit continue to keep conducting.As time goes on this electric current can reduce gradually, is zero at last.When electric current when original variation tendency requires to produce the negative polarity electric current, be closed owing to just controlling the D-S raceway groove of switch, its inner parasitic diode has stopped the negative polarity electric current, therefore can not form negative current, load circuit is that zero back keeps zero current at electric current, promptly is closed.The negative voltage of ac circuit is fallen buttoned-up and is just being controlled on the switch at this moment, and polarity of voltage sample circuit output negative voltage V-signal, V-signal make CLK-signal effectively (this moment, I+ and I-were zero).Negative control D flip-flop is under the effect of CLK-signal, and the low level on its FPDP D is latched and exports to its output port Q and goes up formation Drv-signal, and the Drv-signal becomes low level, and negative control switch MOS FET is disconnected, and the negative D-S raceway groove of controlling switch is closed.So far, just control switch and negative control switch and all closing and finish, finishing the opening operation of load circuit.
Among the present invention, alternating current solid-state power switch is made up of 2 enhancement mode MOSFET solid-state switch, polarity of voltage sample circuit and current polarity sample circuits that connect back-to-back.According to the variation of load circuit voltage or current polarity, latch the ON/OFF control signal by D flip-flop, open or close 2 solid-state switch MOSFET successively with the time difference in half AC power cycle.
In the operating process that load circuit is opened or closed, divide and respectively 2 solid-state switch MOSFET are opened or shutoff operation for 2 times.The 1st time to a certain solid-state switch MOSFET carry out connect or shutoff operation after half AC power in the cycle, the state that is switched on or switched off of load circuit can not change, and is maintained to the voltage or the current over-zero time point of load circuit.The 2nd time another solid-state switch MOSFET carry out connected or during shutoff operation, change has taken place the state that is switched on or switched off of load circuit, promptly become and disconnect or become connection from disconnection from connection.
Solid-state switch MOSFET opening or closing, and is not to be both generation with being switched on or switched off of the load circuit of its control.Being switched on or switched off of load circuit is to finish in voltage or current polarity at load circuit (being zero passage) time that changes.By the D-S raceway groove of 2 solid-state switch MOSFET being controlled and is utilized the unilateal conduction characteristic of their endophyte diodes, load circuit is connected when voltage zero-cross naturally, naturally end when current over-zero, load circuit can not produce peak current and electromagnetic interference.
Alternating current solid-state power switch of the present invention switch on and off control method, each power switch is only once triggered, just controlling switch and negative control switch successively opens or cuts out.Utilize voltage or the alternation characteristic of electric current and the unilateal conduction characteristic of solid-state switch MOSFET endophyte diode of alternating current circuit, make alternating current solid-state power switch satisfy the requirement that no-voltage is connected, zero current disconnects.
Fig. 2 is the control waveform figure of embodiment 1 control resistive load.
Vth+, Vth-are the detection threshold of polarity of voltage sample circuit; Ith+, Ith-are the detection threshold of current polarity sample circuit.The electric current of load circuit and voltage homophase, load current is started from scratch, and changes by sine wave curve, finishes during current over-zero.V+ and V-cyclic variation; CLK+ and CLK-cyclic variation; Change in Drv+ and the Drv-frequency period after the ON/OFF signal changes, in the time period that load switches on and off, remain unchanged.
Fig. 3 is the control waveform figure of embodiment 1 control capacitive load.
The electric current of load circuit is ahead of supply voltage.Because load circuit is to connect when voltage is zero, and changes by sine wave curve, so capacitive load currents is started from scratch, after the minimal tour current charges, change by sine wave curve, finish during current over-zero.Can not the hold period variable condition in CLK+ and the CLK-frequency period after when the ON/OFF signal changes; Change in Drv+ and the Drv-frequency period after the ON/OFF signal changes, in the time period that load switches on and off, remain unchanged.
Fig. 4 is the control waveform figure of embodiment 1 control inductive load.
The electric current of load circuit lags behind supply voltage.Because load circuit is to connect when voltage is zero, and changes by sine wave curve, so the inductive load electric current is started from scratch, after the rising of minimal tour electric current, change by sine wave curve, finish during current over-zero.Can not the hold period variable condition in CLK+ and the CLK-frequency period after when the ON/OFF signal changes; Change in Drv+ and the Drv-frequency period after the ON/OFF signal changes, in the time period that load switches on and off, remain unchanged.
Fig. 5 is the control principle block diagram of embodiments of the invention 2.
The difference of embodiment 2 and embodiment 1 is that line voltage distribution polarity sample circuit detects is voltage difference (Vin-Vout) between Vin and the Vout.Polarity of voltage sample circuit output signal V+ when Vin＞Vout; Polarity of voltage sample circuit output signal V-when Vin＜Vout.The logical expression of CLK+ and CLK-is:
CLK+＝I++V+
CLK-＝I-+V-
In embodiment 2, a common recognition is: the impedance between 2 of Vin and the Vout or very big (when load circuit disconnects), or very little (when load circuit is connected), so, when being arranged, I+ just do not have V+; When being arranged, V+ just do not have I+.In like manner I-and V-also are mutual exclusions.In load circuit connection process, the response first time of CLK+ or CLK-is changed by polarity of voltage and causes, response for the second time is that the electric current variation causes; In load circuit disconnection process, the response first time of CLK+ or CLK-is changed by current polarity and causes that response is that change in voltage causes for the second time.
The assumed load loop is in off-state, and at a time, the ON/OFF control signal is changed to logic high, and purpose is that the AC load loop is connected in requirement.According to the requirement that no-voltage is connected, the conversion moment of obtaining alternating current solid-state power switch by the polarity of voltage that detects load circuit.Because load circuit is in off-state, AC supply voltage is all fallen at negative control switch MOS FET and is just being controlled on the switch MOS FET, and its voltage difference (Vin-Vout) is exactly the moment that the AC load loop is connected when being zero.Suppose that voltage difference polarity becomes negative polarity by positive polarity, i.e. Vin＜Vout, polarity of voltage sample circuit output this moment V-signal, and load circuit does not also have electric current, i.e. I+=I-=0.The V-signal produces a high trigger pulses CLK-through logic sum gate, the rising edge of this trigger impulse makes the high level on the FPDP D that bears the control D flip-flop latch and export to its output port Q and goes up formation Drv-signal, the Drv-signal becomes high level, makes negative control switch MOS FET (1) open-minded.Since this moment Vin＜Vout, and the D-S raceway groove of just controlling switch MOS FET does not also open and its built-in parasitic diode oppositely ends, so although negative control switch MOS FET is open-minded, the AC load loop of this moment does not have electric current and passes through.Through the frequency period of half AC power, polarity of voltage changes, i.e. Vin＞Vout, and load circuit just begins to have forward current.Electric current from AC power inlet side Vin through the D-S raceway groove (open-minded) of negative control switch MOS FET, sampling resistor, just controlling switch MOS FET built-in parasitic diode to Vout, the inflow AC load is to exchanging power supply ground.And then, the forward current in this load circuit forms voltage difference (Va-Vb) and is detected by the current polarity sample circuit on the two ends of sampling resistor a point and b point, and output forward current signal I+; Because the D-S channel resistance of negative control this moment switch MOS FET and the resistance of sampling resistor are very little, the forward voltage drop of built-in parasitic diode of just controlling switch MOS FET is also very little with respect to supply voltage, so the polarity of voltage sample circuit can not exported V+ signal, i.e. V+=0.I+ and V+ signal produce the CLK+ signal through logic sum gate, and CLK+ makes the high level on the FPDP D of just controlling D flip-flop latch and export to its output port Q and goes up and form the Drv+ signal, and the Drv+ signal becomes high level, make that just to control switch MOS FET open-minded.Because the D-S raceway groove of just controlling switch MOS FET is by open-minded, the resistance value between its D-S raceway groove becomes very little, flows through originally just to control electric current in the built-in parasitic diode of switch MOS FET and just be transferred to from the D-S raceway groove of just controlling switch and flow through.So far, just controlling switch and negative control switch has all finished and has opened operation, as long as the ON/OFF control signal remains logic high, Drv+ and the Drv-of just controlling D flip-flop and the output of negative control D flip-flop just can not change, just controlling switch and just keeping lasting open-minded with negative control switch, the AC load loop just keeps normal on-state.During the AC load loop was connected, the voltage drop between Vin and Vout was very little, did not have V+ and V-signal this moment.
Through after the some time, need the disconnecting consumers loop, just the ON/OFF control signal is changed into logic low.This logic low is input on the FPDP D of just controlling D flip-flop and negative control D flip-flop.According to the requirement of zero-current switching, obtain the conversion opportunity of alternating current solid-state power switch by the current polarity that detects load circuit.Promptly only when I+ or I-zero passage, just carry out signal and pass and replace.Among the embodiment 2, during load circuit is connected, do not have the signal of V+ and V-, at this moment, CLK+ and CLK-just only change with I+ or I-.Suppose after the ON/OFF control signal is changed into logic low, the alternating current zero passage, current polarity becomes positive polarity from negative polarity, promptly flows to the b point from a point.Current polarity sample circuit output this moment I+ signal, the I+ signal produces the CLK+ signal behind logic sum gate.The rising edge of CLK+ makes the low level on the FPDP D of just controlling D flip-flop latch and export to its output port Q and goes up formation Drv+ signal, and the Drv+ signal becomes low level, makes just to control switch MOS FET disconnection, and the D-S raceway groove of just controlling switch is closed.Because electric current this moment is a forward current, under the effect of load circuit voltage, this forward current just is transferred to the parasitic diode of just controlling in the switch by the buttoned-up D-S raceway groove of just controlling switch, makes the electric current in the load circuit continue to keep conducting.As time goes on this electric current can reduce gradually, is zero at last.When electric current when original variation tendency requires to produce the negative polarity electric current, be closed owing to just controlling the D-S raceway groove of switch, its inner parasitic diode has stopped the negative polarity electric current, therefore can not form negative current, load circuit is that zero back keeps zero current at electric current, promptly is closed.And this moment the AC load loop negative voltage can fall buttoned-up and just controlling on the switch, make Vout＞Vin, the negative voltage V-signal of polarity of voltage sample circuit output just makes CLK-signal effectively (this moment, I+ and I-were zero).Negative control D flip-flop is under the effect of CLK-signal, and the low level on its FPDP D is latched and exports to its output port Q and goes up formation Drv-signal, and the Drv-signal becomes low level, and negative control switch MOS FET is disconnected, and the negative D-S raceway groove of controlling switch is closed.So far, just control switch and negative control switch and all closing and finish, finishing the opening operation of load circuit.
Fig. 6 is the control waveform figure of embodiment 2 control inductive loads.Voltage difference Vin-Vout is the input of polarity of voltage sample circuit, and Vth+, Vth-are the detection threshold of polarity of voltage sample circuit; Ith+, Ith-are the detection threshold of current polarity sample circuit.After load circuit was connected, the electric current of load circuit lagged behind supply voltage.Because load circuit is to connect when voltage is zero, and changes by sine wave curve, so the inductive load electric current is started from scratch, after the rising of minimal tour electric current, change by sine wave curve, finish during current over-zero.During load circuit is connected, voltage difference Vin-Vou=0, V+=V-=0; When load circuit disconnected at zero current, current changing rate was zero, and the induced electromotive force in the inductive load also is zero, and voltage difference Vin-Vout can be set up to AC supply voltage fast.Can not the hold period variable condition in CLK+ and the CLK-frequency period after when the ON/OFF signal changes; Change in Drv+ and the Drv-frequency period after the ON/OFF signal changes, in the time period that load switches on and off, remain unchanged.
Claims (5)
1, a kind of control method of alternating current solid-state power switch, comprise signal input end, two solid-state switch MOSFET, load current polarity sample circuit, load voltage polarity sample circuit, two D flip-flops, current sampling resistor and insulating power supplies, it is characterized in that, comprise the steps:
1) two solid-state switch MOSFET is connected on the AC power inlet side, makes the source S of two solid-state switch MOSFET connect together by current sampling resistor;
2) drain D with a solid-state switch MOSFET is connected with AC power inlet side Vin, and this solid-state switch MOSFET is negative control switch, controls it by the negative drive signal Drv-of controlling D flip-flop output and is switched on or switched off; The drain D of another solid-state switch MOSFET is connected with AC load, and this solid-state switch MOSFET controls it by the drive signal Drv+ of just controlling D flip-flop output and is switched on or switched off for just controlling switch; When the drive signal Drv-of just controlling D flip-flop and the output of negative control D flip-flop and Drv+ are zero level, just controlling switch and negative control switch all is in off state, the reverse barrier properties of the parasitic diode of their inside makes load circuit be in off-state;
3) be connected on the source S of negative control switch the auxiliary excitation power supply that insulating power supply is exported, signal input end is connected respectively to just controls D flip-flop and negative control D flip-flop FPDP, the switch controlling signal of signal input end output, the control load loop switches on and off;
4) the polarity of voltage sample circuit detects the alternating voltage polarity on ac power supply circuit or the solid-state power switch loop, when this AC voltage difference is timing, and output signal V+; When this AC voltage difference when negative, output signal V-;
5) the current polarity sample circuit detects the polarity of load circuit electric current, obtains the polarity of load circuit electric current by gathering voltage difference on the sampling resistor, when this voltage difference is the timing load circuit sense of current for just, and output signal I+; When this voltage difference when negative the load circuit sense of current for negative, output signal I-;
6) when the polarity of the voltage of the electric current of load circuit or electric power loop changes, the V+ of output, I+ signal are through logic gates output CLK+, and CLK+ is output into drive signal Drv+ to the switch controlling signal of just controlling on the D flip-flop FPDP D to just controlling switch; The V-of output, I-signal are through logic gates output CLK-, and CLK-is output into drive signal Drv-to the switch controlling signal on the negative control D flip-flop FPDP D to negative control switch;
7) the Drv+ signal becomes high level, makes that just to control switch open-minded, and the Drv+ signal becomes low level, makes just to control switch and close, and the Drv-signal becomes high level, makes negative control switch open-minded, and the Drv-signal becomes low level, and negative control switch cuts out.
2, the control method of a kind of alternating current solid-state power switch as claimed in claim 1, it is characterized in that: the described switch of just controlling is an emos, and described just the control in switch and the negative control switch is respectively equipped with parasitic diode.
3, the control method of a kind of alternating current solid-state power switch as claimed in claim 1 is characterized in that: described negative control switch is an emos.
4, the control method of a kind of alternating current solid-state power switch as claimed in claim 1 is characterized in that: described logic gates can be a multiplier and an adder.
5, the control method of a kind of alternating current solid-state power switch as claimed in claim 1 is characterized in that: described logic gates can be an adder.
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| CN200810042119XA CN101662275B (en) | 2008-08-27 | 2008-08-27 | Control method for alternating current solid-state power switch |
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