CN101656213B - Trench gate metal oxide semiconductor field effect transistor and manufacturing method thereof - Google Patents
Trench gate metal oxide semiconductor field effect transistor and manufacturing method thereof Download PDFInfo
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Abstract
The invention relates to a trench gate metal oxide semiconductor field effect transistor and a manufacturing method thereof. The method comprises the following steps: manufacturing a first conductive epitaxial layer on a silicon substrate; manufacturing a plurality of trenches on the epitaxial layer; performing overall ion implantation of a first conductive doping material on the epitaxial layer; manufacturing a polysilicon pattern layer covering the trenches and the epitaxial layer in a preset range around the trenches; implanting a second conductive doping material on the epitaxial layer through the polysilicon pattern layer; importing a doping material to form a well area having the second conductive doping material; implanting the first conductive doping material in the well area through the polysilicon pattern layer to form a plurality of first doped areas; implanting the doping material of the first doped areas to form source electrode doped areas close to the trenches; and removing the polysilicon pattern layer above the epitaxial layer to form a polysilicon gate. The method can improve the depth distribution of the sell area of the trench gate metal oxide semiconductor field effect transistor and avoiding the effectiveness loss caused by the coverage of the gate trenches by the well area.
Description
Technical field
The present invention relates to structure of a kind of mos field effect transistor (MOS) and preparation method thereof; The depth distribution that particularly relates to a kind of well region through improving trench gate metal oxide semiconductor field effect transistor is avoided the bottom of well region cover gate groove and is caused the structure and preparation method thereof of the trench gate metal oxide semiconductor field effect transistor (Trench MOS) of transistor nonfunctional.
Background technology
For satisfying energy-conservation and the demand that reduces system power dissipation, need higher energy conversion efficiency, the design specification requirement that these grow with each passing hour can be increasingly serious challenge for the designer of power supply changeover device.In order to adapt to this demand, new-type (PCC) power institute's role in high-effect transducer is healed and is become important.Wherein, power metal oxide semiconductor field-effect transistor (Power MOSFET) has been widely used in various power supply changeover devices at present.
Power metal oxide semiconductor field-effect transistor main energy loss source in operation comprises the conducting loss that conducting resistance causes, and reaches the energy dissipation that interelectrode capacitance (comprising output capacitance Ciss and feedback capacity Crss etc.) is caused.It should be noted that each item loss beyond the conducting resistance all can be proportional with the interelectrode capacitance and the frequency of operation of power metal oxide semiconductor field-effect transistor.Therefore, if will improve the frequency of operation of power metal oxide semiconductor field-effect transistor, just must manage to reduce the interelectrode capacitance value.
Figure 1A to Fig. 1 H is the making flow process of a typical groove power mos field effect transistor (trench power MOSFET).Be to be example among the figure with N type power metal oxide semiconductor field-effect transistor.See also shown in Figure 1A, at first form a N type epitaxial loayer 120 on a N type silicon substrate 110.Then, utilize a photomask to define the position of gate trench, and in epitaxial loayer 120, produce a plurality of gate trenchs 130 with the mode of dry ecthing.
Subsequently, see also shown in Figure 1B, form a grid oxic horizon 140, then, deposit the exposed surface that a polysilicon layer covers epitaxial loayer 120 in the inwall of gate trench 130.This polysilicon layer is to fill up gate trench 130 fully.Next, eat-back (Etch Back) and remove the polycrystalline silicon material that is positioned at gate trench 130 tops, to constitute polysilicon gate 152.It should be noted that this etching process makes the upper limb of polysilicon gate 152 fall within the below of the upper limb of gate trench 130.
Next, see also shown in Fig. 1 C, the mode of (ion implantation) of injecting with ion is injected the surf zone 120a of P type alloy in N type epitaxial loayer 120.Then, see also shown in Fig. 1 D, heating imports (drive-in) P type alloy, uses and in N type epitaxial loayer 120, forms a P type well region (P-well) 122.It should be noted that; Because outside the sidewall of the opening part of gate trench 130 is exposed to; Shown in Fig. 1 C, through behind the ion implantation process, the concentration of the P type alloy that the epitaxial loayer 120 on gate trench 130 next doors is injected into and the degree of depth all can be greater than other parts of epitaxial loayer 120.Also therefore, shown in Fig. 1 D, import the middle 122a of the formed P type of P type alloy well region 122 and the dual-side 122b that is adjacent to gate trench 130, can have the bigger degree of depth.
Subsequently, see also shown in Fig. 1 E, utilize a photomask (not shown) to make the position of a photoresist pattern layer 162 definition source electrodes, form N type source doping region 160 with the ion injection mode on the surface of P type well region 122 then.These N type source doping region 160 are the sidewalls that are in close proximity to gate trench 130.
See also again shown in Fig. 1 F, deposit a dielectric layer 170 (for example boron-phosphorosilicate glass (BPSG) layer) and cover polysilicon gate 152, source doping region 160 comprehensively and be exposed to outer P type well region 122.Then, in dielectric layer 170, make a contact hole 172, expose the source doping region 160 and P type well region 122 that are positioned at dielectric layer 170 belows through micro image etching procedure.
Then, see also shown in Fig. 1 G,, inject P type alloy, form a P type heavily doped region 180 on the top of P type well region with the ion injection mode through this contact hole 172.At last, see also shown in Fig. 1 H, deposit the source doping region 160 that a metal level 190 covers dielectric layer 170 and is positioned at contact hole 172 bottoms, comprehensively to accomplish the making of this groove power mos field effect transistor.
Yet shown in Fig. 1 C and Fig. 1 D, the P type concentration of dopant in the epitaxial loayer 122 on gate trench 130 next doors is higher, and the degree of depth of injection is also darker, and then causes P type well region 122 to have the bigger degree of depth at the dual-side 122b that is adjacent to gate trench 130.This kind CONCENTRATION DISTRIBUTION state is unfavorable for the control on the processing procedure.Further, the bottom of gate trench 130 must join with the N type epitaxial loayer 120 of P type well region 122 belows, can make the transistor normal operation.In the processing procedure of traditional mos field effect transistor; P type alloy is bigger in the concentration at the dual-side 122b place that is adjacent to gate trench 130; Therefore; In the process that imports alloy formation P type well region 122, the bottom of gate trench 130 is caused transistor nonfunctional by 122 coverings of P type well region easily.
Therefore, how improving the depth distribution of the well region of mos field effect transistor, avoid the bottom of well region cover gate groove and cause transistor nonfunctional, is the target that this field practitioner desires most ardently pursuit.
This shows that above-mentioned existing trench gate metal oxide semiconductor field effect transistor and preparation method thereof obviously still has inconvenience and defective, and demands urgently further improving in product structure, manufacture method and use.In order to solve the problem of above-mentioned existence; Relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly; But do not see always that for a long time suitable design is developed completion; And common product and method do not have appropriate structure and method to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of new trench gate metal oxide semiconductor field effect transistor and preparation method thereof, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Because the defective that above-mentioned existing trench gate metal oxide semiconductor field effect transistor and preparation method thereof exists; The inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge; And the utilization of cooperation scientific principle; Actively study innovation; In the hope of founding a kind of new trench gate metal oxide semiconductor field effect transistor and preparation method thereof, can improve general existing trench gate metal oxide semiconductor field effect transistor and preparation method thereof, make it have more practicality.Through constantly research, design, and after studying sample and improvement repeatedly, found out the present invention of true tool practical value finally.
Summary of the invention
Main purpose of the present invention is; Overcome the defective that existing trench gate metal oxide semiconductor field effect transistor exists; And a kind of new trench gate metal oxide semiconductor field effect transistor is provided; Technical problem to be solved is the depth distribution through the well region that improves trench gate metal oxide semiconductor field effect transistor, avoids the bottom of well region cover gate groove and causes transistor nonfunctional, is very suitable for practicality.
Another object of the present invention is to; Overcome the defective of the manufacture method existence of existing trench gate metal oxide semiconductor field effect transistor; And a kind of manufacture method of new trench gate metal oxide semiconductor field effect transistor is provided; Technical problem to be solved is to make its degree of depth that can effectively control the well region of trench gate metal oxide semiconductor field effect transistor, thereby is suitable for practicality more.
The object of the invention and solve its technical problem and adopt following technical scheme to realize.The manufacture method of a kind of trench gate metal oxide semiconductor field effect transistor that proposes according to the present invention, may further comprise the steps: the epitaxial loayer of making one first conductivity type is on a silicon substrate; Make a plurality of first grooves in epitaxial loayer; Ion injects (Blanket Implant) first conductivity type dopant in this epitaxial loayer comprehensively; Through a polysilicon layer photomask, make a poly-silicon pattern layer with the lithography mode and cover this first groove and its this epitaxial loayer of preset range on every side; Through this poly-silicon pattern layer, inject second conductivity type dopant in this epitaxial loayer with the ion injection mode; Import those alloys in (Drive-in) this epitaxial loayer, with form one have this second conductivity type well region (Well); Through this poly-silicon pattern layer, inject this first conductivity type dopant in this well region, to form a plurality of first doped regions with the ion injection mode; The etching removal is positioned at this poly-silicon pattern layer of this epitaxial loayer top to form polysilicon gate; And remove in the step of this poly-silicon pattern layer in etching; Remove this first doped region of part of the opening below that is positioned at this poly-silicon pattern layer simultaneously; Make the not removed part of this first doped region be divided into two parts, correspond respectively to the said polysilicon gate of these opening both sides; Import the alloy in this first doped region, be in close proximity to this first groove to form the one source pole doped region; Deposit a dielectric layer comprehensively, and in dielectric layer, make a contact hole, this source doping region of exposed portion; And deposit a metal level on this dielectric layer, and insert this this source doping region of contact hole covering.
The object of the invention and solve its technical problem and also can adopt following technical measures further to realize.
The manufacture method of aforesaid trench gate metal oxide semiconductor field effect transistor; Wherein in this dielectric layer, make after this contact hole; More comprise through this contact hole and inject this second conductivity type alloy in this well region, to constitute one second doped region with the ion injection mode.
The object of the invention and solve its technical problem and also adopt following technical scheme to realize.According to a kind of trench gate metal oxide semiconductor field effect transistor of making according to preceding method that the present invention proposes, it includes: the epitaxial loayer of one first conductivity type; A plurality of first grooves are positioned at this epitaxial loayer; One polysilicon gate is positioned at this first groove; The well region of one second conductivity type; Be positioned between adjacent two these first grooves; The lower edge of this well region has a protrusion downwards corresponding to the middle between adjacent two these first grooves, and this well region has the minimum degree of depth in the side-walls that is adjacent to this first groove; And this protrudes downwards is the cambered surface that an opening makes progress; The source doping region of a plurality of first conductivity types is adjacent to those first grooves respectively, and its lower edge presents the curved surface that constitutes because of alloy importing (Drive-in); Second doped region of one second conductivity type is between two these source doping region; One dielectric layer covers this polysilicon gate, and this dielectric layer also has at least one contact hole and exposes this source doping region to the open air; And a metal level, cover this dielectric layer and this source doping region.
The object of the invention and solve its technical problem and also can adopt following technical measures further to realize.
Aforesaid trench gate metal oxide semiconductor field effect transistor, the bosom of wherein said source doping region is positioned at the below of this contact hole.
Aforesaid trench gate metal oxide semiconductor field effect transistor; Wherein said well region upper surface has a depression; Between two these source doping region, the adjacent sidewalls of this depression is in this source doping region, and the bottom surface of this depression is adjacent to second doped region of this second conductivity type; And the sidewall of this contact hole is the outside that is positioned at this depression.
The object of the invention and solve its technical problem and also adopt following technical scheme to realize.The manufacture method of a kind of trench gate metal oxide semiconductor field effect transistor that proposes according to the present invention, it may further comprise the steps: the epitaxial loayer of making one first conductivity type is on a silicon substrate; Make a plurality of first grooves, a plurality of second groove in this epitaxial loayer, this second groove is to be positioned between those adjacent first grooves; Ion injects first conductivity type dopant in this epitaxial loayer comprehensively; Through a polysilicon layer photomask, make a poly-silicon pattern layer with the lithography mode and cover this first groove and its this epitaxial loayer of preset range on every side; Through this poly-silicon pattern layer, inject second conductivity type dopant in this epitaxial loayer with the ion injection mode; Import those alloys in this epitaxial loayer, with form one have this second conductivity type well region; Through the one source pole photomask, make a photoresist pattern layer with the lithography mode and cover this second groove and this well region on every side, make to have opening between this poly-silicon pattern layer and this photoresist pattern layer with this well region of exposed portion; Through this poly-silicon pattern layer and this photoresist pattern layer, inject this first conductivity type dopant in this well region, to form a plurality of first doped regions with the ion injection mode; Remove this photoresist pattern layer with remove be positioned at this epitaxial loayer top this poly-silicon pattern layer to form polysilicon gate; Import the alloy in this first doped region, be in close proximity to this first groove to form the one source pole doped region; Deposit a dielectric layer comprehensively, and in this dielectric layer, make a contact hole, this source doping region of exposed portion; Through this contact hole, inject this second conductivity type dopant in this well region, to form one second doped region at this second channel bottom with the ion injection mode; And deposit a metal level on this dielectric layer, and insert this this source doping region of contact hole covering.
The object of the invention and solve its technical problem and also adopt following technical scheme to realize.According to a kind of trench gate metal oxide semiconductor field effect transistor of making according to preceding method that the present invention proposes, it comprises: the epitaxial loayer of one first conductivity type; A plurality of first grooves are positioned at this epitaxial loayer; One polysilicon gate is positioned at this first groove; The well region of one second conductivity type; Be positioned between adjacent two these first grooves; The lower edge of this well region has a protrusion downwards corresponding to the middle between adjacent two these first grooves, and this well region has the minimum degree of depth in the side-walls that is adjacent to this first groove; And this protrudes downwards is the cambered surface that an opening makes progress; The source doping region of a plurality of first conductivity types is adjacent to those first grooves respectively, and its lower edge presents the curved surface that constitutes because of the alloy importing; One second groove is arranged in the well region of this second conductivity type, and is positioned between adjacent two these first grooves and to be positioned at adjacent two these source dopant interval; Second doped region of one second conductivity type is positioned at this second channel bottom; One dielectric layer covers this polysilicon gate, and this dielectric layer also has at least one contact hole and exposes this source doping region to the open air; And a metal level, cover this dielectric layer and this source doping region.
The object of the invention and solve its technical problem and also can adopt following technical measures further to realize.
Aforesaid trench gate metal oxide semiconductor field effect transistor, wherein said well region have minimum thickness below this second groove.
The present invention compared with prior art has tangible advantage and beneficial effect.Can know that by above technical scheme major technique of the present invention thes contents are as follows:
In order to achieve the above object, the invention provides a kind of manufacture method of trench gate metal oxide semiconductor field effect transistor, comprise the following step: the epitaxial loayer of (a) making one first conductivity type is on a silicon substrate; (b) make a plurality of first grooves in epitaxial loayer; (c) ion injects (Blanket Implant) first conductivity type dopant in epitaxial loayer comprehensively; (d), make a poly-silicon pattern layer with the lithography mode and cover first groove and its epitaxial loayer of a preset range on every side through a polysilicon layer photomask; (e) through the poly-silicon pattern layer, inject second conductivity type dopant in epitaxial loayer with the ion injection mode; (f) import alloy in (Drive-in) epitaxial loayer, with form one have second conductivity type well region (Well); (g) through the poly-silicon pattern layer, inject first conductivity type dopant in well region with the ion injection mode, to form a plurality of first doped regions; (h) remove the poly-silicon pattern layer that is positioned at the epitaxial loayer top, to form polysilicon gate; (i) import the interior alloy of first doped region, form the one source pole doped region and be in close proximity to first groove; (j) deposit a dielectric layer comprehensively, and in dielectric layer, make a contact hole, the source doping region of exposed portion; (k) deposit a metal level on dielectric layer, and cover source doping region.
In addition, in order to achieve the above object, the present invention provides a kind of structure of trench gate metal oxide semiconductor field effect transistor in addition.This trench gate metal oxide semiconductor field effect transistor structure comprises source doping region, a dielectric layer and a metal level of the epitaxial loayer of one first conductivity type, a plurality of first groove, a plurality of polysilicon gate, a plurality of second conductivity type well region, a plurality of first conductivity types.Wherein, a plurality of first grooves are to be positioned at epitaxial loayer.A plurality of polysilicon gates are to lay respectively in these first grooves.A plurality of second conductivity type well regions lay respectively between adjacent two first grooves.The lower edge of the second conductivity type well region has one in the middle corresponding to adjacent two first grooves and protrudes downwards, and this second conductivity type well region has the minimum degree of depth in the side-walls that is adjacent to first groove.The source doping region of a plurality of first conductivity types, the sidewall joint of its lower edge and first groove presents the curved surface that constitutes because of alloy importing (Drive-in).Dielectric layer is to cover polysilicon gate.This dielectric layer also has at least one contact hole and exposes source doping region to the open air.Metal level is to cover dielectric layer and source doping region.
By technique scheme; Trench gate metal oxide semiconductor field effect transistor of the present invention and preparation method thereof has advantage and beneficial effect at least: the present invention can effectively improve the existing various shortcoming that trench gate metal oxide semiconductor field effect transistor and preparation method thereof exists of commonly using; Can improve the depth distribution of the well region of trench gate metal oxide semiconductor field effect transistor; Avoid the bottom of well region cover gate groove and cause transistor nonfunctional, so make the present invention possess skills more progressive, more practical, more meet the required effect of user.
In sum, the manufacture method of a kind of trench gate metal oxide semiconductor field effect transistor of the present invention.Behind the manufacturing grid groove, ion injects first conductivity type dopant in epitaxial loayer comprehensively.Then, make the epitaxial loayer of a preset range around a poly-silicon pattern layer cover gate groove and its, and, inject second conductivity type dopant, have the well region of second conductivity type with formation in epitaxial loayer through this poly-silicon pattern layer.Next, inject first conductivity type dopant to form a plurality of first doped regions through the poly-silicon pattern layer.Then, the poly-silicon pattern layer that is positioned at the epitaxial loayer top is removed in etching, removes first doped region of part simultaneously.Next, import the alloy of first doped region, be next to gate trench to form the one source pole doped region.The present invention has above-mentioned advantage and practical value; No matter it all has bigger improvement on product structure, manufacture method or function; Obvious improvement is arranged technically, and produced handy and practical effect, and more existing trench gate metal oxide semiconductor field effect transistor and preparation method thereof has the outstanding effect of enhancement; Thereby being suitable for practicality more, really is the new design of a novelty, progress, practicality.
Above-mentioned explanation only is the general introduction of technical scheme of the present invention; Understand technological means of the present invention in order can more to know; And can implement according to the content of specification, and for let of the present invention above-mentioned with other purposes, feature and advantage can be more obviously understandable, below special act preferred embodiment; And conjunction with figs., specify as follows.
Description of drawings
Figure 1A to Fig. 1 H is the sketch map of the processing flow of a typical trench gate metal oxide semiconductor field effect transistor.
Fig. 2 A to Fig. 2 H is the sketch map of a preferred embodiment of the making flow process of trench gate metal oxide semiconductor field effect transistor of the present invention.
Fig. 3 A to Fig. 3 H is the sketch map of another preferred embodiment of the making flow process of trench gate metal oxide semiconductor field effect transistor of the present invention.
Fig. 4 A and Fig. 4 B are the sketch mapes of another preferred embodiment of the making flow process of trench gate metal oxide semiconductor field effect transistor of the present invention.
110:N type silicon substrate 120:N type epitaxial loayer
120a: the surf zone 122:P type well region of epitaxial loayer
The side of the middle 122b:P type well region of 122a:P type well region
130: gate trench 140: grid oxic horizon
152: polysilicon gate 160: source doping region
162: photoresist pattern layer 170: dielectric layer
172; Contact hole 180:P type heavily doped region
190: metal level 210:N type silicon substrate
220:N type epitaxial loayer 220a: the surf zone of epitaxial loayer
220b: gate trench bottom 222:P type well region
The side of the centre 222b:P type well region of 222a:P type well region
230: gate trench 240: grid oxic horizon
250: poly-silicon pattern layer 250a: the opening of poly-silicon pattern layer
252: 260: the first doped regions of polysilicon gate
260a: doped region 260b: doped region
262: depression 260 ': source doping region
270: dielectric layer 272: contact hole
310:N type silicon substrate 320:N type epitaxial loayer
320a: the surf zone 320b of epitaxial loayer: the bottom of gate trench
320c: the bottom 322:P type well region of second groove
The side of the centre 322b:P type well region of 322a:P type well region
330: 332: the second grooves of gate trench
340: grid oxic horizon 350: the poly-silicon pattern layer
350a: the opening 352 of poly-silicon pattern layer: polysilicon gate
360: the first doped region 360a: doped region
360b: doped region 361: photoresist pattern layer
362: depression 360 ': source doping region
370: dielectric layer 372: contact hole
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention; Below in conjunction with accompanying drawing and preferred embodiment; To the trench gate metal oxide semiconductor field effect transistor that proposes according to the present invention and preparation method thereof its embodiment, structure, manufacture method, step, characteristic and effect thereof, specify as after.
Relevant aforementioned and other technology contents, characteristics and effect of the present invention can be known to appear in the detailed description of graphic preferred embodiment is consulted in following cooperation.Through the explanation of embodiment, when can being to reach technological means that predetermined purpose takes and effect to get one more deeply and concrete understanding to the present invention, yet the appended graphic usefulness that only provides reference and explanation be not to be used for the present invention is limited.
Fig. 2 A to Fig. 2 H is the sketch map of a preferred embodiment of the making flow process of mos field effect transistor of the present invention.Be to be that example describes among the figure with N type metal oxide semiconductor field-effect transistor.See also shown in Fig. 2 A, at first, make a N type epitaxial loayer 220 on a N type silicon substrate 210.Then, utilize a photomask (not shown) to define the position of grid, and in epitaxial loayer 220, produce a plurality of gate trenchs 230 with the mode of dry ecthing.Next, with the mode of comprehensive ion injection (B1anket Implant), the alloy that injects the N type is in the surf zone 220a of epitaxial loayer 220 and the bottom 220b of gate trench 230.
Subsequently; See also shown in Fig. 2 B, form a grid oxic horizon 240 in the inwall of gate trench 230, then; Through a polysilicon layer photomask (not shown), make a poly-silicon pattern layer 250 cover gate groove 230 and the epitaxial loayer 220 in the preset range around it with the lithography mode.See also shown in Fig. 2 C, through this poly-silicon pattern layer 250, the alloy that injects the P type with the ion injection mode is in epitaxial loayer 220 again.Then, heating imports alloy in (Drive-in) epitaxial loayer 220 (comprise N type alloy that comprehensive ion injects with and the P type alloy that injects through poly-silicon pattern layer 250), forms the well region (Well) 222 of a P type.
Here it should be noted that to see also shown in Fig. 2 B that the poly-silicon pattern layer 250 of present embodiment has not only covered gate trench 230, also cover its interior epitaxial loayer 220 of preset range on every side simultaneously.Therefore, the P type alloy that injects epitaxial loayer 220 is restricted to the below of the opening 250a of poly-silicon pattern layer 250, and the epitaxial loayer 220 on gate trench 230 next doors can't have the P type alloy of high concentration.In follow-up importing processing procedure, these P type alloys just can be gradually by the opening 250a below of poly-silicon pattern layer 250, the direction towards the inside of epitaxial loayer 220 with the sidewall of gate trench 230 spreads.Therefore, see also shown in Fig. 2 C, through the formed P type of heating introducing technology well region 222, its centre 222a can present the trend that reduces gradually towards the depth distribution of its dual-side 222b.With regard to a preferred embodiment, P type well region 222 has the minimum degree of depth being adjacent to gate trench 230 places.
Secondly; Though in the processing procedure of Fig. 2 A, be injected with N type alloy, but the concentration of these N type alloys is far below the P type alloy that in the processing procedure of Fig. 2 C, is injected at the surf zone 220a of epitaxial loayer 220; Therefore, the existence of these N type alloys can't influence the formation of P type well region 222.Help to improve the depth distribution of P type well region 222 on the contrary.Further; Before making P type well region 222, the N type alloy that the mode of injecting with comprehensive ion is injected, and cause among the surf zone 220a of epitaxial loayer 220; N type concentration of dopant in the zone on gate trench 230 next doors is higher, and other regional concentration is then roughly even.Wherein, be distributed in the importing degree of depth of the P type alloy that the N type alloy on gate trench 230 next doors can suppressor grid groove 230 next doors.
Next, see also shown in Fig. 2 D,, inject N type alloy in P type well region 222, to form a plurality of first doped regions 260 with the ion injection mode through poly-silicon pattern layer 250.Then, see also shown in Fig. 2 E, remove the poly-silicon pattern layer 250 that is positioned at epitaxial loayer 220 tops, to constitute polysilicon gate 252.It should be noted that this etching step is for poly-silicon pattern layer 250 and first doped region 260 outside being exposed to carries out comprehensive etching.Therefore, when poly-silicon pattern layer 250 is removed in etching, also can form one and cave in 262 at upper surface corresponding to the well region 222 at the opening 250a place of poly-silicon pattern layer 250.Suitably the degree of depth of control first doped region 260 and poly-silicon pattern layer 250 height can be divided into two parts 260a, 260b with first doped region 260 through the formed depression 262 of this etch process.The doped region 260a of this two part, 260b is the polysilicon gate 252 of corresponding both sides respectively.
Subsequently, see also shown in Fig. 2 F, heating imports the first doped region 260a again, and the alloy in the 260b makes the first doped region 260a, and the distribution of 260b is towards the direction expansion of polysilicon gate 252, to form a plurality of source doping region 260 '.The both sides of this source doping region 260 ' are adjacent to the sidewall and the gate trench 230 of depression 262 respectively.Subsequently, see also shown in Fig. 2 G, deposit a dielectric layer 270 comprehensively, and in dielectric layer 270, make a contact hole 272 exposed portion source doping region 260 '.Then,, inject P type alloy in P type well region 222, constitute one second doped region 280 with the ion injection mode again through this contact hole 272.This second doped region 280 is adjacent to the bottom surface of P type well region 222 depressions in the surface 262.At last, see also shown in Fig. 2 H, deposit a metal level 290 on dielectric layer 270, and insert contact hole 272 covering source doping region 260 ', and accomplish the making flow process of this trench gate metal oxide semiconductor field effect transistor.
Fig. 3 A to Fig. 3 H is the sketch map of another preferred embodiment of the making flow process of mos field effect transistor of the present invention.Be to be that example describes among the figure with N type metal oxide semiconductor field-effect transistor.See also shown in Fig. 3 A, at first, make a N type epitaxial loayer 320 on a N type silicon substrate 310.Then, utilize a photomask (not shown) to define the position of grid, this photomask defines the position of second groove simultaneously between adjacent two grids.Then, in epitaxial loayer 220, produce a plurality of gate trenchs 330 with the mode of dry ecthing, and second groove 332 that is positioned at 330 of adjacent two gate trenchs.Next, with the mode that comprehensive ion injects, the alloy that injects the N type is in the surf zone 320a of epitaxial loayer 320, and the bottom 320b and the 320c of the gate trench 330 and second groove 332.
Subsequently; See also shown in Fig. 3 B, form a grid oxic horizon 340 in the inwall of gate trench 330, then; Through a polysilicon layer photomask (not shown), make a poly-silicon pattern layer 350 cover gate groove 330 and the epitaxial loayer 320 in the preset range around it with the lithography mode.It should be noted that this poly-silicon pattern layer 350 does not cover second groove 332, and most epitaxial loayer 320 still keeps exposed.
Next, see also shown in Fig. 3 C, through this poly-silicon pattern layer 350, the alloy that injects the P type with the ion injection mode is in epitaxial loayer 320.The zone of injecting comprises the bottom 320c of second groove 332.Then, heating imports the alloy (comprising the alloy of N type and the alloy of P type) in (Drive-in) epitaxial loayer 320, forms the well region (Well) 322 of a P type.
Please consult shown in Fig. 3 B, the poly-silicon pattern layer 350 of present embodiment has not only covered gate trench 330 again, also covers its interior epitaxial loayer 320 of preset range on every side simultaneously.Therefore, the P type alloy of injection epitaxial loayer 320 is restricted to the below of the opening 350a of poly-silicon pattern layer 350.Epitaxial loayer 320 on gate trench 330 next doors does not have the P type alloy of high concentration.In follow-up importing processing procedure, these P type alloys just can be gradually by the opening 350a below of poly-silicon pattern layer 350, the direction towards the inside of epitaxial loayer 320 with the sidewall of gate trench 330 spreads.Also therefore, see also shown in Fig. 3 C, through the formed P type of heating introducing technology well region 322, its centre 322a can present the trend that reduces gradually towards the depth distribution of its dual-side 322b.Therefore, with regard to another preferred embodiment, P type well region 322 has the minimum degree of depth being adjacent to gate trench 330 places.
Secondly, see also shown in Fig. 3 A, present embodiment is before making P type well region 322, and the mode of having injected through comprehensive ion is earlier injected N type alloy in the surf zone 320a of epitaxial loayer 320 and the bottom 320c of second groove 332.The surf zone 320a of these N type alloy epitaxial loayers 320 is higher in the N type concentration of dopant in the zone on gate trench 330 next doors, and other regional concentration then is roughly evenly to distribute.Wherein, be distributed in the importing degree of depth of the P type alloy that the N type alloy on gate trench 330 next doors can suppressor grid groove 330 next doors.
In addition, present embodiment is at 330 extra making second grooves 332 of adjacent two gate trenchs.Seeing also the selectivity ion implantation process shown in Fig. 3 C can inject P type alloy in epitaxial loayer 320 through second groove, 332 bottoms, to form P type well region 322.Therefore, the centre 322a of P type well region 322 promptly corresponding to second groove, 332 places, can produce one and protrude downwards.Secondly, see also shown in Fig. 3 A, present embodiment is before making P type well region 322, and the mode of injecting through comprehensive ion is earlier injected the bottom 320c of N type alloy in second groove 332.These N type alloys that are positioned at the bottom 320c of second groove 332 can suppress the importing degree of depth of P type alloy, make P type well region 322 below corresponding to second groove 332, have minimum thickness (i.e. the distance of the lower edge of the bottom surface of second groove 332 and P type well region 322).
Next, see also shown in Fig. 3 D,, make a photoresist pattern layer 361 with the lithography mode and cover second groove 332 and P type well region 322 on every side through one source pole photomask (not shown).Has opening to expose P type well region 322 to the open air at poly- silicon pattern layer 350 and 361 of photoresist pattern layers.Then, through poly-silicon pattern layer 350 and photoresist pattern layer 361, inject N type alloy in P type well region 322, in order to form a plurality of first doped regions 360 with the ion injection mode.See also again shown in Fig. 3 E, remove photoresist pattern layer 361 and the poly-silicon pattern layer 350 that is positioned at epitaxial loayer 320 tops in regular turn, to form polysilicon gate 352 in gate trench 330.
Here it should be noted that aforementioned etching step is for poly-silicon pattern layer 350 and first doped region 360 outside being exposed to carries out etching comprehensively.Therefore, when poly-silicon pattern layer 350 is removed in etching, also can in the epitaxial loayer 320 below the opening 350a of poly-silicon pattern layer 350, form a depression 362, and remove first doped region 360 partly.But; See also shown in Fig. 3 D; First doped region 360 that forms with the ion injection mode can be by horizontal expansion certain limit under the opening 350a of poly-silicon pattern layer 350, therefore, and after poly-silicon pattern layer 350 is removed in etching; Can leave the first doped region 360a of part in depression 362 both sides of epitaxial loayer 320,360b.
Next, see also shown in Fig. 3 F, heating imports the first doped region 360a, and the N type alloy in the 360b makes the direction expansion of the scope of first doped region 360 towards polysilicon gate 352, to form source doping region 360 '.The both sides of this source doping region 360 ' are adjacent to the sidewall and the gate trench 330 of depression 362 respectively.See also shown in Fig. 3 D, doped region 360a, the position of 360b is the influence that receives poly-silicon pattern layer 350.See also Fig. 3 B institute diagrammatic sketch simultaneously, the poly-silicon pattern layer 350 of present embodiment is cover gate groove 330 and the interior epitaxial loayer 320 of a preset range around it.Therefore, the setting of aforementioned preset range must be considered doped region 360a simultaneously in light of actual conditions, the importing degree of depth of the first conductivity type alloy in the 360b and deciding.In order to form source doping region 360 ', this preset range must be less than doped region 360a, the importing degree of depth of 360b conductivity type alloy.
Subsequently, see also shown in Fig. 3 G, deposit a dielectric layer 370 comprehensively, and in dielectric layer 370, make a contact hole 372.This contact hole 372 is the source doping region 360 ' of exposed portion at least.Then, through this contact hole 372, inject P type alloy in P type well region 322, to constitute second doped region 380 with the ion injection mode.At last, see also shown in Fig. 3 H, deposit a metal level 390 on dielectric layer 370, and cover source doping region 360 ', and accomplish the making flow process of this trench gate metal oxide semiconductor field effect transistor through contact hole 372.
In the embodiment of Fig. 3 A to Fig. 3 H, gate trench 330 is through making with micro image etching procedure with second groove 332.But, the invention is not restricted to this.The gate trench 330 and second groove 332 also can use two road micro image etching procedures to make respectively, and the etch depth of second groove 332 need be not identical with the etch depth of gate trench 330 yet.
In the embodiment of Fig. 3 A to Fig. 3 H; Second groove 332 is the middle that roughly are positioned at adjacent two gate trenchs 330; Have the second unique groove 332 330 of adjacent two gate trenchs, and the opening size of second groove 332 is substantially equal to the opening size of gate trench 330.But, the invention is not restricted to this.If 330 of adjacent two gate trenchs have enough spaces; Also can be at 330 second grooves 332 of making greater number of adjacent two gate trenchs; Or strengthening the opening size of second groove 332, the profile with the lower edge that changes P type well region 322 cooperates the demand in the power transistor design.
Secondly, see also shown in Fig. 2 H and Fig. 3 H, in the aforementioned embodiment, the centre 222a of the P type well region 222,322 of mos field effect transistor, the degree of depth of 322a is greater than the degree of depth of gate trench 230,330.But the present invention is not limited to this.The centre 222a of P type well region 222,322, the degree of depth of 322a can also be less than the degree of depth of gate trench 230,330.
See also shown in Fig. 2 G and Fig. 3 G again, can be connected to metal level 290,390 smoothly in order to ensure source doping region 260 ', 360 ', with regard to an embodiment, contact hole 272,372 opening sizes are the size that equals the depression 262,362 of epitaxial loayer at least.See also again shown in Fig. 4 A and the 4B; In order to increase the contact area of source doping region 260 ' and metal level 290; Can further enlarge the size of the contact hole 272 ' in the dielectric layer 270 ', make the sidewall of contact hole 272 ' be positioned at the outside of depression 262, and keep certain distances with depression 262.
In addition, see also shown in Fig. 2 E, Fig. 2 F, Fig. 3 E and Fig. 3 F, manufacture method of the present invention is to doped region 260a, 260b, and 360a, 360b impose the importing processing procedure, to form source doping region 260 ', 360 ' in the side of polysilicon gate 252,352.Lower edge in source doping region 260 ', 360 ' can present the curved surface that constitutes because of the alloy importing.See also simultaneously shown in Fig. 2 D and Fig. 3 D, first doped region 260,360th is formed at well region 222,322 through poly-silicon pattern layer 250,350.Simultaneously, carry out comprehensive etching for poly-silicon pattern layer 250,350 after, still have part first doped region to be positioned at the below of depression 262,362.Therefore, can be through the bosom that imports the formed source doping region 260 ', 360 ' of processing procedure corresponding to the opening 250a of poly-silicon pattern layer 250,350, the below of 350a.In addition, as previously mentioned, with regard to a preferred embodiment, the sidewall of contact hole 272,372 is the outsides that are positioned at depression 262,362.Depression 262,362nd is carried out comprehensive etching and is formed in the epitaxial loayer 220,320 for poly-silicon pattern layer 250,350.Therefore, with regard to a preferred embodiment, the bosom of source doping region 260 ', 360 ' can be seated the below of contact hole 272,372.
It should be noted that the outward appearance of source doping region 260 ', 360 ' can receive the outward appearance of the width difference of poly-silicon pattern layer 250,350, depression 262,362 and the influence that ions inject and import processing procedure.Further, if the reduced width of poly-silicon pattern layer 250,350, the bosom of source doping region 260 ', 360 ' will be moved towards polysilicon gate 252,352; If first doped region 260,360 that is positioned at depression 262,362 belows is by etching removal fully, remaining N type alloy can be moved towards the direction of polysilicon gate 252,352 by the sidewall of depression 262,362.In the case, the bosom of formed source doping region 260 ', 360 ' can be moved towards the direction of polysilicon gate 252,352.Therefore, the bosom of formed source doping region 260 ', 360 ' may not necessarily be seated the below of contact hole 272,372.
See also shown in Fig. 1 H, the P type well region 122 of traditional trench gate metal oxide semiconductor field effect transistor has the bigger degree of depth at the dual-side 122b that is adjacent to gate trench 130.If fail suitably to control the importing degree of depth of P type alloy, transistorized passage takes place easily by the result of P type well region 122 blocking-up.Under comparing, see also shown in Fig. 2 H and Fig. 3 H, the depth distribution of the P type well region 222,322 of trench gate metal oxide semiconductor field effect transistor of the present invention is by centre 222a, and 322a is towards side 222b, and 322b successively decreases.The distribution aspect of this kind P type well region 222,232 helps to prevent that transistor channels is by 222,322 blocking-up of P type well region; And then help in transistorized design shortening gate trench 230; 330 the degree of depth reduces conducting resistance and interelectrode capacitance, to improve transistorized frequency of operation.
Secondly, see also shown in Fig. 3 H, mos field effect transistor of the present invention (corresponding to dual-side 322b of P type well region 322) between adjacent two NPN transistors has a PN diode structure (corresponding to the centre 322a of P type well region 322).And P type well region 322 has minimum width corresponding to the PN diode structure.Therefore collapse electric current (avalanche current) second groove 332 that tends to flow through, can prevent the mos field effect transistor collapse.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction; Though the present invention discloses as above with preferred embodiment; Yet be not in order to limiting the present invention, anyly be familiar with the professional and technical personnel, in not breaking away from technical scheme scope of the present invention; When the method for above-mentioned announcement capable of using and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations; In every case be the content that does not break away from technical scheme of the present invention, to any simple modification, equivalent variations and modification that above embodiment did, all still belong in the scope of technical scheme of the present invention according to technical spirit of the present invention.
Claims (8)
1. the manufacture method of a trench gate metal oxide semiconductor field effect transistor is characterized in that it may further comprise the steps:
The epitaxial loayer of making one first conductivity type is on a silicon substrate;
Make a plurality of first grooves in this epitaxial loayer;
Ion injects first conductivity type dopant in this epitaxial loayer comprehensively;
Through a polysilicon layer photomask, make a poly-silicon pattern layer with the lithography mode and cover this first groove and its this epitaxial loayer of preset range on every side;
Through this poly-silicon pattern layer, inject second conductivity type dopant in this epitaxial loayer with the ion injection mode;
Import those alloys in this epitaxial loayer, with form one have this second conductivity type well region;
Through this poly-silicon pattern layer, inject this first conductivity type dopant in this well region, to form a plurality of first doped regions with the ion injection mode;
The etching removal is positioned at this poly-silicon pattern layer of this epitaxial loayer top to form polysilicon gate; And remove in the step of this poly-silicon pattern layer in etching; Remove this first doped region of part of the opening below that is positioned at this poly-silicon pattern layer simultaneously; Make the not removed part of this first doped region be divided into two parts, correspond respectively to the said polysilicon gate of these opening both sides;
Import the alloy in this first doped region, be in close proximity to this first groove to form the one source pole doped region;
Deposit a dielectric layer comprehensively, and in this dielectric layer, make a contact hole, this source doping region of exposed portion; And
Deposit a metal level on this dielectric layer, and insert this this source doping region of contact hole covering.
2. the manufacture method of trench gate metal oxide semiconductor field effect transistor according to claim 1; It is characterized in that wherein; In this dielectric layer, make after this contact hole; More comprise through this contact hole and inject this second conductivity type alloy in this well region, to constitute one second doped region with the ion injection mode.
3. trench gate metal oxide semiconductor field effect transistor of making according to the method for claim 2 is characterized in that it comprises:
The epitaxial loayer of one first conductivity type;
A plurality of first grooves are positioned at this epitaxial loayer;
One polysilicon gate is positioned at this first groove;
The well region of one second conductivity type; Be positioned between adjacent two these first grooves; The lower edge of this well region has a protrusion downwards corresponding to the middle between adjacent two these first grooves, and this well region has the minimum degree of depth in the side-walls that is adjacent to this first groove; And this protrudes downwards is the cambered surface that an opening makes progress;
The source doping region of a plurality of first conductivity types is adjacent to those first grooves respectively, and its lower edge presents the curved surface that constitutes because of the alloy importing;
Second doped region of one second conductivity type is between two these source doping region;
One dielectric layer covers this polysilicon gate, and this dielectric layer also has at least one contact hole and exposes this source doping region to the open air; And
One metal level covers this dielectric layer and this source doping region.
4. trench gate metal oxide semiconductor field effect transistor according to claim 3 is characterized in that the bosom of wherein said source doping region is positioned at the below of this contact hole.
5. trench gate metal oxide semiconductor field effect transistor according to claim 3; It is characterized in that wherein said well region upper surface has a depression; Between two these source doping region, the adjacent sidewalls of this depression is in this source doping region, and the bottom surface of this depression is adjacent to second doped region of this second conductivity type; And the sidewall of this contact hole is the outside that is positioned at this depression.
6. the manufacture method of a trench gate metal oxide semiconductor field effect transistor is characterized in that it may further comprise the steps:
The epitaxial loayer of making one first conductivity type is on a silicon substrate;
Make a plurality of first grooves, a plurality of second groove in this epitaxial loayer, this second groove is to be positioned between those adjacent first grooves;
Ion injects first conductivity type dopant in this epitaxial loayer comprehensively;
Through a polysilicon layer photomask, make a poly-silicon pattern layer with the lithography mode and cover this first groove and its this epitaxial loayer of preset range on every side;
Through this poly-silicon pattern layer, inject second conductivity type dopant in this epitaxial loayer with the ion injection mode;
Import those alloys in this epitaxial loayer, with form one have this second conductivity type well region;
Through the one source pole photomask, make a photoresist pattern layer with the lithography mode and cover this second groove and this well region on every side, make to have opening between this poly-silicon pattern layer and this photoresist pattern layer with this well region of exposed portion;
Through this poly-silicon pattern layer and this photoresist pattern layer, inject this first conductivity type dopant in this well region, to form a plurality of first doped regions with the ion injection mode;
Remove this photoresist pattern layer with remove be positioned at this epitaxial loayer top this poly-silicon pattern layer to form polysilicon gate;
Import the alloy in this first doped region, be in close proximity to this first groove to form the one source pole doped region;
Deposit a dielectric layer comprehensively, and in this dielectric layer, make a contact hole, this contact hole is this source doping region of exposed portion at least;
Through this contact hole, inject this second conductivity type dopant in this well region, to form one second doped region at this second channel bottom with the ion injection mode; And
Deposit a metal level on this dielectric layer, and insert this this source doping region of contact hole covering.
7. trench gate metal oxide semiconductor field effect transistor of making according to the method for claim 6 is characterized in that it comprises:
The epitaxial loayer of one first conductivity type;
A plurality of first grooves are positioned at this epitaxial loayer;
One polysilicon gate is positioned at this first groove;
The well region of one second conductivity type; Be positioned between adjacent two these first grooves; The lower edge of this well region has a protrusion downwards corresponding to the middle between adjacent two these first grooves, and this well region has the minimum degree of depth in the side-walls that is adjacent to this first groove; And this protrudes downwards is the cambered surface that an opening makes progress;
The source doping region of a plurality of first conductivity types is adjacent to those first grooves respectively, and its lower edge presents the curved surface that constitutes because of the alloy importing;
One second groove is arranged in the well region of this second conductivity type, and is positioned between adjacent two these first grooves and to be positioned at adjacent two these source dopant interval;
Second doped region of one second conductivity type is positioned at this second channel bottom;
One dielectric layer covers this polysilicon gate, and this dielectric layer also has at least one contact hole and exposes this source doping region to the open air; And
One metal level covers this dielectric layer and this source doping region.
8. trench gate metal oxide semiconductor field effect transistor according to claim 7 is characterized in that wherein said well region has minimum thickness below this second groove.
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| CN102339851B (en) * | 2010-07-15 | 2014-04-23 | 科轩微电子股份有限公司 | Power semiconductor with polysilicon structure at bottom of trench and method for manufacturing same |
| JP5939846B2 (en) * | 2012-03-09 | 2016-06-22 | エスアイアイ・セミコンダクタ株式会社 | Manufacturing method of semiconductor device |
| TW201443999A (en) * | 2013-05-14 | 2014-11-16 | Anpec Electronics Corp | Method for fabricating trench type semiconductor power device |
| TWI686903B (en) * | 2019-02-01 | 2020-03-01 | 綠星電子股份有限公司 | Gate structure of split-gate mosfet and manufacturing method thereof |
| CN111697080A (en) * | 2020-07-21 | 2020-09-22 | 江苏长晶科技有限公司 | Semiconductor unit cell, manufacturing method and semiconductor device |
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| CN1628377A (en) * | 2002-03-29 | 2005-06-15 | 费查尔德半导体有限公司 | Field effect transistor having lateral depletion structure |
| CN1799145A (en) * | 2003-05-31 | 2006-07-05 | 皇家飞利浦电子股份有限公司 | Semiconductor device having an edge termination structure and method of manufacture thereof |
| CN101071826A (en) * | 2002-05-03 | 2007-11-14 | 快捷半导体有限公司 | Low voltage high density trench-gated power device with uniformly doped channel and its edge termination technique |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1628377A (en) * | 2002-03-29 | 2005-06-15 | 费查尔德半导体有限公司 | Field effect transistor having lateral depletion structure |
| CN101071826A (en) * | 2002-05-03 | 2007-11-14 | 快捷半导体有限公司 | Low voltage high density trench-gated power device with uniformly doped channel and its edge termination technique |
| CN1799145A (en) * | 2003-05-31 | 2006-07-05 | 皇家飞利浦电子股份有限公司 | Semiconductor device having an edge termination structure and method of manufacture thereof |
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