CN101640415A - Power supply current equalizing system and current equalizing control method thereof - Google Patents
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Abstract
The invention discloses a power supply current equalizing system, which comprises a main module, at least one slave module, a competitive data bus Bd and a competitive signal bus Bs, wherein the main module is used for controlling a current equalizing circuit, the current equalizing control bus Bc is used for receiving and transmitting control signals sent by the main module, the at least one slave module is arranged in parallel with the main module, the competitive data bus Bd is used for receiving/sending level signals of the main module and the slave module, and the competitive signal bus Bs is used for receiving and transmitting high level signals sent by the main module. The invention also discloses a current sharing control method, which comprises the following steps: determining a main module; and switching the voltage inner ring of the master module and the voltage outer ring of the slave module to the voltage outer ring of the master module through the opening and closing of the electronic switch, and simultaneously switching on the current outer rings of the master module and the slave module. The current equalizing circuit has the advantages of good current equalizing effect, strong operation stability and simple circuit structure.
Description
Technical field
The present invention relates to a kind of power supply current-equalizing system and current equalizing method thereof, relate in particular to a kind of large power supply current-equalizing system and current-sharing control method thereof.
Background technology
Power-supply system is formed in high-power DC power supply module (hereinafter to be referred as module) parallel runnings such as communication, electric power, with the power output of expansion direct current system.This system generally requires the output voltage stabilizing of power supply, and output current stabilization value can be adjusted or regulated continuously by outer monitoring by panel.During the multimode parallel running, each module in the parallel connection is to realize module output load-sharing electric current by flow equalizing circuit.
At present, two or more multimode parallel running, the current-sharing parameter is very undesirable.China formulates the parameter that electric current is divided equally in the large power supply parallel operation with reference to international standard, and (the current-sharing degree of unbalance is referring to GB GB/T19826-2005) weighs with " current-sharing degree of unbalance ".Standard code: the current-sharing degree of unbalance is no more than ± and 5%.Wherein test condition requires the module output current greater than 50% rated current, and adopts during test and be no more than 3 module parallel connections.That is to say that when electric power outputting current during less than 50% rated current the current-sharing degree of unbalance surpasses 5% even bigger situation, GB will not be stipulated.
Technical, the equal stream mode that module parallel operation current-sharing is often adopted traditionally has: output impedance method, principal and subordinate be provided with method, by average current value automatic current equalizing method, maximum current automatic current equalizing method, thermal stress automatic current equalizing method, add the equalizing controller current-equalizing method.
Wherein, adopt the decline of output impedance method voltage regulation, decrease in efficiency, current-sharing effect bad; The principal and subordinate is provided with the method primary module and artificially sets, if when primary module broke down, whole parallel connection power supply group was out of control and cisco unity malfunction is not suitable for the n+1 power-supply system.By the average current value automatic current equalizing method, in actual applications, when bus is short-circuited, or be connected on any one module on the bus can not work the time, the current-sharing bus voltage descends, and will be that each module voltage is transferred to its lower limit and is produced fault.Maximum current method automatic current equalizing, the moving principal and subordinate's module that is provided with, the current-sharing of circuit decision primary module itself is always relatively poor.And non-linear during little electric current makes little electric current current-sharing relatively poor.Add equalizing controller current-equalizing method circuit complexity, the sharing control loop design makes system's instability easily, perhaps the dynamic performance variation.
Summary of the invention
Technical problem to be solved by this invention is the defective that overcomes prior art, and the power supply that a kind of current-sharing is effective, operation stability is strong, relatively simple for structure current-equalizing system is provided.
The invention provides a kind of power supply current-equalizing system, it is characterized in that: comprise
A primary module is used to control flow equalizing circuit, and the outer voltage of power-supply system is provided, the output voltage of control parallel power supply system,
A sharing control bus B c is used to receive and transmit the control signal that primary module sends,
At least one is arranged in parallel with described primary module from module,
A competition data/address bus Bd is used to receive/send primary module and from the data-signal of module,
A compete signal bus B s is used to receive and transmit the high level signal that primary module sends.
Wherein, described primary module comprises
The MCU1 microcomputer chip is used for to competition data/address bus Bd and compete signal bus B s output/reception data and level signal,
Outer voltage is used for the voltage of control system;
Voltage inter-loop is used for making module export default voltage separately in competition process;
Current inner loop and electric current outer shroud are used for module is carried out current limliting separately, and current inner loop is used for the limiting module maximum output current, and the electric current outer shroud is used for user's outside to be adjusted,
Insert by electronic switch Sa1 control by MCU1 in described outer voltage
Sb1 is used to switch to outer voltage work and inserts the electric current outer shroud.Sb1 and Sc1 are the interlock electronic switches, and sequence of movement is to connect Sb1 earlier to disconnect Sc1 then rapidly, guarantees that Voltage loop can open loop.
Describedly comprise from module
The MCU2 microcomputer chip is used for to competition data/address bus Bd and compete signal bus B s output/reception data and level signal,
Outer voltage is used for the voltage of control system;
Voltage inter-loop is used for making module export default voltage separately in competition process;
Current inner loop and electric current outer shroud are used for module is carried out current limliting separately.
Insert by electronic switch Sa2 control by MCU2 in described outer voltage,
Sb2 is used to switch to outer voltage work and inserts the electric current outer shroud.Sb2 and Sc2 are the interlock electronic switches, and sequence of movement is to connect Sb2 earlier to disconnect Sc2 then rapidly, guarantees that Voltage loop can open loop.
Between described control signal that is input to each module and described sharing control bus B c, be provided with the current-sharing regulator potentiometer, by regulating the master and slave module potentiometer in control signal loop separately, with the proportionality constant of regulation voltage ring (PID), to reach the current-sharing degree of unbalance of regulating master and slave module in parallel.
Described parallel connection can be provided with 1～15 from module.
The present invention also provides a kind of current-sharing control method, adopts aforesaid power supply current-equalizing system, and this method comprises:
Determine primary module;
By the orderly folding of electronic switch, all switch to the outer voltage of primary module with primary module with from module by voltage inter-loop, connect all modules electric current outer shroud separately simultaneously.
Described definite primary module comprises:
Bs is made as low level, triggers the competition beginning;
Each module in parallel is posted a letter/is collected mail to Bd, and every module content of posting a letter comprises the address information of module self;
In the module in parallel predetermined one post a letter/collection of letters end cycle after, from the module of parallel connection, automatic arbitration goes out a primary module.
The described primary module of arbitrating out comprises:
The transmission signal period of a standard of each module is made up of 6 Bit
When any module detects Bs and is low level, begin competition, prepare to send out the data of 6 Bit toward the Bd data/address bus, preceding 5 Bit be 2 scale codings of this module's address, a high position preceding low level after, send the 6th Bit again,
Each module sends data simultaneously, receives the data of Bd data/address bus, if module sends 0 level and receives that Bd data/address bus data are 1, this module withdraws from the primary module competition immediately in advance, no longer sends data.
If a module is until send last 1 Bit, and the data that receive the Bd data/address bus are 0 level, and this moment, this module was changed to primary module automatically, and to Bs bus output high level, sealed all modules and send compete signals, and the primary module arbitrated procedure finishes.
Because adopt technique scheme, the present invention has following beneficial effect:
1) host-guest architecture mode
The host-guest architecture mode is adopted in module current-sharing in parallel.Primary module sends and receives compete signal (asymmetric by address code of module etc.) by module group in parallel by special-purpose competition bus (2 line), arbitrates out primary module.If can not arbitrate primary module then restart the competition arbitrated procedure.
2) Voltage loop control mode
Under the module parallel voltage-stabilizing running status, flow equalizing circuit is controlled by outer voltage, and under the constant voltage output state, electric current loop does not participate in the sharing control process.Under the limited current state, the electric current of module is finished by current-limiting circuit separately, and it is the same to set each module current limliting set point, does not just have equal flow problem.
3) primary module lifelong tenure
Finish in case produce the primary module arbitration, competition stops immediately.No matter the new module (module of this power-supply system can warm swap) or in service when having module to withdraw from (not being primary module) that adds, each module can not start module competition program.As long as the primary module operate as normal, primary module is a lifelong tenure.
4) inside and outside control ring switches
After primary module was arbitrated successfully, the outer voltage that primary module (Master) provides was as the outer voltage of whole system, disconnected by electronic switch from the voltage inter-loop and the outer voltage of module (Slave), switched to the outer voltage of primary module.
5) module sharing control process is made of 4 rings, under the voltage stabilizing state, is that the outer voltage of public system is finished the sharing control under the voltage stabilizing state of system by the outer voltage of primary module.
Every module all is made up of voltage inter-loop, current inner loop, outer voltage, electric current outer shroud 4 rings.Outer voltage and electric current outer shroud can be adjusted or given by the watch-dog remote regulating by Users panel.
6) reliability design
Before primary module was arbitrated successfully, each module all worked in ring in voltage inter-loop, the current limliting, and output is by default voltage value and the decision of acquiescence cut-off current.Guarantee module in competition primary module process (time is very short generally in the mS level), the basic output of system and basic all stream modes guarantee the reliable and stable of system.After the primary module arbitration finishes, connect system's outer shroud to working stability, each module (comprising primary module) voltage control loop switches to system's outer shroud in order, and whole competition, control procedure are finished.
Description of drawings
Fig. 1 is a circuit diagram of the present invention;
Fig. 2 to Fig. 5 is relatively schematic diagrames of competition data of the present invention.
Embodiment
Shown in 1 figure, the circuit diagram of the embodiment of power supply current-equalizing system of the present invention, wherein Bing Lian DC power supplier (hereinafter to be referred as module) is 2.
Determine the competition process of primary module
A) powered on originally or when not having primary module to produce, Bs is a low level, triggers the competition beginning.
B) each module is posted a letter/is collected mail toward Bd.Every module content of posting a letter is protected the address information (address is not reproducible in the module in parallel) that contains module self.
C) arrange in the module in parallel one send out/collection of letters end cycle after, arbitrate out a primary module (if unsuccessful then repeat a competing cycle) up to arbitrating successfully.
D) after arbitrating successfully, primary module is connected (electronic switch Sa1 or Sa2 among Fig. 5 close) with its voltage control loop, and to Bs output high level, the sign competition is arbitrated successfully.Through moment time-delay, wait primary module outer shroud working stability after, all modules in parallel are closed electronic switch Sb1, Sb2 earlier, the back disconnects Sc1, Sc2, the Voltage loop that makes all modules by interior ring orderly switch to system voltage outer shroud (being the outer voltage of primary module).Handoff procedure guarantees that system can open loop.
E) when Bs is high level, regardless of being the module of competing or newly adding module or have module (except that primary module) to withdraw from that the high level disabled module of Bs is posted a letter toward Bd.When the primary module fault or when withdrawing from, not having module to keep the Bs bus is high level, makes Bs become low level, triggers new competition.
Send out/collection of letters periodic signal and arbitrated procedure analysis
A) the transmission signal period of every module standard is formed (may not distribute 6 Bit and drop by the wayside competition) by 6 Bit, and competition process module signalling undesired signal is synchronous.
B) when any module detects Bs and is low level, begin competition, prepare to send out the data (Bit0～Bit5) of 6 Bit toward the Bd data/address bus.Preceding 5 Bit are 2 scale codings of this module's address, high-order at preceding low level in the back (2 scale codings as the module of address 3# are 00011, and sending order is 00011), send the 5th Bit (being fixed as 0 level) again.Whole transmission sequence is 000110.
C) every module sends data simultaneously, receives the data of Bd data/address bus.In case certain module sends 0 level and receives that Bd data/address bus data are 1, has illustrated that more high address value module participates in the competition, this module withdraws from the primary module competition immediately in advance, no longer sends data.
D) if certain module is not dropped by the wayside competition, adhere to sending last 1 Bit (being Bit5), and the data that receive the Bd data/address bus are 0 level, this moment, this module was changed to primary module automatically, and to Bs bus output high level, seal all modules and send compete signal, the primary module arbitrated procedure finishes.
To shown in Figure 5, address 1# and address 5# module competition process are as follows as Fig. 2:
A) as Fig. 2,1# and 5# module synchronized transmission competition data conditions: 1. 1# and 5# module synchronized transmission data, sending order is B4-B3-B2-B1-B0-B5; When 2. the 1# module sent to B2 (2Bit), because the 1# module is received 1 level of being sent by the 5# module from the Bd bus, the 1# module withdrawed from competition in advance; 3. the 5# module continue to post a letter/collect mail, wait until that always the 5# module sends 0 level of B5 (last 1 Bit) and finish, it never occurred and send 0 level and receive the situation of 1 level from the Bd bus, the 5# module is changed to primary module automatically, competition finishes.
B) as Fig. 3, the 5# module is posted a letter and is lagged behind the situation of 1# module 1.5Bit (asynchronous):
1. the 1# module is posted a letter earlier/is collected mail, send out/receive 1 half Bit after, the 5# module begins to post a letter;
2. the 1# module is posted a letter the second half section of B1, receives 1 level of sending from the 5# module (being the B2 level of 5#) from the Bd bus, and the 1# module withdraws from competition in advance;
3. the 5# module continue to post a letter/collect mail, 0 level that sends B5 up to the 5# module finishes, receiving the Bd bus is 0 level, the 5# module is changed to primary module, competition finishes.
C) as Fig. 4, the 5# module is posted a letter and is lagged behind the situation of 1# module 2Bit (asynchronous):
1. the 1# module is posted a letter earlier/is collected mail, send out/receive 2 Bit after, the 5# module begins to post a letter;
2. the 1# module is posted a letter until B5, never when sending 0 level, the 1# module receives Bd bus 1 level, after the 1# module is received/is posted a letter B5 and finishes, the 1# module is changed to primary module, it is 1 level that the 1# module is put the Bs bus, the forced termination competition process, the 5# module is forced to stop competition midway by 1 level of Bs bus, and competition finishes.
D) as Fig. 5, the 5# module is posted a letter and is lagged behind the situation of 1# module 2.5Bit (asynchronous):
1. the 1# module is posted a letter earlier/is collected mail, send out/receive 2 half Bit after, the 5# module begins to post a letter;
2. post a letter preceding half section of B5 of 1# module received 1 level (being the B2 level of 5#) from the 5# module from the Bd bus, and the 1# module withdraws from competition;
3. the 5# module continue to post a letter/collect mail, after 0 level that the 5# module is sent B5 finished, the Bd bus was 0 level, the 5# module is changed to primary module, competition finishes.
By above example analyses, in the module group in parallel, primary module is unique, and the address value of module in parallel and the sequential scheduling factor that module powers on are depended in the generation of primary module.Under the situation about powering at the same time, the general high module of address value is a primary module.
Flow equalizing circuit control principle of the present invention is as follows:
Among Fig. 1, be outer voltage to module 1: amplifier 1A1; 1A2 is the electric current outer shroud; 1A3 is a voltage inter-loop; 1A4 is a current inner loop.To module 2, circuit is symmetry fully.
A) before primary module produced, electronic switch Sa1, Sa2 disconnected, because Bs is that low level also disconnects electronic switch Sb1, Sb2, electronic switch Sc1, Sc2 connect simultaneously.Each module all works in separately the current inner loop and voltage inter-loop.Voltage inter-loop makes module export default voltage and module maximum current limliting (ring is set on the maximum output current value of module in the blocks current) separately separately.Outer voltage and electric current outer shroud all are disconnected.At this moment each module current-sharing is relatively poor.
B) suppose competition as a result primary module be module 1, MCU1 (the built-in single-chip microcomputer of module 1) makes Sa1 connect the outer voltage of primary module earlier, prepares for each module switches to the system voltage outer shroud.Because Sb1 and Sb2 disconnect, Sc1 and Sc2 closure, Voltage loop and current loop control at this moment all modules also work in, then to put Bs be high level to MCU1.
C) Bs is a high level, each module is through of short duration time-delay, behind the outer voltage working stability Deng primary module, electronic switch Sb1, Sb2 are connected earlier, Sc1, Sc2 are turn-offed in the time-delay back slightly, each module work all switches to system voltage outer shroud (the outer voltage 1A1 of primary module as the voltage control loop of all ground modules in the parallel connection time, we are referred to as system's outer shroud) reposefully by voltage inter-loop, and simultaneously module electric current outer shroud separately inserts.Electric current loop is controlled simultaneously by module current inner loop (being set in 110%Ie) and electric current outer shroud (can be given by the outside) separately.
D) voltage inter-loop and current inner loop are by factory setting, and outer voltage and electric current outer shroud can be given by the user.
Concrete enforcement
The model machine measurement data
By " national relay quality supervision and inspection " center " " type-test report " tables of data that my 3 power modules are provided is as follows:
The production run data
My company in real system is used, much 12 power module parallel runnings, parallel operation current-sharing degree of unbalance is not more than 1%.
The present invention competes program by software, by compete signal bus (Bs) and competition data/address bus (Bd).Intelligence is arbitrated out unique primary module from module in parallel.
The primary module lifelong tenure
In case primary module produces, the Bs bus keeps 1 level, blocks all modules in parallel, forbids its operation competition program.No matter new in the system as long as main mould normally moves, the Bs bus keeps high level, add module or withdraw from module (because of power module is charged hot plug, add or withdraw from module be very easy to), can not compete primary module again.
When primary module dead electricity or primary module were out of service, Bs became 0 level.At this moment just can compete primary module again.
The hardware designs of equalizing control circuit
Before competition finished, each module in the parallel connection all worked in separately voltage inter-loop and current inner loop (dicyclo), set up stable output.
When the primary module arbitrated procedure finishes, primary module is at first connected its outer voltage (but this moment all modules in the module in parallel still by separately voltage inter-loop and the control of current inner loop dicyclo) by electronic switch, is high level by primary module output control signal set Bs bus afterwards.Each module suitable time-delay, behind the outer voltage working stability Deng primary module, all modules in the parallel connection, earlier by electronic switch (as Sb1 among Fig. 1 and Sb2) connecting system outer shroud, this moment, voltage inter-loop, current inner loop, outer voltage, electric current outer shroud are worked simultaneously, and module is in of short duration labile state.
Very fast, by the rapid voltage inter-loop that disconnects separately of electronic switch (as Sc1 among Fig. 1 and Sc2), finish each module and switch to system's outer shroud (making current outer shroud simultaneously) reposefully by voltage inter-loop, module works in 3 ring controls (being the current inner loop of the electric current outer shroud+separately of system's outer shroud+separately), finishes whole competition, control procedure.
The current limliting of power module is finished jointly by separately current inner loop and electric current outer shroud, and current inner loop is set to 110% of rated current, and the electric current outer shroud is given by the user.
Same electrical voltage system outer shroud control down, influence the current-sharing degree of unbalance variation of module by the discreteness of each modular circuit, change the PID proportionality constant of its outer voltage by the potentiometer of regulating each module control signal loop, regulate the current-sharing degree of unbalance of module in parallel.
It should be noted that at last: above embodiment only in order to the explanation the present invention and and unrestricted technical scheme described in the invention; Therefore, although this specification has been described in detail the present invention with reference to each above-mentioned embodiment,, those of ordinary skill in the art should be appreciated that still and can make amendment or be equal to replacement the present invention; And all do not break away from the technical scheme and the improvement thereof of the spirit and scope of the present invention, and it all should be encompassed in the claim scope of the present invention.
Claims (8)
1, a kind of power supply current-equalizing system is characterized in that: comprise
A primary module is used to control flow equalizing circuit, and the outer voltage of power-supply system is provided, the output voltage of control parallel power supply system,
A sharing control bus B c is used to receive and transmit the control signal that primary module sends,
At least one is arranged in parallel with described primary module from module,
A competition data/address bus Bd is used to receive/send primary module and from the data-signal of module,
A compete signal bus B s is used to receive and transmit the high level signal that primary module sends.
2, power supply current-equalizing system according to claim 1, it is characterized in that: described primary module comprises
The MCU1 microcomputer chip is used for to competition data/address bus Bd and compete signal bus B s output/reception data and level signal,
Outer voltage is used for the voltage of control system;
Voltage inter-loop is used for making each module export default voltage separately in competition process;
Current inner loop and electric current outer shroud are used for each module self is carried out current limliting, and current inner loop is used for the limiting module maximum output current, and the electric current outer shroud is used for user's outside to be adjusted,
Insert by electronic switch Sa1 control by MCU1 in described outer voltage,
Sb1 is used to switch to outer voltage work and inserts the electric current outer shroud,
Sb1 and Sc1 are the interlock electronic switches, and sequence of movement is to connect Sb1 earlier to disconnect Sc1 then rapidly, guarantees that Voltage loop can open loop.
3, power supply current-equalizing system according to claim 2 is characterized in that: describedly comprise from module
The MCU2 microcomputer chip is used for to competition data/address bus Bd and compete signal bus B s output/reception data and level signal,
Outer voltage is used for the voltage of control system;
Voltage inter-loop is used for making competition process, each module self output default voltage;
Current inner loop and electric current outer shroud are used for each module self is carried out current limliting, and current inner loop is used for the limiting module maximum output current, and the electric current outer shroud is used for user's outside and adjusts;
Insert by electronic switch Sa2 control by MCU2 in described outer voltage;
Sb2 is used to switch to outer voltage work and inserts the electric current outer shroud, and Sb2 and Sc2 are the interlock electronic switches, and sequence of movement is to connect Sb2 earlier to disconnect Sc2 then rapidly, guarantees that Voltage loop can open loop.
4, power supply current-equalizing system according to claim 3, it is characterized in that: between described control signal that is input to each module and described sharing control bus B c, be provided with the current-sharing regulator potentiometer, by regulating the potentiometer in master and slave module control signal loop, with the proportionality constant of regulation voltage ring, to reach the current-sharing degree of unbalance of regulating master and slave module in parallel.
5, according to each described power supply current-equalizing system in the claim 1 to 4, it is characterized in that: described parallel connection can be provided with 1～15 from module.
6, a kind of current-sharing control method adopts as each described power supply current-equalizing system in the claim 1 to 5, and it is characterized in that: this method comprises:
Determine primary module;
By the orderly folding of electronic switch, all switch to the outer voltage of primary module with primary module with from module by voltage inter-loop, connect all modules electric current outer shroud separately simultaneously.
7, current-sharing control method according to claim 6 is characterized in that: described definite primary module comprises:
Bs is made as low level, triggers the competition beginning;
Each module in parallel is posted a letter/is collected mail to Bd, and every module content of posting a letter comprises the address information of module self;
In the module in parallel predetermined one post a letter/collection of letters end cycle after, from the module of parallel connection, automatic arbitration goes out a primary module.
8, current-sharing control method according to claim 7 is characterized in that: the described primary module of arbitrating out comprises:
The transmission signal period of a standard of each module is made up of 6 Bit,
When any module detects Bs and is low level, begin competition, prepare to send out the data of 6 Bit toward the Bd data/address bus, preceding 5 Bit be 2 scale codings of this module's address, a high position preceding low level after, send the 6th Bit again,
Each module sends data simultaneously, receives the data of Bd data/address bus, if module sends 0 level and receives that Bd data/address bus data are 1, this module withdraws from the primary module competition immediately in advance, no longer sends data,
If a module is until send last 1 Bit, and the data that receive the Bd data/address bus are 0 level, and this moment, this module was changed to primary module automatically, and to Bs bus output high level, sealed all modules and send compete signals, and the primary module arbitrated procedure finishes.
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| CN103187780A (en) * | 2011-12-28 | 2013-07-03 | 艾默生网络能源***北美公司 | Ultra-large power supply system and monitoring method and system for ultra-large power supply system |
| CN103378594A (en) * | 2012-04-21 | 2013-10-30 | 深圳市金威源科技股份有限公司 | Digitization power supply parallel operation current sharing method and current sharing system |
| CN104009465A (en) * | 2014-05-06 | 2014-08-27 | 华南理工大学 | Digital current sharing method for non-master dispersing type direct current power system |
| CN107147290A (en) * | 2017-06-07 | 2017-09-08 | 联想(北京)有限公司 | Power module and power-supply system |
| CN108933436A (en) * | 2018-08-07 | 2018-12-04 | 中国航空工业集团公司雷华电子技术研究所 | A kind of DC power supply parallel system |
| CN109274089A (en) * | 2018-11-26 | 2019-01-25 | 江苏兆能电子有限公司 | A kind of digital current-sharing method of vehicle power module |
| CN111082412A (en) * | 2019-12-30 | 2020-04-28 | 科华恒盛股份有限公司 | Synchronous current sharing method for parallel operation system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103187780A (en) * | 2011-12-28 | 2013-07-03 | 艾默生网络能源***北美公司 | Ultra-large power supply system and monitoring method and system for ultra-large power supply system |
| CN103187780B (en) * | 2011-12-28 | 2015-04-01 | 艾默生网络能源***北美公司 | Ultra-large power supply system and monitoring method and system for ultra-large power supply system |
| CN103378594A (en) * | 2012-04-21 | 2013-10-30 | 深圳市金威源科技股份有限公司 | Digitization power supply parallel operation current sharing method and current sharing system |
| CN103378594B (en) * | 2012-04-21 | 2015-09-02 | 深圳市金威源科技股份有限公司 | A kind of digitlization power parallel machine current equalizing method and current-equalizing system |
| CN104009465A (en) * | 2014-05-06 | 2014-08-27 | 华南理工大学 | Digital current sharing method for non-master dispersing type direct current power system |
| CN104009465B (en) * | 2014-05-06 | 2016-08-24 | 华南理工大学 | A kind of digital current-sharing method of dereliction decentralized DC power system |
| CN107147290A (en) * | 2017-06-07 | 2017-09-08 | 联想(北京)有限公司 | Power module and power-supply system |
| CN108933436A (en) * | 2018-08-07 | 2018-12-04 | 中国航空工业集团公司雷华电子技术研究所 | A kind of DC power supply parallel system |
| CN108933436B (en) * | 2018-08-07 | 2021-10-22 | 中国航空工业集团公司雷华电子技术研究所 | Direct current power supply parallel system |
| CN109274089A (en) * | 2018-11-26 | 2019-01-25 | 江苏兆能电子有限公司 | A kind of digital current-sharing method of vehicle power module |
| CN111082412A (en) * | 2019-12-30 | 2020-04-28 | 科华恒盛股份有限公司 | Synchronous current sharing method for parallel operation system |
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