CN101620981B - Inorganic film etching method in semiconductor manufacture procedure and shallow groove isolation area forming method - Google Patents
Inorganic film etching method in semiconductor manufacture procedure and shallow groove isolation area forming method Download PDFInfo
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- CN101620981B CN101620981B CN2008101159594A CN200810115959A CN101620981B CN 101620981 B CN101620981 B CN 101620981B CN 2008101159594 A CN2008101159594 A CN 2008101159594A CN 200810115959 A CN200810115959 A CN 200810115959A CN 101620981 B CN101620981 B CN 101620981B
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Abstract
The invention discloses an inorganic film etching method in a semiconductor manufacture procedure, which comprises the following steps: cleaning an etching reaction chamber by etching gases for etching an inorganic film; running a semiconductor substrate provided with the inorganic film and exposing partial mask layer of the inorganic film; and taking the mask layer as a mask, and removing the exposed partial inorganic film by reaction gases containing the etching gases. The method can strengthen the consistency of the environment in the etching reaction chamber and does not need equipment improvement. The invention also discloses a shallow groove isolation area forming method, which comprises the following steps: cleaning an etching reaction chamber by etching gases for forming a shallow groove; running a semiconductor substrate on which a patterned mask layer is arranged; taking the pattern mask layer as a mask, and etching the semiconductor substrate in partial depth to form the shallow groove; and filling the shallow groove with an isolation layer to form a shallow groove isolation area. The method can strengthen the consistency of the environment in the etching reaction chamber when the shallow groove is formed, and does not need equipment improvement.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, inorganic film etching method and shallow channel isolation area formation method in particularly a kind of manufacture of semiconductor.
Background technology
In the manufacture of semiconductor, be usually directed to multistep forms figure in the inorganic film of determining etching operation.As shown in Figure 1, the step of carrying out described etching operation comprises step 101: operation has the semiconductor-based end of the mask layer of described inorganic film and the described inorganic film of expose portion; Step 102: with described mask layer is mask, removes the described inorganic film of exposed portions.Before carrying out described etching operation, also comprise in order to remove the pre-cleaning operation of described etching reaction chamber inner wall residue.Described inorganic film comprises polysilicon layer, dielectric layer and metal level.Described dielectric layer comprises interlayer dielectric layer (ILD and/or IMD), hard mask layer and etching stop layer.
Usually, the using plasma etching technics is removed the described inorganic film of exposed portions.Yet, in the practice, experience described etching operation after, usually can residually have the rete and the position particulate thereon of certain thickness and distribution on the reaction chamber inwall.Described particulate easily peels off in the subsequent etching process.The particulate that peels off will and rest on air movement at semiconductor-based the end, form defective and cause rate of finished products to reduce.Thus, in the actual production, before carrying out etching operation, adopt fluorine base gas usually (as SF
6) described reaction chamber is carried out prerinse.
In addition, current, as shown in Figure 2, the step that forms shallow channel isolation area comprises step 201: move the semiconductor-based end that has patterned mask layer on it; Step 202: with described patterned mask layer is mask, the described semiconductor-based end of the etched portions degree of depth, forms shallow trench; Step 203: fill separator to described shallow trench, form shallow channel isolation area.Usually, use plasma etch process and form described shallow trench.After experiencing described etching operation, also can residually have the rete and the position particulate thereon of certain thickness and distribution on the reaction chamber inwall usually.Before carrying out etching operation, also need adopt fluorine base gas usually (as SF
6) described reaction chamber is carried out prerinse.
Yet, actual production is found, after using above-mentioned technology prerinse reaction chamber, particle removing effect is limited, cause when etching operation is carried out at the semiconductor-based end of difference, in described reaction chamber, still may have the particulate that peels off, and the situation that particulate peels off being uncertain, make each residing reaction chamber indoor environment difference of the described semiconductor-based end, cause that etching homogeneity there are differences between each described semiconductor-based end.The consistency that how to strengthen environment in the etching reaction chamber becomes those skilled in the art's problem demanding prompt solution.
On January 24th, 2007, disclosed notification number was for providing a kind of control system and method based on smog of determining separately and dust concentration control blower speed in the Chinese patent application of " CN1899624A ", speed according to smog and dust concentration are regulated air blast automatically is consistent intrasystem smog and dust concentration.
Yet, consider that the etching reaction chamber is to the vacuum degree permissible accuracy, the operating parameter of bleeding of vacuum degree need set in advance in the described reaction chamber in order to keep, if use the consistency of said method intensified response cavity environment, need described reaction chamber is carried out equipment improvement can realize the bleeding accurate adjusting of operating parameter, poor operability.
Summary of the invention
The invention provides inorganic film etching method in a kind of manufacture of semiconductor, can strengthen the consistency of environment in the etching reaction chamber, and need not to carry out equipment improvement;
The invention provides a kind of shallow channel isolation area formation method, can when form shallow trench, strengthen the consistency of environment in the etching reaction chamber, and need not to carry out equipment improvement.
Inorganic film etching method in a kind of manufacture of semiconductor provided by the invention comprises:
Etching gas etching reaction chamber when adopting the etching inorganic film;
Operation has the semiconductor-based end of the mask layer of described inorganic film and the described inorganic film of expose portion;
With described mask layer is mask, adopts the reacting gas that comprises described etching gas to remove the described inorganic film of exposed portions.
Alternatively, carry out described cleaning operation after, form etching exchange layer at described etching reaction chamber inner wall, comprise the element that comprises in the described etching gas in the described etching exchange layer; Alternatively, before carrying out described cleaning operation, also comprise in order to remove the pre-cleaning operation of described etching reaction chamber inner wall residue; Alternatively, using plasma technology is carried out described cleaning operation and pre-cleaning operation; Alternatively, when carrying out described pre-cleaning operation, prerinse gas comprises SF
6, described SF
6Range of flow be 100～1000sccm; Alternatively, described prerinse gas also comprises O
2, described O
2Range of flow be 10～100sccm; Alternatively, when carrying out described pre-cleaning operation, reaction power is 500～2000W; Alternatively, when carrying out described pre-cleaning operation, reaction pressure is 10～100mT; Alternatively, when carrying out described pre-cleaning operation, the described pre-cleaning operation duration is 5～20 seconds;
Alternatively, described inorganic film comprises a kind of in polysilicon layer, dielectric layer or the metal level; Alternatively, when described inorganic film comprises polysilicon layer, comprise SiCl in the described etching gas
4, described SiCl
4Range of flow be 10～300sccm; Alternatively, described inorganic film comprises dielectric layer, when described dielectric layer is oxide layer, comprises C in the described etching gas
4F
8, range of flow be 10～300sccm; Alternatively, described inorganic film comprises dielectric layer, when described dielectric layer is nitration case or nitrogen oxide layer, comprises CH in the described etching gas
2F
2, range of flow be 10～300sccm; Alternatively, also comprise CF in the described etching gas
4, range of flow be 10～100sccm; Alternatively, when carrying out described cleaning operation, reaction power is 500～2000W; Alternatively, when carrying out described cleaning operation, reaction pressure is 10～100mT; Alternatively, the duration of carrying out described cleaning operation is 5～20 seconds.
A kind of shallow channel isolation area formation method provided by the invention comprises:
Adopt the etching gas etching reaction chamber when forming shallow trench;
Move the semiconductor-based end that has patterned mask layer on it;
With described patterned mask layer is mask, the described semiconductor-based end of the etched portions degree of depth, forms shallow trench;
Fill separator to described shallow trench, form shallow channel isolation area.
Alternatively, carry out described cleaning operation after, form etching exchange layer at described etching reaction chamber inner wall, comprise the element that comprises in the described etching gas in the described etching exchange layer; Alternatively, before carrying out described cleaning operation, also comprise in order to remove the pre-cleaning operation of described etching reaction chamber inner wall residue; Alternatively, using plasma technology is carried out described cleaning operation and pre-cleaning operation; Alternatively, when carrying out described pre-cleaning operation, prerinse gas comprises SF
6, described SF
6Range of flow be 100～1000sccm; Alternatively, described prerinse gas also comprises O
2, described O
2Range of flow be 10～100sccm; Alternatively, when carrying out described pre-cleaning operation, reaction power is 500～2000W; Alternatively, when carrying out described pre-cleaning operation, reaction pressure is 10～100mT; Alternatively, when carrying out described pre-cleaning operation, the described pre-cleaning operation duration is 5～20 seconds; Alternatively, described etching gas comprises SiCl
4, described SiCl
4Range of flow be 10～300sccm; Alternatively, when carrying out described cleaning operation, reaction power is 500～2000W; Alternatively, when carrying out described cleaning operation, reaction pressure is 10～100mT; Alternatively, the duration of carrying out described cleaning operation is 5～20 seconds.
Compared with prior art, technique scheme has the following advantages:
Inorganic film etching method in the manufacture of semiconductor that technique scheme provides, at at the semiconductor-based end of the mask layer by having described inorganic film and the described inorganic film of expose portion in operation, etching gas etching reaction chamber when adopting the etching inorganic film in advance, can make before described etching operation is carried out, on described reaction chamber inwall, form the etching exchange layer that one deck comprises described etching gas interior element, make in etching process when the peeling off of described reaction chamber inwall particulate taken place, described particulate easily is the particle of corresponding described etching gas interior element, and the possibility of the accessory substance that produces when having reduced to introduce anter etching operation of the semiconductor-based end, and then make the consistency that strengthens described etching reaction cavity environment become possibility;
The shallow channel isolation area formation method that technique scheme provides, by the operation its on have the semiconductor-based end of patterned mask layer before, adopt the etching gas etching reaction chamber when forming shallow trench in advance, can make before described etching operation is carried out, on described reaction chamber inwall, form the etching exchange layer that one deck comprises described etching gas interior element, make when the peeling off of described reaction chamber inwall particulate taken place in forming the process of shallow trench, described particulate easily is the particle of corresponding described etching gas interior element, and the possibility of the accessory substance that produces when having reduced to introduce anter etching operation of the semiconductor-based end, and then make the consistency that strengthens described etching reaction cavity environment become possibility.
Description of drawings
Fig. 1 is the schematic flow sheet of inorganic film in the etching semiconductor processing procedure in the explanation prior art;
Fig. 2 is for forming the schematic flow sheet of shallow channel isolation area in the explanation prior art;
Fig. 3 is the schematic flow sheet of inorganic film in the etching semiconductor processing procedure of the explanation embodiment of the invention;
The etching gas of Fig. 4 during for the employing etching inorganic film of the explanation embodiment of the invention cleans the structural representation of the described etching reaction chamber in back;
Fig. 5 is the testing result schematic diagram of the effect of the explanation embodiment of the invention;
Fig. 6 is the schematic flow sheet of the formation shallow channel isolation area of the explanation embodiment of the invention.
Embodiment
Although below with reference to accompanying drawings the present invention is described in more detail, wherein represented the preferred embodiments of the present invention, be to be understood that those skilled in the art can revise the present invention described here and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensive instruction for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.In the following description, be not described in detail known function and structure, because they can make the present invention because unnecessary details and confusion.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details, for example, change into another embodiment by an embodiment according to relevant system or relevant commercial restriction to realize developer's specific objective.In addition, will be understood that this development may be complicated and time-consuming, but only be routine work to those skilled in the art.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.Will be clearer according to following explanation and claims advantages and features of the invention.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
As shown in Figure 3, the concrete steps of using inorganic film in the method etching semiconductor processing procedure provided by the invention comprise:
Step 301: the etching gas etching reaction chamber when adopting the etching inorganic film.
In the actual production, before carrying out etching operation, adopt fluorine base gas usually (as SF
6) described reaction chamber is carried out prerinse, after removing the described etching operation of experience, residual rete with certain thickness and distribution and position particulate thereon on the reaction chamber inwall.
Yet, actual production is found, after using above-mentioned technology prerinse reaction chamber, particle removing effect is limited, cause when etching operation is carried out at the semiconductor-based end of difference, in described reaction chamber, still may have the particulate that peels off, and the situation that particulate peels off being uncertain, make each residing reaction chamber indoor environment difference of the described semiconductor-based end, cause that etching homogeneity there are differences between each described semiconductor-based end.The consistency that how to strengthen environment in the etching reaction chamber becomes the subject matter that the present invention solves.
The present inventor thinks after analyzing, since particle removing effect is limited, so, will comprise the particulate that peels off in the described reaction chamber when carrying out etching operation; Current, the reason that technological requirement strengthens particle removing effect is, the particulate that peels off is for forming and adhere to the accessory substance of the etching operation of described reaction chamber inwall in etching operation before, the material of described accessory substance differs from described etching gas and material to be etched at the described semiconductor-based end, both be difficult for as etching gas and the described material to be etched of auxiliary etch, also be difficult for being removed by described etching gas, cause the particulate that peels off easily to be deposited at described the semiconductor-based end and form particle defects as material to be etched.Thus, how to utilize the described particulate that peels off to become the conforming direction that strengthens environment in the etching reaction chamber.
The present inventor's undergoing analysis and practice back propose, at at the semiconductor-based end of the mask layer by having described inorganic film and the described inorganic film of expose portion in operation, on described reaction chamber inwall, form the etching exchange layer that one deck comprises described etching gas interior element, make in etching process when the peeling off of described reaction chamber inwall particulate taken place, described particulate easily is the particle of corresponding described etching gas interior element, then, can reduce to introduce the possibility of the accessory substance that the semiconductor-based end of anter produces during etching operation, and then, can make the consistency that strengthens described etching reaction cavity environment become possibility.
In the practice, as shown in Figure 4,, the etching gas etching reaction chamber when adopting the etching inorganic film in advance is to form etching exchange layer 20 at the semiconductor-based end 10 of the mask layer by having described inorganic film and the described inorganic film of expose portion in operation.After carrying out described cleaning operation, form etching exchange layer, comprise the element that comprises in the described etching gas in the described etching exchange layer 20 at described etching reaction chamber inner wall 30.
Before carrying out described cleaning operation, also comprise in order to remove the pre-cleaning operation of described etching reaction chamber inner wall residue.But using plasma technology is carried out described cleaning operation and pre-cleaning operation.
When carrying out described pre-cleaning operation, prerinse gas comprises SF
6, described SF
6Range of flow be 100～1000sccm, as 200sccm, 300sccm, 500sccm; Described prerinse gas also comprises O
2, described O
2Range of flow be 10～100sccm, as 20sccm, 30sccm, 50sccm; When carrying out described pre-cleaning operation, reaction power is 500～2000W, as 1000W, 1250W, 1500W; When carrying out described pre-cleaning operation, reaction pressure is 10～100mT, as 50mT, 65mT, 80mT; When carrying out described pre-cleaning operation, the described pre-cleaning operation duration was 5～20 seconds, as 10 seconds, 12 seconds, 15 seconds.
Described inorganic film comprises a kind of in polysilicon layer, dielectric layer or the metal level.
As the first embodiment of the present invention, described inorganic film comprises polysilicon layer; The operation of the described inorganic film of etching can be after forming polycrystalline silicon grid layer, and the described polycrystalline silicon grid layer of etching is to form the operation of polysilicon gate.
When described inorganic film comprises polysilicon layer, comprise SiCl in the described etching gas
4, described SiCl
4Range of flow be 10～300sccm, as 30sccm, 90sccm, 120sccm, 150sccm; When carrying out described cleaning operation, reaction power is 500～2000W, as 1000W, 1250W, 1500W; When carrying out described cleaning operation, reaction pressure is 10～100mT, as 50mT, 65mT, 80mT; When carrying out described cleaning operation, the described pre-cleaning operation duration was 5～20 seconds, as 10 seconds, 12 seconds, 15 seconds.
As the second embodiment of the present invention, described inorganic film comprises dielectric layer; Described dielectric layer comprises oxide layer or nitration case/nitrogen oxide layer; When described dielectric layer comprised oxide layer, the operation of the described inorganic film of etching can be after forming described dielectric layer, and the described dielectric layer of etching is to form the operation of through hole; Comprise C in the described etching gas
4F
8, range of flow be 10～300sccm, as 30sccm, 90sccm, 120sccm, 150sccm; When carrying out described cleaning operation, reaction power is 500～2000W, as 1000W, 1250W, 1500W; When carrying out described cleaning operation, reaction pressure is 10～100mT, as 50mT, 65mT, 80mT; When carrying out described cleaning operation, the described pre-cleaning operation duration was 5～20 seconds, as 10 seconds, 12 seconds, 15 seconds.
When described dielectric layer comprised nitration case or nitrogen oxide layer, the operation of the described inorganic film of etching can be after forming described dielectric layer, and the described dielectric layer of etching is to form the operation of hard mask; Perhaps, described dielectric layer is removed the operation on described dielectric layer or barrier layer during as etching stop layer or barrier layer; Comprise CH in the described etching gas
2F
2, range of flow be 10～300sccm, as 30sccm, 90sccm, 120sccm, 150sccm; Also comprise CF in the described etching gas
4, range of flow be 10～100sccm, as 20sccm, 30sccm, 50sccm; When carrying out described cleaning operation, reaction power is 500～2000W, as 1000W, 1250W, 1500W; When carrying out described cleaning operation, reaction pressure is 10～100mT, as 50mT, 65mT, 80mT; When carrying out described cleaning operation, the described pre-cleaning operation duration was 5～20 seconds, as 10 seconds, 12 seconds, 15 seconds.
The existence of described etching exchange layer is difficult to be proved by direct film thickness measuring, but can be by to the gas componant that comprises in the reaction chamber in the etching process and content and detected confirmation.As shown in Figure 5, curve 1 and 2 is corresponding respectively when using conventional method and using method etching inorganic film provided by the invention, use OES (optical emission system, light emission spectrum), by the wavelength that detects carbon (C), nitrogen (N) composition correspondence be the content of the gas that comprises in the reaction chamber that obtains of the light of 348nm.As seen, when using method etching inorganic film provided by the invention, carbon in the reaction chamber, nitrogen content is carbon, the nitrogen content in the reaction chamber when using conventional method.When using method etching inorganic film provided by the invention, when initial, be as good as when carbon content is with the application conventional method in the reaction chamber, and continuing along with etching process, carbon content increases in the reaction chamber, and when using conventional method, along with continuing of etching process, carbon content will reduce in the reaction chamber, and described carbon is only introduced by etching gas, be enough to explanation, when adopting described etching gas etching reaction chamber in advance, on described reaction chamber inwall, formed the etching exchange layer that one deck comprises described etching gas interior element; In etching process, introducing along with etching gas, form dynamic equilibrium in the described reaction chamber gradually, described etching gas is in the etching inorganic film, also can act on the etching exchange layer that adheres to described reaction chamber inwall, and be subjected to described etching gas effect and the partial etching that peels off exchange layer (as comprising the particulate of etching exchange layer material) since have with as described in the identical composition of etching gas, as detected carbon, and remedied the minimizing of carbon content in the reaction chamber, can expand ground, remedy the minimizing of described etching gas in the reaction chamber.
As the third embodiment of the present invention, described inorganic film comprises metal level, and described metal layer material can be aluminium (Al), tungsten (W) or metal composite layer, as titanium nitride (TiN); When described inorganic film comprised metal level, described etching gas was chosen as chlorine-based gas, as SiCl
4, BCl
3Or CCl
4When described inorganic film comprised metal level, the operation of the described inorganic film of etching can be after forming described metal level, and the described metal level of etching is to form the operation of metal interconnecting wires.
At at the semiconductor-based end of the mask layer by having described inorganic film and the described inorganic film of expose portion in operation, etching gas etching reaction chamber when adopting the etching inorganic film in advance, can make before described etching operation is carried out, on described reaction system inwall, form the etching exchange layer that one deck comprises described etching gas interior element, make in etching process when the peeling off of described reaction system inwall particulate taken place, described particulate easily is the particle of corresponding described etching gas interior element, and the possibility of the accessory substance that produces when having reduced to introduce anter etching operation of the semiconductor-based end, and then make the consistency that strengthens described etching reaction system environments become possibility.
Step 302: operation has the semiconductor-based end of the mask layer of described inorganic film and the described inorganic film of expose portion.
Described mask layer comprises resist layer and hard mask layer.Described resist layer comprises photoresist; Described hard mask layer comprises patterned nitration case or nitrogen oxide layer.
In the presents, the described semiconductor-based end make a general reference have on it inorganic film to be etched at goods.Described " RUN " means the operation that the described semiconductor-based end is placed the etching reaction chamber.
Step 303: with described mask layer is mask, adopts the reacting gas that comprises described etching gas to remove the described inorganic film of exposed portions.
Comprise in the reacting gas of described etching gas and also can comprise nitrogen (N
2) wait buffer gas.Remove the operation of the described inorganic film of exposed portions and can adopt any traditional handicraft, do not repeat them here.
Based on identical design, as shown in Figure 6, the present invention also provides a kind of shallow channel isolation area formation method, comprises step 601: adopt the etching gas etching reaction chamber when forming shallow trench; Step 602: move the semiconductor-based end that has patterned mask layer on it; Step 603: with described patterned mask layer is mask, the described semiconductor-based end of the etched portions degree of depth, forms shallow trench; Step 604: fill separator to described shallow trench, form shallow channel isolation area.
In the practice, before having the semiconductor-based end of patterned mask layer in operation on it, the etching gas etching reaction chamber when adopt forming shallow trench in advance is to form etching exchange layer.After carrying out described cleaning operation, form etching exchange layer, comprise the element that comprises in the described etching gas in the described etching exchange layer at described etching reaction chamber inner wall.
Before carrying out described cleaning operation, also comprise in order to remove the pre-cleaning operation of described etching reaction chamber inner wall residue.But using plasma technology is carried out described cleaning operation and pre-cleaning operation.
When carrying out described pre-cleaning operation, prerinse gas comprises SF
6, described SF
6Range of flow be 100～1000sccm, as 200sccm, 300sccm, 500sccm; Described prerinse gas also comprises O
2, described O
2Range of flow be 10～100sccm, as 20sccm, 30sccm, 50sccm; When carrying out described pre-cleaning operation, reaction power is 500～2000W, as 1000W, 1250W, 1500W; When carrying out described pre-cleaning operation, reaction pressure is 10～100mT, as 50mT, 65mT, 80mT; When carrying out described pre-cleaning operation, the described pre-cleaning operation duration was 5～20 seconds, as 10 seconds, 12 seconds, 15 seconds.
Comprise SiCl in the described etching gas
4, described SiCl
4Range of flow be 10～300sccm, as 30sccm, 90sccm, 120sccm, 150sccm; When carrying out described cleaning operation, reaction power is 500～2000W, as 1000W, 1250W, 1500W; When carrying out described cleaning operation, reaction pressure is 10～100mT, as 50mT, 65mT, 80mT; When carrying out described cleaning operation, the described pre-cleaning operation duration was 5～20 seconds, as 10 seconds, 12 seconds, 15 seconds.
By the operation its on have the semiconductor-based end of patterned mask layer before, adopt the etching gas etching reaction chamber when forming shallow trench in advance, can make before described etching operation is carried out, on described reaction system inwall, form the etching exchange layer that one deck comprises described etching gas interior element, make when the peeling off of described reaction system inwall particulate taken place in forming the process of shallow trench, described particulate easily is the particle of corresponding described etching gas interior element, and the possibility of the accessory substance that produces when having reduced to introduce anter etching operation of the semiconductor-based end, and then make the consistency that strengthens described etching reaction system environments become possibility.
It should be noted that not elsewhere specified step all can use conventional methods acquisition, and concrete technological parameter is determined according to product requirement and process conditions.
Although the present invention has been described and has enough described embodiment in detail although describe by the embodiment at this, the applicant does not wish by any way the scope of claims is limited on this details.Other to those skilled in the art advantage and improvement are conspicuous.Therefore, relative broad range the invention is not restricted to represent and the specific detail of describing, equipment and the method and the illustrative example of expression.Therefore, can depart from these details and do not break away from the spirit and scope of the total inventive concept of applicant.
Claims (29)
1. inorganic film etching method in the manufacture of semiconductor is characterized in that, comprising:
Etching gas etching reaction chamber when adopting the etching inorganic film forms the etching exchange layer that one deck comprises described etching gas interior element on described reaction chamber inwall, wherein, using plasma technology is carried out described cleaning operation;
Operation has the semiconductor-based end of the mask layer of described inorganic film and the described inorganic film of expose portion;
With described mask layer is mask, employing comprises the reacting gas of described etching gas and removes the described inorganic film of exposed portions, make that in etching process described particulate easily was the particle of corresponding described etching gas interior element when the peeling off of described reaction chamber inwall particulate taken place.
2. inorganic film etching method in the manufacture of semiconductor according to claim 1 is characterized in that: before carrying out described cleaning operation, also comprise in order to remove the pre-cleaning operation of described etching reaction chamber inner wall residue.
3. inorganic film etching method in the manufacture of semiconductor according to claim 2 is characterized in that: using plasma technology is carried out described pre-cleaning operation.
4. inorganic film etching method in the manufacture of semiconductor according to claim 2 is characterized in that: when carrying out described pre-cleaning operation, prerinse gas comprises SF
6, described SF
6Range of flow be 100～1000sccm.
5. inorganic film etching method in the manufacture of semiconductor according to claim 4 is characterized in that: described prerinse gas also comprises O
2, described O
2Range of flow be 10～100sccm.
6. inorganic film etching method in the manufacture of semiconductor according to claim 2 is characterized in that: when carrying out described pre-cleaning operation, reaction power is 500～2000W.
7. inorganic film etching method in the manufacture of semiconductor according to claim 2 is characterized in that: when carrying out described pre-cleaning operation, reaction pressure is 10～100mT.
8. inorganic film etching method in the manufacture of semiconductor according to claim 2 is characterized in that: when carrying out described pre-cleaning operation, the described pre-cleaning operation duration is 5～20 seconds.
9. inorganic film etching method in the manufacture of semiconductor according to claim 1 is characterized in that: described inorganic film comprises polysilicon layer.
10. inorganic film etching method in the manufacture of semiconductor according to claim 1 is characterized in that: described inorganic film comprises dielectric layer.
11. inorganic film etching method in the manufacture of semiconductor according to claim 1 is characterized in that: described inorganic film comprises metal level.
12. inorganic film etching method in the manufacture of semiconductor according to claim 1 is characterized in that: described inorganic film comprises dielectric layer, when described dielectric layer is oxide layer, comprises C in the described etching gas
4F
8, described C
4F
8Range of flow be 10～300sccm.
13. inorganic film etching method in the manufacture of semiconductor according to claim 1 is characterized in that: described inorganic film comprises dielectric layer, when described dielectric layer is nitration case or nitrogen oxide layer, comprises CH in the described etching gas
2F
2, described CH
2F
2Range of flow be 10～300sccm.
14. inorganic film etching method in the manufacture of semiconductor according to claim 12 is characterized in that: also comprise CF in the described etching gas
4, described CF
4Range of flow be 10～100sccm.
15. inorganic film etching method in the manufacture of semiconductor according to claim 1 is characterized in that: when carrying out described cleaning operation, reaction power is 500～2000W.
16. inorganic film etching method in the manufacture of semiconductor according to claim 1 is characterized in that: when carrying out described cleaning operation, reaction pressure is 10～100mT.
17. inorganic film etching method in the manufacture of semiconductor according to claim 1 is characterized in that: the duration of carrying out described cleaning operation is 5～20 seconds.
18. a shallow channel isolation area formation method is characterized in that, comprising:
Adopt the etching gas etching reaction chamber when forming shallow trench, form the etching exchange layer that one deck comprises described etching gas interior element on described reaction chamber inwall, wherein, using plasma technology is carried out described cleaning operation;
Move the semiconductor-based end that has patterned mask layer on it;
With described patterned mask layer is mask, the described semiconductor-based end of the etched portions degree of depth, form shallow trench, and make that described particulate easily was the particle of corresponding described etching gas interior element when the peeling off of described reaction chamber inwall particulate taken place in etching process;
Fill separator to described shallow trench, form shallow channel isolation area.
19. shallow channel isolation area formation method according to claim 18 is characterized in that: before carrying out described cleaning operation, also comprise in order to remove the pre-cleaning operation of described etching reaction chamber inner wall residue.
20. shallow channel isolation area formation method according to claim 19 is characterized in that: using plasma technology is carried out described pre-cleaning operation.
21. shallow channel isolation area formation method according to claim 19 is characterized in that: when carrying out described pre-cleaning operation, prerinse gas comprises SF
6, described SF
6Range of flow be 100～1000sccm.
22. shallow channel isolation area formation method according to claim 21 is characterized in that: described prerinse gas also comprises O
2, described O
2Range of flow be 10～100sccm.
23. shallow channel isolation area formation method according to claim 19 is characterized in that: when carrying out described pre-cleaning operation, reaction power is 500～2000W.
24. shallow channel isolation area formation method according to claim 19 is characterized in that: when carrying out described pre-cleaning operation, reaction pressure is 10～100mT.
25. shallow channel isolation area formation method according to claim 19 is characterized in that: when carrying out described pre-cleaning operation, the described pre-cleaning operation duration is 5～20 seconds.
26. shallow channel isolation area formation method according to claim 18 is characterized in that: using plasma technology is carried out described cleaning operation.
27. shallow channel isolation area formation method according to claim 18 is characterized in that: when carrying out described cleaning operation, reaction power is 500～2000W.
28. shallow channel isolation area formation method according to claim 18 is characterized in that: when carrying out described cleaning operation, reaction pressure is 10～100mT.
29. shallow channel isolation area formation method according to claim 18 is characterized in that: the duration of carrying out described cleaning operation is 5～20 seconds.
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| CN2008101159594A CN101620981B (en) | 2008-06-30 | 2008-06-30 | Inorganic film etching method in semiconductor manufacture procedure and shallow groove isolation area forming method |
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| CN2008101159594A CN101620981B (en) | 2008-06-30 | 2008-06-30 | Inorganic film etching method in semiconductor manufacture procedure and shallow groove isolation area forming method |
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| CN101620981A CN101620981A (en) | 2010-01-06 |
| CN101620981B true CN101620981B (en) | 2011-07-06 |
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| CN2008101159594A Active CN101620981B (en) | 2008-06-30 | 2008-06-30 | Inorganic film etching method in semiconductor manufacture procedure and shallow groove isolation area forming method |
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| CN1489641A (en) * | 2000-12-29 | 2004-04-14 | ��ķ�о�����˾ | Low Contamination plasma chamber components and method for making same |
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