CN101604974A - A kind of test data compression coding, coding/decoding method and special decoding unit with same run length - Google Patents
A kind of test data compression coding, coding/decoding method and special decoding unit with same run length Download PDFInfo
- Publication number
- CN101604974A CN101604974A CNA2009101165956A CN200910116595A CN101604974A CN 101604974 A CN101604974 A CN 101604974A CN A2009101165956 A CNA2009101165956 A CN A2009101165956A CN 200910116595 A CN200910116595 A CN 200910116595A CN 101604974 A CN101604974 A CN 101604974A
- Authority
- CN
- China
- Prior art keywords
- swimming
- test
- distance
- coding
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
The present invention relates to a kind of LSI circuit test data compressed encoding, coding/decoding method and special decoding unit, belong to the ic test technique field.In order to reduce the memory capacity of test data, shorten test application time, the invention discloses a kind of coding method of LSI circuit test data compression, carry out following steps by stored program computer: at first be elementary cell with the bit string, the distance of swimming to 0 and 1 two type is added up, test data is separated, the length of statistics bit string, utilize two kinds of dissimilar coded system bit strings length to encode again, make coded system both consider that variable length code used short code word to replace long original bit string, consider the correlation between the distance of swimming again, the follow-up distance of swimming for the continuous distance of swimming with same run length can further be represented with short code word, realizes the compression of data; The method of decoding is to utilize the decoding unit of making at this compression method to decompress.
Description
One, technical field
The present invention relates to the ic test technique field, particularly to test data compressing method in built-in self-test (Built-In Self-Test) method of very lagre scale integrated circuit (VLSIC).
Two, technical background
The development of integrated circuit technique make can be in a chip integrated hundreds of millions of device, and can integratedly design and pass through the IP core of checking in advance, as memory core, microprocessor core, DSP are examined etc.The integrated chip of this diversification has become the integrated system that can handle various information, is called as SOC (system on a chip) or System on Chip/SoC SOC.SOC greatly reduces system cost, has shortened the design cycle, has accelerated time to market (TTM), but the test of SOC product faces increasing challenge, as:
1, chip testing point is few, and the test point that can directly control or observe is limited, can only test by the limited I/O pin of chip usually, and the chip internal node is difficult to directly control or observe by macroscopical mechanical device.
2, automatic test equipment ATE costs an arm and a leg, and the design and fabrication technology development speed of chip is faster than the design and fabrication technology development of ATE, and the clock frequency of chip has surpassed the frequency of present state-of-the-art ATE, can't carry out the full speed test.
3, amount of test data is big, and core integrated among the SOC is many more, and required amount of test data is just big more.The capacity that expects the required memory of storage test vector in 2014 is 150 times in 1999, will surpass the storage depth of ATE.
The test of chip has become " bottleneck " of restriction integrated circuit development.For the tester of determining, the capacity of its test channel, test data transmission bandwidth are all determined.Therefore reducing test data can shorten the testing time.
Existing compress technique more typically has: dictionary encoding, LFSR replay kind of a coding method, Huffman and mutation coding method thereof, classical distance of swimming sign indicating number, Golomb sign indicating number, FDR sign indicating number, alternately continuation code (AARLC), EFDR, mixing distance of swimming sign indicating number (HRC), SVIC sign indicating number, Variable-Tail sign indicating number and 9C sign indicating number etc.These coding methods can obtain compression effectiveness preferably, and are especially obvious with FDR sign indicating number and mutation sign indicating number thereof.But the correlation between the distance of swimming is not all considered in these traditional coding methods, and its compression effectiveness is subjected to certain restriction.
Three, summary of the invention
To the objective of the invention is in order guaranteeing, especially not change under the situation of internal structure of scan chain, reduce the memory capacity of test data, shorten test application time at the internal circuit configuration that does not change tested design.
Because test data itself has unique attribute, as includes a large amount of don't-care bits, these don't-care bits are characteristics such as assignment arbitrarily, so can come the compression verification data according to these characteristics, can obtain better compression effectiveness.
The present invention proposes test data compression coding, coding/decoding method.
With the bit string is elementary cell, simultaneously 0 and 1 two type the distance of swimming is added up, test data is separated, the length of statistics bit string, utilize two kinds of dissimilar coded system bit strings length to encode at last, make coded system both consider that variable length code uses short code word to replace long original bit string, considered the correlation between the distance of swimming again, the follow-up distance of swimming for the continuous distance of swimming with same run length can further be represented with short code word, realizes the compression of data; The method that decompresses is to utilize the decoding unit of making at this compression method to decompress.Concrete steps are:
A, employing automatic test pattern Core Generator ATPG generate the complete test set T that determines;
B, described test set is carried out distance of swimming analysis, be about to test data and cut apart by 0 and 1 two type the distance of swimming, don't-care bit wouldn't be filled, and statistics is cut apart the every section possible run length in back;
The correlation between the adjacent distance of swimming is considered earlier in the filling of c, don't-care bit, promptly makes the adjacent continuous run length identical as much as possible, then is to consider to make last run length maximum as far as possible to the filling of remaining don't-care bit;
D, the test data after filling encoded adopt two kinds of coded systems, for the adjacent distance of swimming of equal length and the coded system of follow-up distance of swimming type of service 1, for the coding of other data coded system of type of service 2 then, finally realized the test data compression;
Then, utilize the data importing chip under test of automatic test equipment ATE with compression, carry out decompress(ion) by the decompression circuit of chip under test, the transfer of data after will decompressing at last is to the scan chain of circuit-under-test.
The present invention also provides a kind of test data comprssing coding/decoding method and special decoding unit of realizing having same run length, comprising: finite state machine (FSM), counter and relevant control circuit; The tranmitting data register of decompression circuit closes into described counter and control circuit; Finite state machine will set counter initial state signal respectively and coding input state signal is given counter and control circuit; Data output signal goes out the scan chain of tested design with the transfer of data that decompresses under state machine control, finish whole decompression process.
The characteristics of the inventive method also are:
Include don't-care bit " X " in all test vector among the described test set T, and don't-care bit need account for 35%～95% of test vector figure place.
The fill method of don't-care bit can further expand among the described step c, the single distance of swimming is filled to the distance of swimming of two or more equal length.
Four, description of drawings
The structural representation of special decoding unit.
Five, embodiment
Further describe the present invention to closing chart below.
Test of the present invention is counted compressed encoding and is conciliate compaction coding method.
At first, test data is carried out compressed encoding, adopt test data compressing method, comprise the steps: with same run length by stored program computer
1) described test set is carried out distance of swimming analysis, be about to test data and cut apart by 0 and 1 two type the distance of swimming, don't-care bit wouldn't be filled, and statistics is cut apart the every section possible run length in back;
2) correlation between the adjacent distance of swimming is considered earlier in the filling of don't-care bit, promptly makes the adjacent continuous run length identical as much as possible, then is to consider to make last run length maximum as far as possible to the filling of remaining don't-care bit;
3) test data after filling is encoded adopt two kinds of coded systems, for the adjacent distance of swimming of equal length and the coded system of follow-up distance of swimming type of service 1, for the coding of other data coded system of type of service 2 then, finally realized the test data compression;
Then, utilize the data importing chip under test of automatic test equipment ATE with compression, carry out decompress(ion) by the decompression circuit of chip under test, the transfer of data after will decompressing at last is to the scan chain of circuit-under-test.Determine the generation of test set fully:
Adopt atpg tool to generate the complete test set T that determines, contained test vector can be tested all faults among the test set T fully.To the selection of atpg tool, make the test vector of its generation contain don't-care bit.Following step is exactly that the complete test set T that determines that generates is compressed.
Cataloged procedure:
Data compression coding method of the present invention adopts the unequal-interval coded system, and promptly when dividing into groups, the size of each group has been carried out suitable adjustment according to its frequency of occurrences, the distribution of the distance of swimming in the more realistic data of this new grouping.
The present invention adopts two kinds of different coded systems that test data is encoded: (1) type of service 1 coding schedule coding, this mode attempts replacing the long distance of swimming with short code word, its coding schedule is as shown in table 1, the type of the highest order of code word (Far Left) the expression distance of swimming, 0 this code word of expression is the distance of swimming of 0 type, and 1 this code word of expression is the distance of swimming of 1 type; (2) type of service 2 coded systems coding, this mode attempts representing that with two code words 000 and 100 this distance of swimming is identical with the length of the last distance of swimming, its distance of swimming type is still provided by highest order, and 0 this code word of expression is the distance of swimming of 0 type, and 1 this code word of expression is the distance of swimming of 1 type.
The circuit implement device is one of vital factor for test data compressing method.Because if adopted test data compressing method, in design for Measurability, must increase a decompression circuit so and recover original test data.This decompression circuit must be controlled in certain scale scope, has autgmentability preferably simultaneously again, so that test generates automatically.
Table 1 is distance of swimming code type 1 coding schedule altogether
Decoding unit:
Decoding unit structured flowchart of the present invention as shown in Figure 1, it is by a finite state machine, a k digit counter, a log
2K digit counter, a k bit register are formed.This decompression circuit is simple in structure, and circuit scale is little, can not introduce hardware cost significantly.
The groundwork principle of decoding unit of the present invention is as follows:
1) at first, it is 1 that finite state machine sends enable signal en, and shift and inc are high level then, reads the value of bit_in simultaneously, this value is carried out suitable control to rest-set flip-flop under the control of finite state machine, making it optionally is the 0 type distance of swimming or the 1 type distance of swimming.
2) read the value of bit_in, if be not 0, log
2The k digit counter begins to add a counting, and it is 0 that this process repeats to bit_in always.
3) next, under the control of finite state machine, output k bit counter value corresponding number several 0 or 1, the k digit counter puts 0.
4) under the control of finite state machine, read log from bit_in
2The k bit counter value the data of corresponding number.
5) reg_cnt1 is changed to high level, and the value of duplicating the k digit counter by dcnt is in the k bit register.
6) again under the control of finite state machine, output k bit counter value corresponding number several 0 or 1, the k digit counter puts 0.Export an inverse value at last.So far, this runs decoding finishes.
7) read the value of bit_in, this value is carried out suitable control to rest-set flip-flop under the control of finite state machine, and making it optionally is the 0 type distance of swimming or the 1 type distance of swimming.Read the value of bit_in,, repeat 1) if be not 0.If 0, read again once, judge that this moment should value, if 0, the value of k bit register is copied to the k digit counter, repeating step 5), otherwise repeating step 1).
Claims (3)
1, a kind of test data compression coding with same run length, coding/decoding method and special decoding unit, it is characterized in that: at first be elementary cell with the bit string, simultaneously 0 and 1 two type the distance of swimming is added up, test data is separated, the length of statistics bit string, utilize two kinds of dissimilar coded system bit strings length to encode again, make coded system both consider that variable length code used short code word to replace long original bit string, consider the correlation between the distance of swimming again, the follow-up distance of swimming for the continuous distance of swimming with same run length can further be represented with short code word, realizes the compression of data; The method that decompresses is to utilize the decoding unit of making at this compression method to decompress.Concrete steps are:
A, employing automatic test pattern Core Generator ATPG generate the complete test set T that determines;
B, described test set is carried out distance of swimming analysis, be about to test data and cut apart by 0 and 1 two type the distance of swimming, don't-care bit wouldn't be filled, and statistics is cut apart the every section possible run length in back;
The correlation between the adjacent distance of swimming is considered earlier in the filling of c, don't-care bit, promptly makes the adjacent continuous run length identical as much as possible, then is to consider to make last run length maximum as far as possible to the filling of remaining don't-care bit;
D, the test data after filling encoded adopt two kinds of coded systems, for the adjacent distance of swimming of equal length and the coded system of follow-up distance of swimming type of service 1, for the coding of other data coded system of type of service 2 then, finally realized the test data compression;
Then, utilize the data importing chip under test of automatic test equipment (ATE) with compression, carry out decompress(ion) by the decompression circuit of chip under test, the transfer of data after will decompressing at last is to the scan chain of circuit-under-test.
2, a kind of LSI circuit test data compressed encoding according to claim 1, coding/decoding method and special decoding unit, it is characterized in that including don't-care bit " X " in the test vectors all among the described complete test set T, and don't-care bit need account for 35%～95% of test vector figure place.
3, realize the described a kind of LSI circuit test data compressed encoding of claim 1, coding/decoding method and special decoding unit, it is characterized in that: this decompression circuit comprises finite state machine (FSM), counter and relevant control circuit; The tranmitting data register of decompression circuit closes into described counter and control circuit; Finite state machine will set counter initial state signal respectively and coding input state signal is given counter and control circuit; Data output signal goes out the scan chain of tested design with the transfer of data that decompresses under state machine control, finish whole decompression process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2009101165956A CN101604974A (en) | 2009-04-21 | 2009-04-21 | A kind of test data compression coding, coding/decoding method and special decoding unit with same run length |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2009101165956A CN101604974A (en) | 2009-04-21 | 2009-04-21 | A kind of test data compression coding, coding/decoding method and special decoding unit with same run length |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101604974A true CN101604974A (en) | 2009-12-16 |
Family
ID=41470547
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2009101165956A Pending CN101604974A (en) | 2009-04-21 | 2009-04-21 | A kind of test data compression coding, coding/decoding method and special decoding unit with same run length |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101604974A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101807926A (en) * | 2010-01-21 | 2010-08-18 | 上海电力学院 | Compressing and encoding method of low energy consumption SOC (System On a Chip) test data |
| WO2012155331A1 (en) * | 2011-05-17 | 2012-11-22 | 上海华岭集成电路技术股份有限公司 | Compression method for test file |
| CN103973311A (en) * | 2014-04-11 | 2014-08-06 | 北京工业大学 | Fast coding and decoding algorithm for elongated binaryzation descriptors |
| CN103746706B (en) * | 2014-01-01 | 2016-08-17 | 安庆师范学院 | Test data compression based on double distance of swimming alternate coded and decompression method |
| CN107144782A (en) * | 2017-04-21 | 2017-09-08 | 吴海峰 | The integrated circuit test data compression method stored based on continued fraction |
| CN108777583A (en) * | 2018-06-12 | 2018-11-09 | 安庆师范大学 | A kind of data compression method and apparatus |
| CN109799449A (en) * | 2018-12-20 | 2019-05-24 | 深圳科安达电子科技股份有限公司 | A kind of track circuit monitoring data decompression method and processing system based on parameter identification |
| CN111384960A (en) * | 2018-12-28 | 2020-07-07 | 上海寒武纪信息科技有限公司 | Decoding method, processor, decoding device and storage medium |
| CN112600566A (en) * | 2020-12-18 | 2021-04-02 | 上海集成电路研发中心有限公司 | Digital circuit for decoding run length |
-
2009
- 2009-04-21 CN CNA2009101165956A patent/CN101604974A/en active Pending
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101807926A (en) * | 2010-01-21 | 2010-08-18 | 上海电力学院 | Compressing and encoding method of low energy consumption SOC (System On a Chip) test data |
| CN101807926B (en) * | 2010-01-21 | 2013-01-23 | 上海电力学院 | Compressing and encoding method of low energy consumption SOC (System On a Chip) test data |
| WO2012155331A1 (en) * | 2011-05-17 | 2012-11-22 | 上海华岭集成电路技术股份有限公司 | Compression method for test file |
| CN103746706B (en) * | 2014-01-01 | 2016-08-17 | 安庆师范学院 | Test data compression based on double distance of swimming alternate coded and decompression method |
| CN103973311A (en) * | 2014-04-11 | 2014-08-06 | 北京工业大学 | Fast coding and decoding algorithm for elongated binaryzation descriptors |
| CN103973311B (en) * | 2014-04-11 | 2017-08-04 | 北京工业大学 | A kind of quick braiding decoding algorithm that son is described to elongated binaryzation |
| CN107144782A (en) * | 2017-04-21 | 2017-09-08 | 吴海峰 | The integrated circuit test data compression method stored based on continued fraction |
| CN107144782B (en) * | 2017-04-21 | 2019-05-14 | 吴海峰 | Integrated circuit test data compression method based on continued fraction storage |
| CN108777583A (en) * | 2018-06-12 | 2018-11-09 | 安庆师范大学 | A kind of data compression method and apparatus |
| CN108777583B (en) * | 2018-06-12 | 2021-08-13 | 安庆师范大学 | Data compression method and device |
| CN109799449A (en) * | 2018-12-20 | 2019-05-24 | 深圳科安达电子科技股份有限公司 | A kind of track circuit monitoring data decompression method and processing system based on parameter identification |
| CN109799449B (en) * | 2018-12-20 | 2021-07-02 | 深圳科安达电子科技股份有限公司 | Parameter identification-based track circuit monitoring data decompression method and processing system |
| CN111384960A (en) * | 2018-12-28 | 2020-07-07 | 上海寒武纪信息科技有限公司 | Decoding method, processor, decoding device and storage medium |
| CN111384960B (en) * | 2018-12-28 | 2022-05-10 | 上海寒武纪信息科技有限公司 | Decoding method, processor, decoding device and storage medium |
| CN112600566A (en) * | 2020-12-18 | 2021-04-02 | 上海集成电路研发中心有限公司 | Digital circuit for decoding run length |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101604974A (en) | A kind of test data compression coding, coding/decoding method and special decoding unit with same run length | |
| Li et al. | Test data compression using dictionaries with fixed-length indices [soc testing] | |
| Li et al. | Test set embedding for deterministic BIST using a reconfigurable interconnection network | |
| CN100516911C (en) | System chip test data compression method of block mark | |
| Chandra et al. | Frequency-directed run-length (FDR) codes with application to system-on-a-chip test data compression | |
| US7552373B2 (en) | Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit | |
| CN100445760C (en) | Multi-scanning chain LSI circuit test data compressing method | |
| CN101968528B (en) | Test data compression method of integrated circuit test | |
| Chandra et al. | Test data compression and decompression based on internal scan chains and Golomb coding | |
| Kavousianos et al. | Multilevel Huffman coding: An efficient test-data compression method for IP cores | |
| CN101807926B (en) | Compressing and encoding method of low energy consumption SOC (System On a Chip) test data | |
| JP2003526778A (en) | Continuous application and decompression of test patterns to circuit technology under test | |
| CN101158706A (en) | Large scale integrated circuit test data and method for testing power consumption cooperate optimization | |
| CN102522120B (en) | Dictionary coding compression method | |
| CN101493499B (en) | Exponent cut LFSR replanting VLSI test data compression method | |
| CN104753541A (en) | Compression method for test data of irrational number storage test vector | |
| Chandra et al. | Test resource partitioning for SOCs | |
| CN101762782B (en) | Method for compressing built-off self-test data of system-on-a-chip and special decoding unit thereof | |
| CN102323540A (en) | Test method for SOC (System On Chip) based on coding | |
| Vranken et al. | ATPG padding and ATE vector repeat per port for reducing test data volume | |
| CN101937056B (en) | Compression generation method for testing data of digital integrated circuit | |
| Tenentes et al. | High-quality statistical test compression with narrow ATE interface | |
| CN107026651A (en) | The data compression method of two by stages and the test data storage method of integrated circuit | |
| Kim et al. | Test-decompression mechanism using a variable-length multiple-polynomial LFSR | |
| CN116415533A (en) | Testability design method of on-chip processor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20091216 |