CN101604201B - Multi-processor system and dynamic power saving method thereof - Google Patents
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- CN101604201B CN101604201B CN2009101613223A CN200910161322A CN101604201B CN 101604201 B CN101604201 B CN 101604201B CN 2009101613223 A CN2009101613223 A CN 2009101613223A CN 200910161322 A CN200910161322 A CN 200910161322A CN 101604201 B CN101604201 B CN 101604201B
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Abstract
The invention provides a multi-processor system and a dynamic power saving method thereof. The multi-processor system comprises a plurality of processors and a chip set, wherein each processor comprises a plurality of standard bus request pins and a specific bus request pin, and the standard bus request pins of each processor are interactively connected with the standard bus request pins of other processors respectively; and the chip set is coupled to the specific bus request pin of each processor to sense control request signals on the specific bus request pins. When a control request signal is sensed, an input buffer to be connected with the processor is started, so that the processor can access data through the input buffer; and on the contrary, when the control request signal is not sensed, the input buffer is shut down. The multi-processor system and the dynamic power saving method thereof can start or shut down the input buffer according to whether the processor has the control request signal for a bus or not, to further achieve the power saving effect.
Description
Technical field
The present invention is relevant for a kind of processor system and electricity saving method thereof, and is particularly to a kind of multicomputer system and dynamic electricity-saving method thereof.
Background technology
Multicomputer system can be made up of a GENERAL TYPE processor and one or many processor with special arithmetic capability.This multicomputer system adopts the notion of resource sharing, so as to reducing the hardware configuration cost, wherein the most general resources shared is a storer, can deposit any data in this storer, comprise in order to the signal of communication state between the instruction processorunit and the data of carrying out computing by a plurality of processors simultaneously.
Along with the universalness of multicomputer system, also all adopt this framework such as desktop PC, mobile computer or embedded equipments such as mobile phone, personal digital assistant on the market.By integrating the computation performance of different processor, not only can reach better usefulness, also come efficiently than the method for the single high speed processor of general use.
Since the different characteristic of processor hardware framework, the difference in the practical operation of bottom arithmetic element, and the identical time that is operated on the heterogeneous processor is all different with the power consumption performance.Therefore, the technology of development focuses on mostly and weighs execution time and the power consumption of different processors for job at present, and then adjusts the work scheduling in the operating system, so as to reaching power saving and the purpose that improves usefulness.Yet, how can effectively integrate the different characteristic of processor hardware framework, and then reach the power saving effect of entire system, still be those skilled in the art's a big problem.
Summary of the invention
The invention provides a kind of multicomputer system, utilize the control request signal of the bus request pin position receiving processor of additional configuration, and start adaptively or close input buffer in the chipset for bus.
The invention provides a kind of dynamic electricity-saving method of multicomputer system, when processor enters active state (Active Status), dynamically start or close input buffer in the chipset to save electric power.
The present invention proposes a kind of multicomputer system, and it comprises a plurality of processors and a chipset.Wherein, each processor includes a plurality of STD bus requests (BusRequest) pin position and a specific bus request pin position, and the STD bus request pin position of each processor is connected alternately with the STD bus request pin position of other processors respectively.Chipset is coupled to the specific bus request pin position of each processor, and detects the control request signal on these specific bus request pin positions.Wherein, when chipset detected the control request signal, the input buffer that soon is connected with processor started, and passed through this input buffer access data for processor; Otherwise, when chipset does not detect the control request signal, then input buffer cuts out.
The present invention proposes a kind of dynamic electricity-saving method of multicomputer system, is applicable to the multicomputer system that comprises a plurality of processors and a chipset, and wherein each processor all is coupled to chipset by a specific bus request pin position.The method is to detect control request signal on the described specific bus request pin position by chipset.When chipset detected the control request signal, the input buffer that soon is connected with processor started, and passed through this input buffer access data for processor; Otherwise, when chipset does not detect the control request signal, then input buffer cuts out.
The present invention proposes a kind of multicomputer system, and it comprises a plurality of processors and a chipset.Wherein, each processor comprises a plurality of bus request pin position, and is connected alternately with the bus request pin position of other processors respectively.Chipset is coupled to the bus request pin position of each processor respectively, and detects the control request signal on these bus request pin positions.When chipset detects the control request signal, start with the input buffer that soon is connected with processor, pass through this input buffer access data for processor; When chipset does not detect the control request signal, then input buffer cuts out.
The present invention proposes a kind of dynamic electricity-saving method of multicomputer system, be applicable to the multicomputer system that comprises a plurality of processors and a chipset, described chipset is coupled to a plurality of bus request pin position of each processor respectively, and the bus request pin position of each processor then is connected alternately with the bus request pin position of other processors.The method is to detect control request signal on these bus request pin positions by chipset, and when detecting the control request signal, the input buffer that soon is connected with these processors starts, for processor by the input buffer access data; When not detecting the control request signal, then input buffer cuts out.
Multicomputer system of the present invention and dynamic electricity-saving method thereof can be opened input buffer or close, and then reach less electricity consumption according to this according to whether the control request signal of processor for bus being arranged.
Description of drawings
Fig. 1 is the circuit block diagram of the multicomputer system that illustrates according to one embodiment of the invention.
Fig. 2 is the process flow diagram of the dynamic electricity-saving method of the multicomputer system that illustrates according to one embodiment of the invention.
Fig. 3 is the circuit block diagram of the multicomputer system that illustrates according to one embodiment of the invention.
Fig. 4 is the process flow diagram of the dynamic electricity-saving method of the multicomputer system that illustrates according to one embodiment of the invention.
Embodiment
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphic being described in detail below.
The present invention is coupled to chipset respectively with the bus request pin position of each processor in the multicomputer system, or use extra bus request pin position to be coupled to chipset, and can enter active state (Active Status) at the processor of multicomputer system the time, allow chipset grasp the control request state of each processor for bus in the very first time.Here " active state " of indication is with respect to the defined holding state of ACPI specification (ACPI) (Sleep State) power management, for example: standby states such as C1, C2, C3 or Cn; That is active state can be meant the duty (Execution State) of C0.
When having the processor request to use bus transfer data, the input buffer (Input buffer) that chipset soon will be connected with processor starts, and transmits data for processor by input buffer.Yet when active state, if in a period of time interval, and non-processor request use bus transfer data, the input buffer on the chipset can cut out, open the required electric power of input buffer so as to saving.In order to make content of the present invention more clear, below the example that can implement according to this really as the present invention especially exemplified by embodiment.
Fig. 1 is the circuit block diagram of the multicomputer system that illustrates according to one embodiment of the invention.Please refer to Fig. 1, the multicomputer system 100 of present embodiment comprises processor 102,104,106,108 and chipset 110.Above-mentioned processor 102,104,106,108 includes four bus request pin position BR0#, BR1#, BR2#, BR3#, and can connect its bus request pin position alternately by bus request line BREQ0#, BREQ1#, BREQ2#, BREQ3# between these processors.For example, the pin position BR0# of processor 102 is connected with pin position BR3#, the pin position BR2# of processor 106, the pin position BR1# of processor 108 of processor 104; The pin position BR1# of processor 102 then is connected with pin position BR0#, the pin position BR3# of processor 106, the pin position BR2# of processor 108 of processor 104, by that analogy.
It should be noted that, general processor all is to utilize pin position BR0# to give notice signal to other processors when the use of needs bus transfer data is arranged, and has asked to use bus to inform it, also utilize pin position BR0# to send the control request signal, so as to obtaining the ownership of bus to chipset.In view of the above, the present invention all is connected to chipset 110 with the bus request pin position BR0# of each processor, make the chipset 110 and the pin position BR0# of processor 102,104,106,108 keep linking, and can grasp the control request state of each processor at any time for bus.
In detail, Fig. 2 is the process flow diagram of the dynamic electricity-saving method of the multicomputer system that illustrates according to one embodiment of the invention.Please be simultaneously with reference to Fig. 1 and Fig. 2, present embodiment is after the processor 102,104,106,108 of multicomputer system 100 enters active state, if in a period of time interval, and non-processor 102,104,106,108 request is when using bus transfer datas, then earlier the input buffer that is connected with processor in the chipset 110 cuts out, so as to saving the electric power that input buffer consumed.
At the same time, chipset 110 can be detected the bus request pin position (step S202) of each processor by above-mentioned bus request line BREQ0#, BREQ1#, BREQ2#, BREQ3#, and has judged whether to detect control request signal (step S204).
When chipset 110 detects the control request signal, i.e. representative has the processor request to use bus with the transmission data, the input buffer that chipset 110 meetings will wherein be connected with processor this moment starts (step S206), passes through the input buffer access data for this processor.In addition, after step S206, also comprise: when having processor to use bus transfer data to finish, if in a period of time interval, and bus transfer data is used in non-processor 102,104,106,108 requests, present embodiment also can be closed the input buffer that originally started so as to saving electric power, and the bus request pin position of continuing each processor of detecting by step S202.
When chipset 110 does not detect the control request signal, processor will continue to be in to be stagnated or waiting status, therefore the present invention can continue the input buffer in the chipset is maintained closed condition (step S208), to save the electric power that these input buffers are consumed.Wherein, above-mentioned startup and the step of closing input buffer for example are to reach by the mode of opening or closing the power supply that offers input buffer, and present embodiment does not limit its scope.After step S208, also comprise the bus request pin position (step S202) of continuing each processor of detecting.
Framework and dynamic electricity-saving method by above-mentioned multicomputer system, the present invention can be under the situation of multicomputer system normal operation (for example: processor is in the C0 state), according to the control request state whether processor is arranged, in time the input buffer that temporarily need not use on the chipset cuts out, and reach the effect of dynamic saving electric power.
Except above-mentioned all bus request pin positions of processor all are connected to the mode of chipset, another embodiment of the present invention then is a specific bus request pin of additional configuration position outside these pin positions, in order to being connected to chipset, and can allow chipset directly learn the control request state of each processor for bus by this specific bus request pin position.Describe in detail for an embodiment again with next.
Fig. 3 is the circuit block diagram of the multicomputer system that illustrates according to one embodiment of the invention.Please refer to Fig. 3, the multicomputer system 300 of present embodiment comprises processor 302,304,306,308 and chipset 310.Wherein, each processor includes bus request pin position BR0#, BR1#, BR2#, the BR3# of four standards, and can connect its bus request pin position alternately by bus request line BREQ0#, BREQ 1#, BREQ2#, BREQ3# between these processors.The configuration of these pin positions is all identical with previous embodiment, so do not repeat them here.
Difference that it should be noted that a present embodiment and a last embodiment is that present embodiment is specific bus request pin position BRS# of additional configuration on each processor, but not the bus request pin position BR0# of each processor all is connected to chipset.In addition, in the present embodiment, by one independently specific bus request pin bit line BRQS# the specific bus request pin position BRS# of these processors is linked up and is coupled to chipset 310, couple and also need have extra pin position to carry out correspondence at chipset 310.Here " the specific bus request pin position BRS# " of indication and " specific bus request pin bit line BRQS# " is for the framework of general multiprocessor, that is the additional configuration that present embodiment carried out under standard architecture.
As for bus request pin position BR0#, BR1#, BR2#, BR3# originally, then only with the pin position BR0# of processor 302, and the pin position BR3# of coupled processor 304, the pin position BR2# of processor 306, the pin position BR1# of processor 308 are coupled to chipset 310.Wherein, when bus was used in the needs request, processor promptly can send the control request signal by specific bus request pin position BRS#.And before sending the control request signal, processor then also comprises gives notice signal to other processors by STD bus request pin position BR0# earlier, has asked to use bus to inform it.
What deserves to be mentioned is, if the specific bus request pin position BRS# and the specific bus request pin bit line BRQS# of no present embodiment, and each processor is when all the bus request pin position BR0# by separately sends the control request signal, owing to only have the pin position BR0# of processor 302 can be coupled to chipset 310, so chipset can't detect the control request signal that the pin position BR0# by processor 304,306,308 is sent, and so can't enter power down mode by technology of the present invention.Therefore, in the present embodiment, the configuration by specific bus request pin position BRS# and specific bus request pin bit line BRQS# has solved above-mentioned problem, and and then reaches the effect of dynamic electricity-saving.
In above-mentioned multicomputer system framework, chipset equally can be by the control request signal on the detection bus request pin position, whether have processor for bus ask, and start according to this or close wherein corresponding input buffer if learning, so as to reaching less electricity consumption.
In detail, Fig. 4 is the process flow diagram of the dynamic electricity-saving method of the multicomputer system that illustrates according to one embodiment of the invention.Please be simultaneously with reference to Fig. 3 and Fig. 4, present embodiment is after the processor 302,304,306,308 of processor system 300 enters active state, if in a period of time interval, and non-processor 302,304,306,308 request is when using bus transfer datas, then earlier the input buffer that is connected with processor in the chipset 310 cuts out, so as to saving the electric power that input buffer consumed.
At the same time, chipset 310 can be detected the specific bus request pin position BRS# (step S402) of each processor by above-mentioned specific bus request line BREQS#, and has judged whether to detect control request signal (step S404).Wherein, each processor also comprised and gives notice signal to other processors by STD bus request pin position BR0# earlier before sending the control request signal by specific bus request pin position BRS#, asked to use bus to inform it.
When chipset 310 detects the control request signal, i.e. representative has the processor request to use bus with the transmission data, the input buffer that chipset 310 meetings will wherein be connected with processor this moment starts (step S406), passes through the input buffer access data for this processor.In addition, after step S406, also comprise: when having processor to use bus transfer data to finish, if in a period of time interval, and bus transfer data is used in non-processor 302,304,306,308 requests, present embodiment also can be closed the input buffer that originally started so as to saving electric power, and the bus request pin position of continuing each processor of detecting by step S402.
Otherwise when chipset 310 did not detect the control request signal, then representative did not have the processor request to use bus with the transmission data, and the input buffer that 310 continuation of chipset this moment will wherein be connected with processor maintains closed condition (step S406).After step S408, also comprise the specific bus request pin position (step S402) of continuing each processor of detecting.
What deserves to be mentioned is that in one embodiment, chipset for example is after detecting one section specified time interval of control request signal, just can start input buffer.Also therefore, in order to make the startup of input buffer get caught up in the access action of processor, the time point that present embodiment can also send processor the control request signal shifts to an earlier date, meaning is that processor is before sending the control request signal by STD bus request pin position, promptly earlier send the control request signal by specific bus request pin position, and allow chipset start input buffer ahead of time, to deal with processor thing followed access action.
In sum, multicomputer system of the present invention and dynamic electricity-saving method thereof are coupled to chipset respectively by all the bus request pin positions with each processor in the multicomputer system, or in each processor additional configuration specific bus request pin position and in order to the coupling chip group, and make when the processor in the multicomputer system enters active state, if in a period of time interval, and bus transfer data is used in the non-processor request, chipset can temporarily be closed untapped input buffer, and can reach the effect of dynamic electricity-saving.
The above only is preferred embodiment of the present invention; so it is not in order to limit scope of the present invention; any personnel that are familiar with this technology; without departing from the spirit and scope of the present invention; can do further improvement and variation on this basis, so the scope that claims were defined that protection scope of the present invention is worked as with the application is as the criterion.
Being simply described as follows of symbol in the accompanying drawing:
100,300: multicomputer system
102,104,106,108,302,304,306,308: processor
110,310: chipset
BR0#, BR 1#, BR2#, BR3#: bus request pin position
BRS#: specific bus request pin position
BREQ0#, BREQ1#, BREQ2#, BREQ3#: specific bus request line
BREQS#: bus request line
S202～S208: each step of the dynamic electricity-saving method of multicomputer system of the present invention
S402～S408: each step of the dynamic electricity-saving method of multicomputer system of the present invention.
Claims (9)
1. a multicomputer system is characterized in that, comprising:
A plurality of processors, each described processor comprise an a plurality of STD bus requests pin position and a specific bus request pin position, and wherein the described STD bus request pin position of each described processor is connected alternately with the STD bus request pin position of other processors respectively; And
One chipset is coupled to this specific bus request pin position of each described processor, and detects the control request signal on the described specific bus request pin position, wherein:
When this chipset detects this control request signal, start an input buffer that is connected with described processor, pass through this input buffer access data for described processor; And
When this chipset does not detect this control request signal, close this input buffer.
2. multicomputer system according to claim 1, it is characterized in that, when this chipset enters an active state at described processor, begin to detect this control request signal on this specific bus request pin position of each described processor, start according to this or close this input buffer that is connected with described processor;
Wherein, this active state is the defined C0 state of ACPI specification.
3. the dynamic electricity-saving method of a multicomputer system, it is characterized in that, be applicable to a multicomputer system that comprises a plurality of processors and a chipset, wherein each described processor is coupled to this chipset by a specific bus request pin position, and this dynamic electricity-saving method comprises the following steps:
This chipset is detected the control request signal on the described specific bus request pin position;
When this chipset detects this control request signal, start an input buffer that is connected with described processor, pass through this input buffer access data for described processor; And
When this chipset does not detect this control request signal, close this input buffer.
4. the dynamic electricity-saving method of multicomputer system according to claim 3 is characterized in that, the step that starts this input buffer that is connected with described processor also comprises:
After detecting a specified time interval of this control request signal, just start this input buffer.
5. the dynamic electricity-saving method of multicomputer system according to claim 3 is characterized in that, this dynamic electricity-saving method is suitable for the defined C0 state of ACPI specification.
6. a multicomputer system is characterized in that, comprising:
A plurality of processors, each described processor comprise a plurality of bus request pin position, and described bus request pin position is connected alternately with the bus request pin position of other processors respectively; And
One chipset is coupled to the described bus request pin position of each described processor respectively, and detects the control request signal on the described bus request pin position, wherein:
When this chipset detects this control request signal, start an input buffer that is connected with described processor, pass through this input buffer access data for described processor; And
When this chipset does not detect this control request signal, close this input buffer.
7. multicomputer system according to claim 6, it is characterized in that, when this chipset enters an active state at described processor, begin to detect this control request signal that described bus request pin position is sent, start according to this or close this input buffer that is connected with each described processor;
Wherein, this active state is the defined C0 state of ACPI specification.
8. the dynamic electricity-saving method of a multicomputer system, it is characterized in that, be applicable to a multicomputer system that comprises a plurality of processors and a chipset, wherein this chipset is coupled to a plurality of bus request pin position of each described processor respectively, and the bus request pin position of each described processor is connected alternately with the bus request pin position of other processors, and this dynamic electricity-saving method comprises the following steps:
This chipset is detected the control request signal on the described bus request pin position;
When detecting this control request signal, start an input buffer that is connected with described processor, pass through this input buffer access data for described processor; And
When not detecting this control request signal, close this input buffer.
9. the dynamic electricity-saving method of multicomputer system according to claim 8 is characterized in that, this dynamic electricity-saving method is suitable for the defined C0 state of ACPI specification.
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| CN1794140A (en) * | 2006-01-09 | 2006-06-28 | 威盛电子股份有限公司 | Power-saving method of central processor |
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