CN101599505A - Distribution mode of power transistor with high density and efficiency - Google Patents
Distribution mode of power transistor with high density and efficiency Download PDFInfo
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- CN101599505A CN101599505A CNA2008101000338A CN200810100033A CN101599505A CN 101599505 A CN101599505 A CN 101599505A CN A2008101000338 A CNA2008101000338 A CN A2008101000338A CN 200810100033 A CN200810100033 A CN 200810100033A CN 101599505 A CN101599505 A CN 101599505A
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Abstract
Power transistor has grid, source electrode, reaches drain electrode.Grid has first straight line portion, second straight line portion, reaches the 3rd straight line portion.First straight line portion and second straight line portion are connected and form first v-shaped structure.Second straight line portion and the 3rd straight line portion are connected and form second v-shaped structure.First straight line portion, second straight line portion, and the 3rd straight line portion form N shape structure.
Description
Technical field
The present invention relates to a kind of distribution mode of power transistor (power transistor layout), relate in particular to a kind of distribution mode of power transistor with high density and efficiency.
Background technology
Fig. 1 shows the layout type of known power transistor 10.Power transistor 10 can be applicable to power converter (power converter) with the purposes as power management.In example shown in Figure 1, power transistor 10 is implemented by the PMOS transistor.Power transistor 10 comprises grid 11, source electrode 12, reaches drain electrode 13.Source electrode 12 has a plurality of trap contact (well pickup contact) 15a and a plurality of source electrode contact (source contact) 15b, and wherein a plurality of trap contact 15a are positioned at N type diffusion region 14 and a plurality of source electrode contact 15b is positioned at p type diffusion region 16.Drain electrode 13 has a plurality of drain electrode contact (draincontact) 15c, and wherein a plurality of drain electrode contact 15c are positioned at p type diffusion region 16.The layout type that Fig. 1 shows is called honeycombed (hive-shaped) structure, wherein increases effective channel width (channel width) of power transistor 10 by the bending (this example is 45 degree) of grid 11.
As shown in Figure 1, the source electrode 12 of the formed equivalent transistor of bending part 11a of grid 11 and drain 13 just in time has source electrode contact 15b and drain electrode contact 15c to be positioned at corresponding both sides, so it possesses low source electrode to drain resistance (Rds on), thereby usefulness is preferable.Yet, the formed equivalent transistor of horizontal component 11b of grid 11 has a side (source electrode 12 or drain 13) could connect source electrode contact 15b or drain electrode contact 15c through one section P shape diffusion region 16, so it possesses high source to drain resistance, thereby usefulness is relatively poor.
Summary of the invention
The object of the present invention is to provide a kind of high-effect and have highdensity power transistor concurrently.
According to purpose of the present invention, provide a kind of power transistor.This power transistor has grid, source electrode, reaches drain electrode.Grid has first straight line portion, second straight line portion, reaches the 3rd straight line portion.First straight line portion and second straight line portion are connected and form first angle.First straight line portion and second straight line portion form first v-shaped structure.Second straight line portion and the 3rd straight line portion are connected and form second angle.Second straight line portion and the 3rd straight line portion form second v-shaped structure.First straight line portion, second straight line portion, and the 3rd straight line portion form N shape structure.
Description of drawings
Fig. 1 shows the layout type of known power transistor;
Fig. 2 shows the layout type according to the power transistor of the first embodiment of the present invention;
Fig. 3 shows the layout type according to the power transistor of the second embodiment of the present invention.
Embodiment
Explanation hereinafter and accompanying drawing will make aforementioned and other purpose of the present invention, feature, more obvious with advantage.Describe in detail according to preferred embodiment of the present invention hereinafter with reference to accompanying drawing.
Fig. 2 shows the layout type according to the power transistor 20 of the first embodiment of the present invention.Power transistor 20 can be applicable to power converter with the purposes as power management.In example shown in Figure 2, power transistor 20 is implemented by the PMOS transistor.Power transistor 20 comprises grid 21, source electrode 22, reaches drain electrode 23.Source electrode 22 has a plurality of trap contact 25a and a plurality of source electrode contact 25b, and wherein a plurality of trap contact 25a are positioned at N type diffusion region 24 and a plurality of source electrode contact 25b is positioned at p type diffusion region 26.Drain electrode 23 has a plurality of drain electrode contact 25c, and wherein a plurality of drain electrode contact 25c are positioned at p type diffusion region 26.
As shown in Figure 2, grid 21 all adopts bending part, so its formed equivalent transistor source electrode 22 and drain and 23 source electrode contact 25b and the drain electrode contact 25c both sides in correspondence are arranged all just in time, therefore whole source electrode to drain resistance can be low than known layout method (as Fig. 1), and reaches dynamical purpose.In addition, because grid 21 all adopts bending part,, and reach highdensity purpose simultaneously so its formed effective channel width in unit are can be big than known layout method (as Fig. 1) also.
In order to further specify the technical characterictic of present embodiment, Fig. 2 shows that grid 21 comprises the first straight line portion 21a, the second straight line portion 21b, reaches the 3rd straight line portion 21c.Present embodiment selects the length of the first straight line portion 21a to equal the length of the second straight line portion 21b, and the length of the second straight line portion 21b equals the length of the 3rd straight line portion 21c.The first straight line portion 21a and the second straight line portion 21b are connected and form the first angle θ 1, and wherein the first straight line portion 21a and the second straight line portion 21b form first V-arrangement (v-shaped) structure.The second straight line portion 21b and the 3rd straight line portion 21c are connected and form the second angle θ 2, and wherein the second straight line portion 21b and the 3rd straight line portion 21c form one second v-shaped structure.The first straight line portion 21a, the second straight line portion 21b, and the 3rd straight line portion 21c form N shape (n-shaped) structure.Present embodiment selects θ 1 to equal θ 2, but the invention is not restricted to this.In addition, present embodiment selects θ 1 to equal 90 degree to reach optimization.
By the calculating of layout software, the formed unit are channel width of Fig. 2 is about 1.25 times of the formed unit are channel width of Fig. 1.In other words, when reaching identical channel width, the layout type of Fig. 2 can reduce the area (1-1/1.25=20%) of about 20% power transistor.
Fig. 3 shows the layout type according to the power transistor 30 of the second embodiment of the present invention.As shown in Figure 3, except the number that increases drain electrode contact 35c, can further reduce source electrode by the distance that shortens between drain electrode contact 35c and the grid 31, and reach best efficiency to drain resistance.
In addition, though the present invention can be applicable to power converter with the purposes as power management, the present invention also can be applicable to other circuit that needs the power transistor of big live width, just repeats no more in this.
Though the present invention was illustrated as illustration by preferred embodiment already, it should be understood that to the invention is not restricted to the embodiment that this is disclosed.On the contrary, this invention is intended to contain is tangible various modification and similar configuration to those skilled in the art.Therefore, the scope of claim should be according to the widest annotation, and this type of is revised and similar configuration to contain all.
Claims (10)
1, a kind of power transistor comprises:
Grid, it has first straight line portion, second straight line portion, reaches the 3rd straight line portion, wherein this first straight line portion and this second straight line portion are connected and form first angle, and this second straight line portion and the 3rd straight line portion are connected and form second angle;
Source electrode; And
Drain electrode,
Wherein this first straight line portion and this second straight line portion form first v-shaped structure, and this second straight line portion and the 3rd straight line portion form second v-shaped structure, and this first straight line portion, this second straight line portion, and the 3rd straight line portion form N shape structure.
2, power transistor as claimed in claim 1, wherein the length of this first straight line portion equals the length of this second straight line portion.
3, power transistor as claimed in claim 2, wherein the length of this second straight line portion equals the length of the 3rd straight line portion.
4, power transistor as claimed in claim 3, wherein this first angle equals this second angle.
5, power transistor as claimed in claim 4, wherein this first angle equals 90 degree.
6, power transistor as claimed in claim 5, wherein this source electrode has a plurality of trap contacts and the contact of a plurality of source electrode.
7, power transistor as claimed in claim 6, wherein this a plurality of traps contact is positioned at N type diffusion region and should a plurality of source electrodes contacts and is positioned at p type diffusion region.
8, power transistor as claimed in claim 7, wherein this drain electrode has a plurality of drain electrode contacts.
9, power transistor as claimed in claim 8, wherein these a plurality of drain electrode contacts are positioned at this p type diffusion region.
10, power transistor as claimed in claim 9, wherein this power transistor is applied to power converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008101000338A CN101599505A (en) | 2008-06-03 | 2008-06-03 | Distribution mode of power transistor with high density and efficiency |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008101000338A CN101599505A (en) | 2008-06-03 | 2008-06-03 | Distribution mode of power transistor with high density and efficiency |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101599505A true CN101599505A (en) | 2009-12-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2008101000338A Pending CN101599505A (en) | 2008-06-03 | 2008-06-03 | Distribution mode of power transistor with high density and efficiency |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102110691A (en) * | 2010-12-03 | 2011-06-29 | 杭州矽力杰半导体技术有限公司 | Power field effect transistor and layout method thereof |
| CN102142439A (en) * | 2010-12-30 | 2011-08-03 | 苏州华芯微电子股份有限公司 | Layout structure of driving chip |
| CN111785683A (en) * | 2020-07-17 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | Semiconductor device forming method and layout structure |
-
2008
- 2008-06-03 CN CNA2008101000338A patent/CN101599505A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102110691A (en) * | 2010-12-03 | 2011-06-29 | 杭州矽力杰半导体技术有限公司 | Power field effect transistor and layout method thereof |
| CN102142439A (en) * | 2010-12-30 | 2011-08-03 | 苏州华芯微电子股份有限公司 | Layout structure of driving chip |
| CN111785683A (en) * | 2020-07-17 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | Semiconductor device forming method and layout structure |
| CN111785683B (en) * | 2020-07-17 | 2024-05-03 | 上海华虹宏力半导体制造有限公司 | Semiconductor device forming method and layout structure |
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| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Open date: 20091209 |