CN101593747B - A semiconductor device assembly and a method of establishing electric connection in the semiconductor device assembly - Google Patents
A semiconductor device assembly and a method of establishing electric connection in the semiconductor device assembly Download PDFInfo
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- CN101593747B CN101593747B CN2009102036219A CN200910203621A CN101593747B CN 101593747 B CN101593747 B CN 101593747B CN 2009102036219 A CN2009102036219 A CN 2009102036219A CN 200910203621 A CN200910203621 A CN 200910203621A CN 101593747 B CN101593747 B CN 101593747B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
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Abstract
The invention provides a semiconductor device assembly and a method of establishing electric connection in the semiconductor device assembly, wherein the semiconductor assembly comprises the following components: a first semi-conductor crystal particle, which includes at least one welding pad; a second semi-conductor crystal particle, which includes a welding pad module, wherein the welding pad module comprises a plurality of welding pads arranged in the manner of array; at least one semi-conductor sealing assembly or another semi-conductor crystal particle; a first conductive component and a second conductive assembly, wherein the first semi-conductor crystal particle is coupled between the semi-conductor sealing assembly or the other semi-conductor crystal particle through the first conductive component and the second conductive component. In the invention, a semi-conductor crystal particle can communicate through the welding pad of the other semi-conductor crystal particle or the semi-conductor sealing assembly or the other semi-conductor crystal particle by adding the welding module on the semi-conductor crystal particle, which reduces wire laying difficulty of the semi-conductor crystal particle and improves design efficiency of the semi-conductor crystal particle.
Description
Technical field
The invention relates to a kind of semiconductor device combination and in the semiconductor device combination, set up the method that is electrically connected, more specifically, be to set up the method that is electrically connected in the semiconductor device combination about a kind of semiconductor device combination and a kind of being used for that comprises semiconductor grain.
Background technology
When semiconductor grain was packed, wiring was used for connecting the weld pad and the package assembling (for example lead-in wire of lead frame) of semiconductor grain, made can communicate by letter between weld pad and the semiconductor package.In addition, weld pad is connected with wiring between the semiconductor package, and for example the distance between the length of each bar wiring and two adjacent wiring all needs to satisfy wiring rule (routing rule).
Make up about semiconductor device, multi-chip module (Multi-Chip Module for example, MCM), the function of its two or more semiconductor grains is incorporated in the encapsulation,, because many semiconductor grains are positioned at an encapsulation, in order to satisfy wiring rule, the design meeting of semiconductor grain is very complicated.
Summary of the invention
In order to solve the wiring complicated technology problem of a plurality of semiconductor grains in the semiconductor device, the invention provides a kind of semiconductor device combination and a kind of method that is used in semiconductor device combination foundation electrical connection, can reduce the wiring complexity of semiconductor device combination with a plurality of semiconductor grains.
The invention provides a kind of semiconductor device combination, comprise: first semiconductor grain, it comprises at least one weld pad; Second semiconductor grain, it comprises the weld pad module, comprises a plurality of weld pads of arranging with array way in the wherein above-mentioned weld pad module; At least one semiconductor package or another semiconductor grain; First conductive component is coupled between the weld pad of the weld pad module of second semiconductor grain and first semiconductor grain; And second conductive component, be coupled to weld pad module and semiconductor package or second half conductor intergranule of second semiconductor grain; Wherein first semiconductor grain is coupled to semiconductor package or second half conductor intergranule via weld pad, weld pad module and first conductive component and second conductive component.
The present invention provides a kind of being used for to set up the method that is electrically connected in the semiconductor device combination in addition, and comprise: first semiconductor grain is provided, and it comprises at least one weld pad; Second semiconductor grain is provided, and it comprises the weld pad module, comprises a plurality of weld pads of arranging with array way in the wherein above-mentioned weld pad module; At least one semiconductor package or another semiconductor grain are provided; Between the weld pad of the weld pad module of second semiconductor grain and first semiconductor grain, place first conductive component; And place second conductive component in the weld pad module of second semiconductor grain and second semiconductor package or second half conductor intergranule; Wherein first semiconductor grain is coupled to semiconductor package or another semiconductor grain via weld pad, weld pad module, first conductive component and second conductive component.
The present invention utilizes increases the weld pad module on semiconductor grain, a semiconductor grain can be communicated by letter via the weld pad of another semiconductor grain and semiconductor package or other semiconductor grain, reduce the wiring difficulty of semiconductor grain, promoted the design efficiency of semiconductor grain.
Description of drawings
Figure 1A is the schematic diagram according to the semiconductor device combination of first embodiment of the invention.
Figure 1B is the schematic diagram according to the semiconductor device combination of second embodiment of the invention.
Fig. 2 is the schematic diagram according to the semiconductor device combination of third embodiment of the invention.
Fig. 3 is the schematic diagram according to the semiconductor device combination of four embodiment of the invention.
Fig. 4 is the schematic diagram according to the semiconductor device combination of fifth embodiment of the invention.
Fig. 5 is the schematic diagram according to the semiconductor device combination of sixth embodiment of the invention.
Fig. 6 is the schematic diagram according to the semiconductor device combination of seventh embodiment of the invention.
Fig. 7 is the schematic diagram according to the semiconductor device combination of eighth embodiment of the invention.
Fig. 8 is the schematic diagram according to the semiconductor device combination of ninth embodiment of the invention.
Fig. 9 is the schematic diagram according to the semiconductor device combination of tenth embodiment of the invention.
Figure 10 is the schematic diagram according to the semiconductor device combination of eleventh embodiment of the invention.
Figure 11 is the schematic diagram according to the semiconductor device combination of twelveth embodiment of the invention.
Figure 12 is the schematic diagram according to the semiconductor device combination of thirteenth embodiment of the invention.
Figure 13 is the schematic diagram according to the semiconductor device combination of fourteenth embodiment of the invention.
Embodiment
In the middle of specification and claims, used some vocabulary to call specific element.Those skilled in the art should understand, and hardware manufacturer may be called same element with different nouns.This specification and claims book is not used as distinguishing the mode of element with the difference of title, but the criterion that is used as distinguishing with the difference of element on function.Be open term mentioned " comprising " in the middle of specification and claims in the whole text, so should be construed to " comprise but be not limited to ".In addition, " coupling " speech is to comprise any indirect means that are electrically connected that directly reach at this.Therefore, be coupled to second device, then represent first device can directly be electrically connected in second device, or be connected electrically to second device indirectly by other device or connection means if describe first device in the literary composition.
Please refer to Figure 1A.Figure 1A is the schematic diagram according to the semiconductor device combination of first embodiment of the invention.Semiconductor device combination 100 comprises two semiconductor grains 110 and 120, a plurality of first conductive components 130, a plurality of second conductive components 140, and a plurality of semiconductor package 150.Semiconductor grain 110 comprises a plurality of weld pads (bonding pad) 112.Semiconductor grain 120 comprises the weld pad module, and the weld pad module comprises a plurality of first weld pads 121 and a plurality of second weld pad 122, and wherein first weld pad 121 and second weld pad 122 couple by conductor wire (conductive trace) 124 respectively.In addition, according to different application, first weld pad 121 and second weld pad 122 can couple or not be coupled to the crystal grain nuclear (die core) of semiconductor grain 120 via any conductor wire in the semiconductor grain 120.For instance, can use signal from semiconductor package 150 in order to make semiconductor grain 110 and 120 boths, wherein at least one can be coupled to the crystal grain nuclear of semiconductor grain 120 for first weld pad 121 and second weld pad 122.In addition, semiconductor grain 110 and 120 can be positioned at above the substrate (figure do not show) or top (not running into each other), and first conductive component 130 and second conductive component 140 can be positioned at outside the substrate.
First conductive component 130 is coupled between first weld pad 121 of the weld pad 112 of semiconductor grain 110 and semiconductor grain 120, and second conductive component 140 is coupled between second weld pad 122 and semiconductor package 150 of second semiconductor grain 120.Therefore, weld pad 112 can be communicated by letter with semiconductor subassembly 150 with second weld pad 122 by first weld pad 121 of semiconductor grain 120.Therefore, semiconductor grain 110 can be coupled to semiconductor package 150 via first weld pad 121 in weld pad 112 and the weld pad module and second weld pad 122 and first conductive component 130 and second conductive component 140.
In addition, in the combination of the semiconductor device shown in Figure 1A 100, semiconductor grain 110 is coupled to semiconductor package 150 via the weld pad module of semiconductor grain 120.In second execution mode, shown in Figure 1B, for the semiconductor device according to second embodiment of the invention makes up 1400 schematic diagram, semiconductor grain 110 is coupled to another semiconductor grain 1450 via the weld pad module of weld pad 112, semiconductor grain 120 and the weld pad 1452 of another semiconductor grain 1450.The appropriate section of the remainder of semiconductor device combination 1400 and semiconductor device combination 100 is similar, repeats no more herein.
In the method for packing of correlation technique, the weld pad of semiconductor grain is coupled to its corresponding semiconductor package with wiring, the weld pad 112 usefulness wiring of itself and semiconductor grain 110 directly and semiconductor package 150 couple similar., in the method for packing of above-mentioned correlation technique, the distance between the length of above-mentioned wiring or two adjacent wiring may not satisfy wiring rule, and therefore, it is more complicated to reach wiring rule that the design of semiconductor grain can become.In semiconductor device of the present invention combination 100, the weld pad 112 of semiconductor grain 110 can pass through semiconductor grain 120 communicate by letter with semiconductor package 150, and therefore, semiconductor grain 110 and 120 design are more flexible.
In addition, when semiconductor device combination 100 has different application, the specification of for example different TVs or communication system, semiconductor grain 110 and 120 generally need satisfy these different application through repeatedly redesigning.In another embodiment of the present invention, semiconductor grain 120 can be designed to comprise the general utility functions of all application.Therefore, only semiconductor grain 110 need be redesigned to be used for the different application of semiconductor device combination 100.Further, because semiconductor grain 120 comprises first weld pad 121 and second weld pad 122 that allows semiconductor grain 110 to communicate by letter with semiconductor package 150, the redesign of semiconductor device combination 100 can become faster and more effective.
In another embodiment of the present invention, semiconductor grain 110 and 120 one of them can be designed to the combine digital signal processing, and another can be designed to carry out analog.
Fig. 2 is the schematic diagram according to the semiconductor device combination 200 of third embodiment of the invention.Semiconductor device combination 200 comprises two semiconductor grains 210 and 220, a plurality of first conductive components 230, a plurality of second conductive components 240 and a plurality of semiconductor package 250.Semiconductor grain 210 comprises a plurality of weld pads 212.Semiconductor grain 220 comprises the weld pad module, and the weld pad module comprises a plurality of first weld pads 221 and second weld pad 222, and wherein first weld pad 221 couples by the conductor wire 224 and second weld pad 222 respectively.In addition, according to different application, first weld pad 221 and second weld pad 222 can couple or not be coupled to the crystal grain nuclear of semiconductor grain 220 via any conductor wire in the semiconductor grain 220.In addition, first conductive component 230 is coupled between first weld pad 221 of the weld pad 212 of semiconductor grain 210 and semiconductor grain 220, and second conductive component 240 is coupled between second weld pad 222 and semiconductor package 250 of semiconductor grain 220.And semiconductor grain 220 can pile up (stacked) above semiconductor grain 210 or top (not running into each other).In addition, semiconductor grain 210 and 220 can be positioned at above the substrate (figure do not show) or top (not running into each other), and first conductive component 230 and second conductive component 240 can be arranged at outside the substrate.
Fig. 3 is the schematic diagram according to the semiconductor device combination 300 of the 4th execution mode of the present invention.Semiconductor device combination 300 comprises three semiconductor grains 310,320 and 360, a plurality of first conductive components 330, a plurality of second conductive components 340, and a plurality of semiconductor package 350.Semiconductor grain 310 comprises a plurality of weld pads 312.Semiconductor grain 320 comprises the weld pad module, and the weld pad module comprises a plurality of first weld pads 321 and second weld pad 322, and wherein first weld pad 321 couples by the conductor wire 324 and second weld pad 322 respectively.In addition, according to different application, first weld pad 321 and second weld pad 322 can couple or not be coupled to the crystal grain nuclear of semiconductor grain 320 via any conductor wire in the semiconductor grain 320.And, first conductive component 330 is coupled between first weld pad 321 of the weld pad 312 of semiconductor grain 310 and semiconductor grain 320, and second conductive component 340 is coupled between second weld pad 322 and semiconductor package 350 of second semiconductor grain 320.In addition, semiconductor grain 310 and 320 setting (side-by-side) that can walk abreast, semiconductor grain 360 can be stacked in above the semiconductor grain 320, or is stacked in semiconductor grain 320 tops (not running into each other).In addition, semiconductor grain 310,320 and 360 can be positioned at above the substrate (figure do not show) or top (not running into each other), and first conductive component 330 and second conductive component 340 can be positioned at outside the substrate.
Fig. 4 is the schematic diagram according to the semiconductor device combination 400 of the 5th execution mode of the present invention.Semiconductor device combination 400 comprises three semiconductor grains 410,420 and 460, a plurality of first conductive components 430, a plurality of second conductive components 440, and a plurality of semiconductor package 450.Semiconductor grain 410 comprises a plurality of weld pads 412.Semiconductor grain 420 comprises the weld pad module, and the weld pad module comprises a plurality of first weld pads 421 and a plurality of second weld pad 422, and wherein first weld pad 421 couples by the conductor wire 424 and second weld pad 422 respectively.In addition, according to different application, first weld pad 421 and second weld pad 422 can couple or not be coupled to the crystal grain nuclear of semiconductor grain 420 via any conductor wire in the semiconductor grain 420.And, first conductive component 430 is coupled between first weld pad 421 of the weld pad 412 of semiconductor grain 410 and semiconductor grain 420, and second conductive component 440 is coupled between second weld pad 422 and semiconductor package 450 of second semiconductor grain 420.In addition, semiconductor grain 410 and semiconductor grain 460 parallel settings, semiconductor grain 420 can be stacked in above the semiconductor grain 460, or is stacked in semiconductor grain 460 tops (not running into each other).In addition, semiconductor grain 410,420 and 460 can be positioned at above the substrate (figure do not show) or substrate top (not running into each other), and first conductive component 430 and second conductive component 440 can be positioned at outside the substrate.
Fig. 5 is the schematic diagram according to the semiconductor device combination 500 of sixth embodiment of the invention.Semiconductor device combination 500 comprises three semiconductor grains 510,520 and 560, a plurality of first conductive components 530, a plurality of second conductive components 540, and a plurality of semiconductor package 550.Semiconductor grain 510 comprises a plurality of weld pads 512.Semiconductor grain 520 comprises the weld pad module, and the weld pad module comprises a plurality of first weld pads 521 and second weld pad 522, and wherein first weld pad 521 couples by the conductor wire 524 and second weld pad 522 respectively.In addition, according to different application, first weld pad 521 and second weld pad 522 can couple or not be coupled to the crystal grain nuclear of semiconductor grain 520 via any conductor wire in the semiconductor grain 520.And, first conductive component 530 is coupled between first weld pad 521 of the weld pad 512 of semiconductor grain 510 and semiconductor grain 520, and second conductive component 540 is coupled between second weld pad 522 and semiconductor package 550 of second semiconductor grain 520.In addition, semiconductor grain 510 and 560 can be stacked in above the semiconductor grain 520 or be stacked in the top (not running into each other) of semiconductor grain 520.In addition, semiconductor grain 510,520 and 560 can be positioned at above the substrate (figure do not show) or substrate top (not running into each other), and first conductive component 530 and second conductive component 540 can be positioned at outside the substrate.
It should be noted that in other execution mode of the present invention, semiconductor package 250,350,450 and 550 can be the lead-in wire of lead frame or the pin of ball grid array base plate.Semiconductor grain 210,310,410 and 510 can be used for the combine digital signal processing, and semiconductor grain 220,320,420 and 520 can be used to carry out analog; Perhaps semiconductor grain 210,310,410 and 510 can be used for carrying out analog, and semiconductor grain 220,320,420 and 520 can be used to the combine digital signal processing.
Fig. 6 is the schematic diagram according to the semiconductor device combination 600 of the 7th execution mode of the present invention.Semiconductor device combination 600 comprises three semiconductor grains 610,620 and 660, a plurality of first conductive components 630, a plurality of second conductive components 640, a plurality of the 3rd conductive components 670, and a plurality of semiconductor package 650.Semiconductor grain 610 comprises a plurality of weld pads 612, and wherein, according to different application, weld pad 612 can couple or not be coupled to the crystal grain nuclear of semiconductor grain 610 via any conductor wire in the semiconductor grain 610.Semiconductor grain 620 comprises the weld pad module, and the weld pad module comprises a plurality of first weld pads 621 and second weld pad 622, and wherein first weld pad 621 couples by the conductor wire 624 and second weld pad 622 respectively.In addition, first weld pad 621 and second weld pad 622 can couple or not be coupled to the crystal grain nuclear of semiconductor grain 620 via any conductor wire in the semiconductor grain 620.In addition, semiconductor grain 610 and 620 setting that can walk abreast, but invention and not only in this, semiconductor grain 660 also is not limited only to be stacked in the top or top (not running into each other) of semiconductor grain 610.And semiconductor grain 610,620 and 660 can be positioned at above the substrate (figure does not show) or top (not running into each other), and first conductive component, 630, the second conductive components 640 and the 3rd conductive component 670 can be positioned at outside the substrate.
First conductive component 630 is respectively coupled between first weld pad 621 of the weld pad 612 of semiconductor grain 610 and semiconductor grain 620, second conductive component 640 is respectively coupled between second weld pad 622 and semiconductor package 650 of second semiconductor grain 620, and the 3rd conductive component 670 is respectively coupled between the weld pad 612 of the weld pad 662 of semiconductor grain 660 and semiconductor grain 610.Therefore, weld pad 662 can be communicated by letter with semiconductor package 650 by weld pad 612,621 and 622.
In addition, in the semiconductor device combination 600 as shown in Figure 6, semiconductor grain 610 and 620 parallel settings, semiconductor grain 660 is stacked in above the semiconductor grain 610 or top (not running into each other)., in other execution mode of the present invention, semiconductor grain 610 and 620 one of them can be stacked in semiconductor grain 610 and 620 another top or top (not running into each other) wherein; Perhaps, semiconductor grain 660 can be stacked in the top or top (not running into each other) of semiconductor grain 620.These and other variation designs all within the scope of the invention.
Fig. 7 is the schematic diagram according to the semiconductor device combination 700 of the 8th execution mode of the present invention.It is 100 similar that semiconductor device combination 700 and the semiconductor device shown in Figure 1A make up, and difference is that the top or top of semiconductor grain 110 has additional semiconductor 760.And in Fig. 7, semiconductor grain 760 is stacked in the top or top (not running into each other) of semiconductor grain 110., in other execution mode of the present invention, semiconductor grain 760 can also be placed on below the semiconductor grain 110 or below (not running into each other).
It should be noted that in other execution mode the semiconductor package 200-700 as shown in Fig. 2 to Fig. 7 can be replaced by another semiconductor grain.With semiconductor device combination 200 is example, and semiconductor grain 210 can be coupled to another semiconductor grain via the weld pad module of semiconductor grain 220.
Please refer to Fig. 8.Fig. 8 is the schematic diagram according to the semiconductor device combination 800 of the 9th execution mode of the present invention.Semiconductor device combination 800 comprises two semiconductor grains 810 and 820, a plurality of first conductive components 830, a plurality of second conductive components 840, and a plurality of semiconductor package 850.Semiconductor grain 810 comprises a plurality of weld pads 812.Semiconductor grain 820 comprises the weld pad module, and the weld pad module comprises a plurality of weld pads 822 of arranging with array way.According to different application, weld pad 822 can be electrically connected or be not attached to the crystal grain nuclear of semiconductor grain 820 via any conductor wire in the semiconductor grain 820.For instance, for the signal of transmission between semiconductor grain 810 and semiconductor package 850, weld pad 822 can not be electrically connected to the crystal grain nuclear of semiconductor grain 820.
In addition, each first conductive component 830 all is coupled between the weld pad 812 of the weld pad 822 of semiconductor grain 820 and semiconductor grain 810.Each second conductive component 840 is coupled between the weld pad 822 and semiconductor package 850 of semiconductor grain 820.Therefore, weld pad 812 can be communicated by letter with semiconductor package 850 by the weld pad 822 of semiconductor grain 820.So semiconductor grain 810 can be coupled to semiconductor package 850 or another semiconductor grain via weld pad 822 and first conductive component 830 and second conductive component 840 of weld pad 812 with the weld pad module.
In the method for packing of correlation technique, the weld pad of semiconductor grain is coupled to its corresponding semiconductor package with wiring.But the distance between the length of wiring and two adjacent wiring possibly can't satisfy wiring rule, and therefore, in order to satisfy wiring rule, it is more complicated that the design of semiconductor grain can become.And in semiconductor packages 800 of the present invention, the weld pad 812 of semiconductor grain 810 can be communicated by letter with semiconductor package 850 by semiconductor grain 820, and therefore, semiconductor grain 810 and 820 design are just more flexible.
In addition, semiconductor package 850 can be the lead-in wire of lead frame or the pin of ball grid array base plate.
In addition, when semiconductor device combination 800 had different application, for example during the different size of TV or communication system, semiconductor grain 810 and 820 generally needed to redesign repeatedly satisfy these different application.In another embodiment of the present invention, semiconductor grain 820 can be designed to comprise the general utility functions of all application.Therefore, only there is semiconductor grain 810 to be redesigned in the different application of semiconductor device combination 800.And, because comprising weld pad 822, semiconductor grain 820 can communicate by letter with semiconductor package 850 to allow semiconductor grain 810, the redesign of semiconductor device combination 800 becomes quicker and effective.
Fig. 9 is the schematic diagram according to the semiconductor device combination 900 that comprises the semiconductor grain 820 among Fig. 8 of the tenth execution mode of the present invention.As shown in Figure 9, because do not need to replace semiconductor grain 820, and because the weld pad 912 of semiconductor grain 910 can select to be connected to different connected modes the weld pad 822 of the semiconductor grain 820 of arranging with array way, communicate by letter with semiconductor package 950, so the design of semiconductor device combination 900 can be more effective.
In another embodiment of the present invention, semiconductor grain 810 and 820 one of them can be designed to the combine digital signal processing, and another is designed to carry out analog.
Please refer to Figure 10.Figure 10 is the schematic diagram of the semiconductor device combination 1000 of the 11 execution mode of the present invention.Semiconductor device combination 1000 comprises two semiconductor grains 1010 and 1020, a plurality of first conductive components 1030, a plurality of second conductive components 1040, and a plurality of semiconductor package 1050.Semiconductor grain 1010 comprises a plurality of weld pads 1012.Semiconductor grain 1020 comprises the weld pad module, and the weld pad module comprises a plurality of weld pads 1022 of arranging with array way, and wherein weld pad 1022 can be electrically connected or be not attached to semiconductor grain 1020 via any conductor wire in the semiconductor grain 1020 according to different application.Further, each first conductive component 1030 is coupled between the weld pad 1012 of the weld pad 1022 of semiconductor grain 1020 and semiconductor grain 1010, and each second conductive component 1040 is coupled between the weld pad 1022 and semiconductor package 1050 of semiconductor grain 1020.In addition, semiconductor grain 1010 can be stacked in above the semiconductor grain 1020 or top (not running into each other).
Please refer to Figure 11.Figure 11 is the schematic diagram according to the semiconductor device assembly 1100 of the 12 execution mode of the present invention.Semiconductor device combination 1100 comprises three semiconductor grains 1110,1120 and 1160, a plurality of first conductive components 1130, a plurality of second conductive components 1140, a plurality of the 3rd conductive components 1170, and a plurality of semiconductor package 1150.Semiconductor grain 1110 comprises a plurality of weld pads 1112, and it can be electrically connected or be not attached to the crystal grain nuclear of semiconductor grain 1110 according to different application via any conductor wire in the semiconductor grain 1110.Semiconductor grain 1120 comprises the weld pad module, the weld pad module comprises a plurality of weld pads 1122 of arranging with array way, and weld pad 1122 can be electrically connected or be not attached to the crystal grain nuclear of semiconductor grain 1120 according to different application via any conductor wire in the semiconductor grain 1120.Semiconductor grain 1160 comprises a plurality of weld pads 1162.In addition, semiconductor grain 1110 and 1160 can be stacked in the top or top (not running into each other) of semiconductor grain 1120.
Each first conductive component 1130 is coupled between the weld pad 1112 of the weld pad 1122 of semiconductor grain 1120 and semiconductor grain 1110, each second conductive component 1140 is coupled between the weld pad 1122 and semiconductor package 1150 of semiconductor grain 1120, and each the 3rd conductive component 1170 is coupled between the weld pad 1162 of the weld pad 1112 of semiconductor grain 1110 and semiconductor grain 1160.Therefore, weld pad 1162 can be communicated by letter with semiconductor package 1150 by weld pad 1112 and 1122.
Please refer to Figure 12.Figure 12 is the schematic diagram according to the semiconductor device combination 1200 of the 13 execution mode of the present invention.Semiconductor device combination 1200 comprises three semiconductor grains 1210,1220 and 1260, a plurality of first conductive components 1230, a plurality of second conductive components 1240, a plurality of the 3rd conductive components 1270, and a plurality of semiconductor packages 1250.Semiconductor grain 1210 comprises a plurality of weld pads 1212, and weld pad 1212 can be electrically connected or be not attached to the crystal grain nuclear of semiconductor grain 1210 according to different application via any conductor wire in the semiconductor grain 1210.Semiconductor grain 1220 comprises the weld pad module, the weld pad module comprises a plurality of weld pads 1222 of arranging with array way, and weld pad 1222 can be electrically connected or be not attached to the crystal grain nuclear of semiconductor grain 1220 according to different application via any conductor wire in the semiconductor grain 1220.Semiconductor grain 1260 comprises a plurality of weld pads 1262.In addition, semiconductor grain 1210 can be stacked in above the semiconductor grain 1220 or top (not running into each other).The annexation and the conductive component among Figure 11 1130,1140 and 1170 that it should be noted that first conductive component 1230, second conductive component 1240 and the 3rd conductive component 1270 are similar, therefore, repeat no more herein.
Figure 13 is the schematic diagram according to the semiconductor device combination 1300 of the 14 execution mode of the present invention.It is 800 similar that semiconductor device combination 1300 and semiconductor device shown in Figure 8 make up, difference only be on semiconductor grain 810 or above (not running into each other) have additional semiconductor grain 1360.In addition, in Figure 13, semiconductor grain 1360 can be stacked in above the semiconductor grain 810 or top (not running into each other),, in other execution mode of the present invention, semiconductor grain 1360 also can be positioned over below the semiconductor grain 810 or below (not running into each other).
In addition, to semiconductor device combination 800-1300 shown in Figure 13, semiconductor grain 810,910,1010,1110 or 1210 one of them weld pad only are coupled to semiconductor package via semiconductor grain 820,1020,1120 or 1220 one of them weld pad in Fig. 8., in other execution mode of the present invention, be example with semiconductor device combination 800, a weld pad 812 can be coupled to semiconductor package 850 via two or more weld pads 822 of semiconductor grain 820.In addition, semiconductor grain 820,1020,1120 and 1120 weld pad can have other shape, rather than the rectangle as shown in Fig. 8-13.
It should be noted that in other execution mode the semiconductor device combination 800-1300 shown in Fig. 8-13 can be substituted by other semiconductor grain.With semiconductor device combination 800 is example, and semiconductor grain 810 can be coupled to another semiconductor grain via the weld pad module of semiconductor grain 820.
Generally speaking, in semiconductor device combination of the present invention, a semiconductor grain can be communicated by letter with semiconductor package or other semiconductor grain via the weld pad of another semiconductor grain.Therefore, the wiring meeting between semiconductor grain and the semiconductor package is easier, and the design of semiconductor grain also can be more flexible.
Though the present invention with the better embodiment explanation as above; yet it is not to be used for limiting scope of the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; any change and the change made; all in protection scope of the present invention, specifically the scope that defines with claim is as the criterion.
Claims (24)
1. semiconductor device combination comprises:
First semiconductor grain comprises at least one weld pad;
Second semiconductor grain comprises the weld pad module, comprises a plurality of weld pads of arranging with array way in the wherein above-mentioned weld pad module;
At least one semiconductor package or another semiconductor grain;
First conductive component is coupled between the above-mentioned weld pad of the above-mentioned weld pad module of above-mentioned second semiconductor grain and above-mentioned first semiconductor grain; And
Second conductive component is coupled to above-mentioned weld pad module and above-mentioned semiconductor package or above-mentioned second half conductor intergranule of above-mentioned second semiconductor grain;
Wherein above-mentioned first semiconductor grain is coupled to above-mentioned semiconductor package or above-mentioned another semiconductor grain via above-mentioned weld pad, above-mentioned weld pad module and above-mentioned first conductive component and above-mentioned second conductive component.
2. semiconductor device combination as claimed in claim 1 is characterized in that, at least one weld pad is not electrically connected to the crystal grain nuclear of above-mentioned second semiconductor grain in the above-mentioned weld pad module via any conductor wire of the above-mentioned second semiconductor die intragranular.
3. semiconductor device combination as claimed in claim 1 is characterized in that:
The above-mentioned weld pad module of above-mentioned second semiconductor grain comprises first weld pad and second weld pad that is coupled to each other;
Above-mentioned first conductive component is coupled between above-mentioned first weld pad of the above-mentioned weld pad of above-mentioned first semiconductor grain and above-mentioned second semiconductor grain;
Above-mentioned second conductive component is coupled to above-mentioned second weld pad and above-mentioned semiconductor package or above-mentioned second half conductor intergranule of above-mentioned second semiconductor grain; And
Above-mentioned first semiconductor grain and above-mentioned second semiconductor grain are positioned at above the substrate or the top, and above-mentioned first conductive component and above-mentioned second conductive component are positioned at outside the aforesaid substrate.
4. semiconductor device combination as claimed in claim 1, it is characterized in that, one of them is used for the combine digital signal processing above-mentioned first semiconductor grain and above-mentioned second semiconductor grain, and wherein another of above-mentioned first semiconductor grain and above-mentioned second semiconductor grain is used to carry out analog.
5. semiconductor device combination as claimed in claim 1 is characterized in that above-mentioned semiconductor package is the lead-in wire of lead frame or the pin of ball grid array base plate.
6. semiconductor device as claimed in claim 1 combination is characterized in that, one of them is stacked in above-mentioned first semiconductor grain and above-mentioned second semiconductor grain another top or top wherein above-mentioned first semiconductor grain and above-mentioned second semiconductor grain.
7. semiconductor device as claimed in claim 1 combination is characterized in that, more comprises: the 3rd semiconductor grain is positioned at above above-mentioned second semiconductor grain, top, following or below.
8. semiconductor device as claimed in claim 1 combination is characterized in that, more comprises: the 3rd semiconductor grain is positioned at above above-mentioned first semiconductor grain, top, following or below.
9. semiconductor device combination as claimed in claim 1 is characterized in that, more comprises:
The 3rd semiconductor grain comprises at least one weld pad; And
The 3rd conductive component is coupled between the above-mentioned weld pad of the above-mentioned weld pad of above-mentioned first semiconductor grain and above-mentioned the 3rd semiconductor grain.
10. semiconductor device combination as claimed in claim 9, it is characterized in that one of them is stacked in above-mentioned first semiconductor grain and above-mentioned second semiconductor grain another top or top wherein above-mentioned first semiconductor grain and above-mentioned second semiconductor grain.
11. semiconductor device as claimed in claim 9 combination is characterized in that, above-mentioned the 3rd semiconductor grain is positioned at top, the top of above-mentioned second semiconductor grain, following or below.
12. semiconductor device as claimed in claim 9 combination is characterized in that, above-mentioned the 3rd semiconductor grain is positioned at top, the top of above-mentioned first semiconductor grain, following or below.
13. one kind is used for setting up the method that is electrically connected in the semiconductor device combination, comprises:
First semiconductor grain is provided, and it comprises at least one weld pad;
Second semiconductor grain is provided, and it comprises the weld pad module, comprises a plurality of weld pads of arranging with array way in the wherein above-mentioned weld pad module;
At least one semiconductor package or another semiconductor grain are provided;
Between the above-mentioned weld pad of the above-mentioned weld pad module of above-mentioned second semiconductor grain and above-mentioned first semiconductor grain, place first conductive component; And
Place second conductive component in the above-mentioned weld pad module of above-mentioned second semiconductor grain and above-mentioned second semiconductor package or above-mentioned second half conductor intergranule;
Wherein above-mentioned first semiconductor grain is coupled to above-mentioned semiconductor package or above-mentioned another semiconductor grain via above-mentioned weld pad, above-mentioned weld pad module, above-mentioned first conductive component and above-mentioned second conductive component.
14. as claimed in claim 13 being used for set up the method that is electrically connected in the semiconductor device combination, it is characterized in that at least one weld pad is not electrically connected to the crystal grain nuclear of above-mentioned second semiconductor grain in the above-mentioned weld pad module via any conductor wire of the above-mentioned second semiconductor die intragranular.
15. as claimed in claim 13 being used for set up the method that is electrically connected in the semiconductor device combination, it is characterized in that:
The above-mentioned weld pad module of above-mentioned second semiconductor grain comprises first weld pad and second weld pad that is coupled to each other;
Above-mentioned first conductive component is coupled between above-mentioned first weld pad of the weld pad of above-mentioned first semiconductor grain and above-mentioned second semiconductor grain;
Above-mentioned second conductive component is coupled to above-mentioned second weld pad and above-mentioned semiconductor package or above-mentioned second half conductor intergranule of above-mentioned second semiconductor grain; And
Above-mentioned first semiconductor grain and above-mentioned second semiconductor grain are positioned at above the substrate or the top, and above-mentioned first conductive component and above-mentioned second conductive component are positioned at outside the aforesaid substrate.
16. as claimed in claim 13 being used for set up the method that is electrically connected in the semiconductor device combination, it is characterized in that, one of them is used for the combine digital signal processing above-mentioned first semiconductor grain and above-mentioned second semiconductor grain, and wherein another of above-mentioned first semiconductor grain and above-mentioned second semiconductor grain is used to carry out analog.
17. as claimed in claim 13 being used for set up the method that is electrically connected in the semiconductor device combination, it is characterized in that above-mentioned semiconductor package is the lead-in wire of lead frame or the pin of ball grid array base plate.
18. as claimed in claim 13 being used for set up the method that is electrically connected in the semiconductor device combination, it is characterized in that, more comprises:
Place above-mentioned first semiconductor grain and above-mentioned second semiconductor grain one of them in above-mentioned first semiconductor grain and above-mentioned second semiconductor grain wherein another above or the top.
19. as claimed in claim 13 being used for set up the method that is electrically connected in the semiconductor device combination, it is characterized in that, more comprises:
Place the 3rd semiconductor grain above above-mentioned second semiconductor grain, the top, below or the below.
20. as claimed in claim 13 being used for set up the method that is electrically connected in the semiconductor device combination, it is characterized in that, more comprises:
Place the 3rd semiconductor grain above above-mentioned first semiconductor grain, the top, below or the below.
21. as claimed in claim 13 being used for set up the method that is electrically connected in the semiconductor device combination, it is characterized in that, more comprises:
The 3rd semiconductor grain is provided, and it comprises at least one weld pad; And
Between the above-mentioned weld pad of the above-mentioned weld pad of above-mentioned first semiconductor grain and above-mentioned the 3rd semiconductor grain, place the 3rd conductive component.
22. as claimed in claim 21 being used for set up the method that is electrically connected in the semiconductor device combination, it is characterized in that, more comprises:
Place above-mentioned first semiconductor grain and above-mentioned second semiconductor grain one of them in above-mentioned first semiconductor grain and above-mentioned second semiconductor grain wherein another above or the top.
23. as claimed in claim 21 being used for set up the method that is electrically connected in the semiconductor device combination, it is characterized in that, more comprises:
Place above-mentioned the 3rd semiconductor grain above above-mentioned second semiconductor grain, the top, below or the below.
24. as claimed in claim 21 being used for set up the method that is electrically connected in the semiconductor device combination, it is characterized in that, more comprises:
Place above-mentioned the 3rd semiconductor grain above above-mentioned first semiconductor grain, the top, below or the below.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US5721108P | 2008-05-30 | 2008-05-30 | |
| US61/057,211 | 2008-05-30 | ||
| US12/396,450 US8049321B2 (en) | 2008-05-30 | 2009-03-02 | Semiconductor device assembly and method thereof |
| US12/396,450 | 2009-03-02 |
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| CN101593747A CN101593747A (en) | 2009-12-02 |
| CN101593747B true CN101593747B (en) | 2011-05-18 |
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| CN2009102036219A Active CN101593747B (en) | 2008-05-30 | 2009-05-26 | A semiconductor device assembly and a method of establishing electric connection in the semiconductor device assembly |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5715147A (en) * | 1990-12-20 | 1998-02-03 | Kabushiki Kaisha Toshiba | Semiconductor device having an interconnecting circuit board |
| US5789816A (en) * | 1996-10-04 | 1998-08-04 | United Microelectronics Corporation | Multiple-chip integrated circuit package including a dummy chip |
| CN1498423A (en) * | 2001-03-02 | 2004-05-19 | �����ɷ� | Mixed analog and digital inegrated circits |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP3545200B2 (en) * | 1997-04-17 | 2004-07-21 | シャープ株式会社 | Semiconductor device |
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- 2009-05-26 TW TW98117496A patent/TWI384610B/en active
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5715147A (en) * | 1990-12-20 | 1998-02-03 | Kabushiki Kaisha Toshiba | Semiconductor device having an interconnecting circuit board |
| US5789816A (en) * | 1996-10-04 | 1998-08-04 | United Microelectronics Corporation | Multiple-chip integrated circuit package including a dummy chip |
| CN1498423A (en) * | 2001-03-02 | 2004-05-19 | �����ɷ� | Mixed analog and digital inegrated circits |
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| TW200950057A (en) | 2009-12-01 |
| CN101593747A (en) | 2009-12-02 |
| TWI384610B (en) | 2013-02-01 |
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