CN101593729B - Method for manufacturing silication metal electrode of OTP memory - Google Patents
Method for manufacturing silication metal electrode of OTP memory Download PDFInfo
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- CN101593729B CN101593729B CN2009100497901A CN200910049790A CN101593729B CN 101593729 B CN101593729 B CN 101593729B CN 2009100497901 A CN2009100497901 A CN 2009100497901A CN 200910049790 A CN200910049790 A CN 200910049790A CN 101593729 B CN101593729 B CN 101593729B
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Abstract
The invention provides a method for manufacturing a silication metal electrode of an OTP memory. The method is carried out after a first control grid, a first float grid, a second grid and a second control grid which are arranged in sequence are manufactured. The OTP memory is provided with a silication metal block area and a silication metal electrode area. The metal electrode area comprises a bit line area positioned between the first float gird and the second float grid. A bit line area graph is formed by a photoresist photoetching process or a photoetching process matched with a bottom anti-reflection coating as a mask in the prior art, because the size of the bit line area is small, the consideration to the quality of the bit line area graph and the quality of the OTP memory is difficult to realize. The method comprises: firstly depositing a block oxidation layer, then depositing double layers of hard reticle mask layers, etching to form a mask graph of the bit line area, photoetching the bit line area with small size by the hard mask photoetching process, and then photoetching other graphs with larger characteristic sizes by the photoresist photoetching process. The method can realize the consideration to the photoetching quality and the maintaining performance of the OTP memory, and meets the demands of miniaturization.
Description
Technical field
The present invention relates to the manufacturing process of otp memory, relate in particular to a kind of method for manufacturing silication metal electrode of otp memory.
Background technology
The floating boom transistor has become the basic device architecture of nonvolatile semiconductor memory at present.When making had the memory of floating boom, the control gate and the floating boom that can adopt the double-layered polycrystal silicon structure to form to pile up also can adopt the single level polysilicon structure to form the floating boom and the control gate of parallel arrangement.The double-layered polycrystal silicon structure can effectively improve the density of memory; But its processing procedure is incompatible with the standard CMOS processing procedure; Need to make extra light shield and increase extra step; Thereby cost is higher, is generally used for flash memory (FLASH) and Electrically Erasable Read Only Memory (Electrically-Erasable Programmable Read-Only Memory at present; Be called for short EEPROM) in.The single level polysilicon structure can be compatible with the regular transistor processing procedure, thereby cost is lower, existing disposable programmable (the One Time Programming Memory that is applied to usually; Abbreviation OTP) in the memory.
Referring to Fig. 1 and Fig. 2, vertical view and composition structural representation that it has shown otp memory are simplicity of illustration, doped region are not shown.As depicted in figs. 1 and 2, said otp memory comprises the first control gate CG1, the first floating boom FG1, the second floating boom FG2 and the second control gate CG2 that arranges successively.Said otp memory also has bitline regions BL, the first source area SL1, the second source area SL2, metal silicide blocking area SABA and silication metal electrode district SAEA.Bitline regions BL is between the first floating boom FG1 and the second floating boom FG2.The first source area SL1 is positioned at the side of the first control gate CG1 away from the first floating boom FG1, and the second source area SL2 is positioned at the side of the second control gate CG2 away from the second floating boom FG2.Said silication metal electrode district SAEA comprises the first control gate CG1, the second control gate CG2, bitline regions BL, the first source area SL1 and the second source area SL2.
After the making of accomplishing the first control gate CG1, the first floating boom FG1, the second control gate CG2 and the second floating boom FG2 and corresponding side wall thereof, need on silication metal electrode district SAEA, make silication metal electrode SAE.The detailed step that prior art is made silication metal electrode SAE is: at first deposition stops oxide layer, and stoping the thickness of oxide layer scope is 300 to 2000 dusts; Apply photoresist then and make the shape of silication metal electrode district SAEA by lithography; Then form metal silicide blocking layer SAB through dry etch process; Use hydrofluoric acid (DHF) the removal oxide after diluting residual afterwards; At last, remove technology through physical gas-phase deposition, Technology for Heating Processing and kish and on silication metal electrode district SAEA, form silication metal electrode SAE.In above-mentioned processing procedure, because the spacing less (can be as small as 0.28 micron or littler) between the first floating boom FG1 and the second floating boom FG2 adopts the technology of photoresist photoetching to be difficult to form accurately bitline regions BL.
For overcoming the problems referred to above, elder generation deposited one deck organic bottom antireflective coating (Bottom Anti-Reflective Coating before the someone had proposed to be employed in the coating photoresist again in the prior art; Be called for short BARC) or inorganic bottom antireflective coatings (Dielectric Anti-Reflectivity Coating; Abbreviation DARC) method.BARC and DARC can obtain better live width control and wideer process window through the reflectivity of control substrate when the photoetching, thereby can improve the photoetching quality of bitline regions BL.Thereby but be prone to the etching that residual BARC in the small space between the first floating boom FG1 and the second floating boom FG2 influences bitline regions BL when applying BARC.When adopting DARC, thereby DARC is prone to remain in the first floating boom FG1 and the second floating boom FG2 goes up the maintenance performance that reduces data.
Therefore; How a kind of method for manufacturing silication metal electrode of otp memory is provided; Overcome the demand that characteristic size that common photoresist photoetching process can't satisfy otp memory neutrality line district reduces day by day; And the data of taking into account otp memory simultaneously keep performance, have become the technical problem that industry needs to be resolved hurrily.
Summary of the invention
The object of the present invention is to provide a kind of method for manufacturing silication metal electrode of otp memory; Can overcome the demand that characteristic size that photoetching process can't satisfy otp memory neutrality line district reduces day by day through said method; And the data of taking into account otp memory simultaneously keep performance, the development trend of adaptation otp memory miniaturization.
The objective of the invention is to realize like this: a kind of method for manufacturing silication metal electrode of otp memory; It carries out after having made first control gate, first floating boom, second floating boom and second control gate of arranging successively; This otp memory has metal silicide blocking area and silication metal electrode district; This silication metal electrode district comprises the bitline regions that is positioned between first floating boom and second floating boom, and this method may further comprise the steps: a, deposition stop oxide layer; B, deposition first hard mask layer; C, apply photoresist and make bitline regions by lithography; D, carry out etching technics and on first hard mask layer, form the bitline regions figure; E, deposition second hard mask layer; F, etching second hard mask layer are to form the mask side wall on the bitline regions figure two side of first hard mask layer; G, form the bitline regions figure on the oxide layer to stop carrying out etching technics under the covering of first hard mask layer and mask side wall; H, removal first hard mask layer and mask side wall; I, coating photoresist also pass through photoetching process and remove metal silicide blocking area and the outer photoresist of bitline regions; J, carry out etching technics to form the metal silicide blocking layer; K, make silication metal electrode in the silication metal electrode district.
In the method for manufacturing silication metal electrode of above-mentioned otp memory, in step a, this prevention thickness of oxide layer scope is 300 to 2000 dusts.
In the method for manufacturing silication metal electrode of above-mentioned otp memory, in step g, the etching technics etching is removed bitline regions and is stoped 80% to 98% of oxidated layer thickness.
In the method for manufacturing silication metal electrode of above-mentioned otp memory, this step j may further comprise the steps: j1, carry out the dry etch process etching and remove to stop 80% to 98% of oxidated layer thickness; Photoresist on j2, removal metal silicide blocking area and the bitline regions; J3, carry out wet-etching technology and remove the prevention oxide layer in the silication metal electrode district, and form the metal silicide blocking layer.
In the method for manufacturing silication metal electrode of above-mentioned otp memory, in step j3, the etching liquid of wet-etching technology is a hydrofluoric acid, or the mixed liquor of hydrofluoric acid and ammonium fluoride.
In the method for manufacturing silication metal electrode of above-mentioned otp memory, this first hard mask layer and second hard mask layer include silicon nitride.
In the method for manufacturing silication metal electrode of above-mentioned otp memory, this first hard mask layer and second hard mask layer are all through plasma reinforced chemical vapour deposition technology or low-pressure chemical vapor deposition process deposition.
In the method for manufacturing silication metal electrode of above-mentioned otp memory, the thickness range of this first hard mask layer and second hard mask layer is 200 to 1800 dusts, the width negative correlation of the thickness of this first hard mask layer and second hard mask layer and the electrode of bitline regions.
In the method for manufacturing silication metal electrode of above-mentioned otp memory, step k may further comprise the steps: k1, carry out the deposited by pvd metal; K2, heat-treat to form silication metal electrode in the silication metal electrode district; K3, removal unreacted metal.
In the method for manufacturing silication metal electrode of above-mentioned otp memory, this metal comprises cobalt, titanium or nickel, and this silication metal electrode comprises cobalt silicide electrode, titanium silicide electrode and nickle silicide electrode.
Accomplish the photoetching of metal silicide blocking layer with the photoetching process of available technology adopting single-layer lithography glue or photoresist collocation BARC; Can't satisfy the less photoetching demand of metal silicide blocking layer characteristic size compares; The method for manufacturing silication metal electrode of otp memory of the present invention adopts hard mask lithography technology to make the less figure of characteristic size by lithography; Adopting photoresist afterwards is that the photoetching process of mask defines the bigger figure of other characteristic sizes; Thereby adapt to the ever-reduced demand of silicide metals trapping layer characteristic size, also adapt to the demand of otp memory miniaturization simultaneously.
Keep performance with the easy data that influence otp memory of photoetching process of available technology adopting DARC collocation photoresist; The present invention adopts the double-deck hard mask that is easy to remove; Both satisfied the metal silicide blocking layer and had photoetching demand, and can not remain in the data that influence otp memory on first floating boom and second floating boom simultaneously again and keep performance than the small-feature-size figure.
Description of drawings
The method for manufacturing silication metal electrode of otp memory of the present invention is provided by following embodiment and accompanying drawing.
Fig. 1 is the vertical view of otp memory among the present invention;
Fig. 2 is the composition structural representation of otp memory among the present invention;
Fig. 3 is the composition structural representation that carries out the preceding otp memory of method for manufacturing silication metal electrode of otp memory of the present invention;
Fig. 4 is the flow chart of the method for manufacturing silication metal electrode of otp memory of the present invention;
Fig. 5 to Figure 17 is respectively and accomplishes among Fig. 3 the composition structural representation of otp memory behind step S10 to S18, S20, S21, S22, the S24.
Embodiment
Below will do further to describe in detail to the method for manufacturing silication metal electrode of otp memory of the present invention.
Referring to Fig. 3; It has shown the composition structural representation of the otp memory before making silication metal electrode; As shown in the figure, said otp memory comprises the first control gate CG1, the first floating boom FG1, the second floating boom FG2 and the second control gate CG2 and the corresponding side wall thereof of arranging successively.Said otp memory has bitline regions BL, the first source area SL1, the second source area SL2, metal silicide blocking area SABA and silication metal electrode district SAEA.Bitline regions BL is between the first floating boom FG1 and the second floating boom FG2.The first source area SL1 is positioned at the side of the first control gate CG1 away from the first floating boom FG1, and the second source area SL2 is positioned at the side of the second control gate CG2 away from the second floating boom FG2.Said silication metal electrode district SAEA comprises the first control gate CG1, the second control gate CG2, bitline regions BL, the first source area SL1 and the second source area SL2.
What need explanation is, is simplicity of illustration and explanation, and accompanying drawing does not all show trap and doped region in the present embodiment.
Referring to Fig. 4; It has shown the flow chart of embodiment of the method for manufacturing silication metal electrode of otp memory of the present invention; Said method is at first carried out step S10, and deposition stops oxide layer, wherein; Said prevention thickness of oxide layer scope is 300 to 2000 dusts, can adopt plasma reinforced chemical vapour deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) process deposits to form.In the present embodiment, said prevention thickness of oxide layer is 1600 dusts, employing be LPCVD technology.
Referring to Fig. 5, in conjunction with referring to Fig. 3, Fig. 5 has shown the structure of having accomplished otp memory behind the step S10, and is as shown in the figure, stops oxide layer 10 to cover metal silicide blocking area SABA and silication metal electrode district SAEA.
Then continue step S11; Deposit first hard mask layer through chemical vapor deposition method; Wherein, The thickness range of said first hard mask layer is 200 to 1800 dusts, and said chemical vapor deposition method can be plasma reinforced chemical vapour deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) technology.In the present embodiment, said first hard mask layer is processed through LPCVD technology, and the said first hard mask layer thickness is 1000 dusts, and said first hard mask layer is a silicon nitride.
Referring to Fig. 6, in conjunction with referring to Fig. 3 and Fig. 5, Fig. 6 has shown the structure of having accomplished otp memory behind the step S11, and as shown in the figure, first hard mask layer 11 covers and stops on the oxide layer 10.
Then continue step S12, apply photoresist and make bitline regions by lithography.
Referring to Fig. 7, in conjunction with referring to Fig. 3, Fig. 5 and Fig. 6, Fig. 7 has shown the structure of having accomplished otp memory behind the step S12, and as shown in the figure, photoresist 12 covers on first hard mask layer 11, and has bitline regions figure 120 on the photoresist 12.
Then continue step S13, carry out etching technics and on first hard mask layer, form the bitline regions figure.In the present embodiment, the etching technics in the said step is a dry etch process, and etching gas comprises oxygen (O
2) and carbon tetrafluoride (CF
4).
Referring to Fig. 8, in conjunction with referring to Fig. 3, Fig. 5 to Fig. 7, Fig. 8 has shown the structure of having accomplished otp memory behind the step S13, and is as shown in the figure, formed bitline regions figure 110 on first hard mask layer 11.
Then continue step S14, deposit second hard mask layer through chemical vapor deposition method, wherein, the thickness range of said second hard mask layer is 200 to 1800 dusts, and said chemical vapor deposition method can be LPCVD or PECVD.In the present embodiment, said second hard mask layer is processed through LPCVD technology, and the said second hard mask layer thickness is 800 dusts, and said second hard mask layer is a silicon nitride.
Referring to Fig. 9, in conjunction with referring to Fig. 3, Fig. 5 to Fig. 8, Fig. 9 has shown the structure of having accomplished otp memory behind the step S14, and is as shown in the figure, and second hard mask layer 13 covers on first hard mask layer 11 and partially filled bitline regions figure 110.
Then continue step S15, etching second hard mask layer is to form the mask side wall on the bitline regions figure two side of first hard mask layer.In the present embodiment, the etching technics in the said step is a dry etch process, and etching gas comprises oxygen (O
2) and carbon tetrafluoride (CF
4).
Referring to Figure 10, in conjunction with referring to Fig. 3, Fig. 5 to Fig. 9, Figure 10 has shown the structure of having accomplished otp memory behind the step S15, and as shown in the figure, mask side wall 111 and 112 is formed on the two side of bitline regions figure 110.
Then continue step S16, carrying out etching technics under the covering of first hard mask layer and mask side wall to stop formation bitline regions figure on the oxide layer, wherein, the etching technics etching is removed bitline regions and is stoped 80% to 98% of oxidated layer thickness.In the present embodiment, said etching technics is a dry etching, and etching gas comprises O
2And CF
4, etching is removed bitline regions and is stoped 90% of oxidated layer thickness, and etching off is except the prevention oxide layer of 1440 dusts at once.
Referring to Figure 11, in conjunction with referring to Fig. 3, Fig. 5 to Figure 10, Figure 11 has shown the structure of having accomplished otp memory behind the step S16, and is as shown in the figure, stops on the oxide layer 10 to have formed bitline regions figure 100, and bitline regions SL goes up the residual prevention oxide layer that 160 dusts are arranged.
Then continue step S17, remove first hard mask layer and mask side wall through wet-etching technology.In the present embodiment, etching liquid is a phosphoric acid.
Referring to Figure 12, in conjunction with referring to Fig. 3, Fig. 5 to Figure 11, Figure 12 has shown the structure of having accomplished otp memory behind the step S17, and is as shown in the figure, and first hard mask layer 11, mask side wall 111 and 112 are all removed.
Then continue step S18, apply photoresist and remove metal silicide blocking area and the outer photoresist of bitline regions through photoetching process.
Referring to Figure 13, in conjunction with referring to Fig. 3, Fig. 5 to Figure 12, Figure 13 has shown the structure of having accomplished otp memory behind the step S18, and as shown in the figure, photoresist 14 covers on bitline regions BL and the metal silicide blocking area SABA.
Then continue step S19, carry out the dry etch process etching and remove 80% to 98% of prevention oxidated layer thickness.In the present embodiment, said etching technics is a dry etching, and etching gas comprises O
2And CF
4, etching has been removed and has been stoped 90% of oxidated layer thickness, and etching off is except the prevention oxide layer of 1440 dusts at once.
Then continue step S20, remove the photoresist on metal silicide blocking area and the bitline regions.
Referring to Figure 14, in conjunction with referring to Fig. 3, Fig. 5 to Figure 13, Figure 14 has shown the structure of having accomplished otp memory behind the step S20, and as shown in the figure, the prevention oxidated layer thickness on the metal silicide blocking area SABA is 1600 dusts, and all the other zones are 160 dusts.
Then continue step S21, carry out wet-etching technology and remove the prevention oxide layer in the silication metal electrode district, and form the metal silicide blocking layer, wherein, the etching liquid of wet-etching technology is hydrofluoric acid or hydrofluoric acid and ammonium fluoride NH
4The mixed liquor of F.In the present embodiment, etching liquid is a hydrofluoric acid.
Referring to Figure 15, in conjunction with referring to Fig. 3, Fig. 5 to Figure 14, Figure 15 has shown the structure of having accomplished otp memory behind the step S21, and as shown in the figure, metal silicide blocking area SABA has generated metal silicide blocking layer SAB.
Then continue step S22, carry out the deposited by pvd metal, wherein, said metal can be cobalt, titanium or nickel etc.In the present embodiment, said metal is a cobalt.
Referring to Figure 16, in conjunction with referring to Fig. 3, Fig. 5 to Figure 15, Figure 16 has shown the structure of having accomplished otp memory behind the step S22, and as shown in the figure, metal level 15 covers the otp memory surface.
Then continue step S23; Heat-treat to form silication metal electrode in the silication metal electrode district; Said silication metal electrode comprises cobalt silicide electrode, titanium silicide electrode and nickle silicide electrode; Metal is prone to and the silicon formation metal silicide that reacts, and metal does not react with silica, and therefore oxidized silicon region covered does not form silication metal electrode.In the present embodiment, said silication metal electrode is the cobalt silicide electrode.
Then continue step S24, remove unreacted metal.In the present embodiment, remove unreacted cobalt through SPM cleaning fluid (mixed liquor of sulfuric acid H2SO4 and oxydol H 2O2) and AMP cleaning fluid (mixed liquor of ammoniacal liquor NH4OH, oxydol H 2O2 and water H2O) cleaning fluid.
Referring to Figure 17, in conjunction with referring to Fig. 3, Fig. 5 to Figure 16, Figure 17 has shown the structure of having accomplished otp memory behind the step S24, and silication metal electrode district SAEA has silication metal electrode SAE, and other zones are that metal silicide blocking area SABA goes up no metal residual.
What need explanation is; The width negative correlation of the thickness of first hard mask layer 11 and second hard mask layer 13 and the electrode of bitline regions BL can be turned the width of the electrode of (or transferring greatly) bitline regions BL through the thickness of transferring big (or turning down) first hard mask layer 11 and second hard mask layer 13 down.
In sum; The method for manufacturing silication metal electrode of otp memory of the present invention deposition earlier stops oxide layer; Deposit first hard mask layer and second hard mask layer then; And on first hard mask layer, form bitline regions figure and mask side wall through photoetching and etching technics, and so etching forms the less bitline regions figure of characteristic size under the mask of first hard mask layer and mask side wall, and adopting photoresist afterwards is that the photoetching process of mask defines the bigger figure of other characteristic sizes; Thereby adapt to the ever-reduced demand of silicide metals trapping layer characteristic size, also adapt to the demand of otp memory miniaturization simultaneously.
Claims (9)
1. the method for manufacturing silication metal electrode of an otp memory; It carries out after having made first control gate, first floating boom, second floating boom and second control gate of arranging successively; This otp memory has metal silicide blocking area and silication metal electrode district; This silication metal electrode district comprises the bitline regions that is positioned between first floating boom and second floating boom, it is characterized in that, this method may further comprise the steps: a, deposition stop oxide layer; B, deposition first hard mask layer; C, apply photoresist and make the bitline regions figure by lithography, this bitline regions figure has the opening corresponding to said bitline regions, and this opening exposes said first hard mask layer; D, carry out etching technics and on first hard mask layer, form the bitline regions figure, this bitline regions figure has the opening corresponding to said bitline regions, and this opening exposes said prevention oxide layer; E, deposition second hard mask layer; F, etching second hard mask layer are to form the mask side wall on the bitline regions figure two side of first hard mask layer; G, under the covering of first hard mask layer and mask side wall, carry out etching technics, etching is removed bitline regions and is stoped 80% to 98% of oxidated layer thickness, to form the bitline regions figure on the oxide layer stoping; H, removal first hard mask layer and mask side wall; I, coating photoresist also pass through photoetching process and remove metal silicide blocking area and the outer photoresist of bitline regions; J, carry out etching technics to form the metal silicide blocking layer to stoping oxide layer; K, make silication metal electrode in the silication metal electrode district.
2. the method for manufacturing silication metal electrode of otp memory as claimed in claim 1 is characterized in that, in step a, this prevention thickness of oxide layer scope is 300 to 2000 dusts.
3. the method for manufacturing silication metal electrode of otp memory as claimed in claim 1 is characterized in that, this step j may further comprise the steps: j1, carry out the dry etch process etching and remove to stop 80% to 98% of oxidated layer thickness; Photoresist on j2, removal metal silicide blocking area and the bitline regions; J3, carry out wet-etching technology and remove the prevention oxide layer in the silication metal electrode district, and form the metal silicide blocking layer.
4. the method for manufacturing silication metal electrode of otp memory as claimed in claim 3 is characterized in that, in step j3, the etching liquid of wet-etching technology is a hydrofluoric acid, or the mixed liquor of hydrofluoric acid and ammonium fluoride.
5. the method for manufacturing silication metal electrode of otp memory as claimed in claim 1 is characterized in that, this first hard mask layer and second hard mask layer include silicon nitride.
6. the method for manufacturing silication metal electrode of otp memory as claimed in claim 5 is characterized in that, this first hard mask layer and second hard mask layer are all through plasma reinforced chemical vapour deposition technology or low-pressure chemical vapor deposition process deposition.
7. the method for manufacturing silication metal electrode of otp memory as claimed in claim 1; It is characterized in that; The thickness range of this first hard mask layer and second hard mask layer is 200 to 1800 dusts, the width negative correlation of the thickness of this first hard mask layer and second hard mask layer and the electrode of bitline regions.
8. the method for manufacturing silication metal electrode of otp memory as claimed in claim 1 is characterized in that, step k may further comprise the steps: k1, carry out the deposited by pvd metal; K2, heat-treat to form silication metal electrode in the silication metal electrode district; K3, removal unreacted metal.
9. the method for manufacturing silication metal electrode of otp memory as claimed in claim 8 is characterized in that, this metal comprises cobalt, titanium or nickel, and this silication metal electrode comprises cobalt silicide electrode, titanium silicide electrode or nickle silicide electrode.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102122642B (en) * | 2011-01-27 | 2015-12-02 | 上海华虹宏力半导体制造有限公司 | The formation method of OTP parts |
| CN102122641B (en) * | 2011-01-27 | 2015-02-25 | 上海华虹宏力半导体制造有限公司 | Method for forming one time programmable (OTP) device |
| CN103956339B (en) * | 2014-05-21 | 2016-11-09 | 上海华力微电子有限公司 | The manufacture method of disposal programmable device |
| CN104538362B (en) * | 2014-12-29 | 2019-02-05 | 上海华虹宏力半导体制造有限公司 | The structure and production method of OTP parts |
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| US5851882A (en) * | 1996-05-06 | 1998-12-22 | Micron Technology, Inc. | ZPROM manufacture and design and methods for forming thin structures using spacers as an etching mask |
| US7045425B2 (en) * | 2004-06-30 | 2006-05-16 | Texas Instruments Incorporated | Bird's beak-less or STI-less OTP EPROM |
| CN1941381A (en) * | 2005-09-28 | 2007-04-04 | 中芯国际集成电路制造(上海)有限公司 | Structure and method for disposable programmable memory for built-in EEPROM |
| CN101189729A (en) * | 2005-04-29 | 2008-05-28 | 德州仪器公司 | One time programmable ROM |
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2009
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|---|---|---|---|---|
| US5851882A (en) * | 1996-05-06 | 1998-12-22 | Micron Technology, Inc. | ZPROM manufacture and design and methods for forming thin structures using spacers as an etching mask |
| US7045425B2 (en) * | 2004-06-30 | 2006-05-16 | Texas Instruments Incorporated | Bird's beak-less or STI-less OTP EPROM |
| CN101189729A (en) * | 2005-04-29 | 2008-05-28 | 德州仪器公司 | One time programmable ROM |
| CN1941381A (en) * | 2005-09-28 | 2007-04-04 | 中芯国际集成电路制造(上海)有限公司 | Structure and method for disposable programmable memory for built-in EEPROM |
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