CN101593689A - The formation method and the double mosaic structure manufacture method of photoengraving pattern - Google Patents
The formation method and the double mosaic structure manufacture method of photoengraving pattern Download PDFInfo
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Abstract
The invention provides a kind of formation method of photoengraving pattern, comprising: the semiconductor-based end is provided, and described substrate comprises low temperature oxide layer at least; Passivation Treatment is carried out on surface to described low temperature oxide layer; Spin coating photoresist on the low temperature oxide layer after the Passivation Treatment; Graphical described photoresist forms photoengraving pattern.The present invention also provides a kind of double mosaic structure manufacture method.The formation method of photoengraving pattern provided by the invention can solve low temperature oxide layer and react with photoresist in photoetching process, generates the problem of the difficult residue of removing, thereby improves the accuracy of photoengraving pattern, improves the uniformity of critical size.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of formation method of photoengraving pattern and a kind of double mosaic structure manufacture method.
Background technology
Along with very lagre scale integrated circuit (VLSIC) high integration and high performance demand are increased gradually, semiconductor technology is towards the technology node development of 65nm processing procedure, when component size is constantly dwindled, the metal interconnected also more difficult characteristic that satisfies low resistance and low electric capacity, incident is the requirement that the metal interconnect technology level is promoted.
Industry selects for use copper and advanced low-k materials as the solution that reduces interconnection resistance and capacitance delays (RC), because copper has characteristics such as easy diffusion, difficult etching, so introduced dual-damascene technics (DualDamascene).Publication number is that the patent application document of CN101079408A discloses a kind of double mosaic structure manufacture method, as shown in Figure 1, the substrate 100 that forms semiconductor device (not shown active area) is provided, on substrate 100, form the metal pattern layer 105 in dielectric layer 115 and the embedding medium layer 115, deposition-etch stops layer 110 on described dielectric layer 115, then at the cover layer 125 on dielectric layer 120 and the intermetallic dielectric layer 120 between plated metal on the described etching stop layer 110, spin coating photoresist on cover layer 125 then, exposure imaging and etching form through hole and groove, the etching stop layer of opening under the through hole by etching 110 exposes metal pattern layer 105, in the above-mentioned etching process, cover layer 125 on the intermetallic dielectric layer 120 also is etched away until exposing intermetallic dielectric layer 120, thereafter, fill the metal barrier successively, metal seed layer and metal interconnecting layer 135, thereby inlay interconnecting lead and interlayer stopple together, form dual-damascene structure as shown in Figure 1.
Above-mentioned double mosaic structure manufacture method is via-first technology (Via First), in the etching stop layer 110 that has deposited, intermetallic dielectric layer 120 and cover layer 125, etch through hole 123 as shown in Figures 2 and 3, adopt three layer process (tri-layer) to etch groove then.As shown in Figure 3, in through hole 123, fill bottom anti-reflection layer 127 (BARC, Bottom Anti-reflective Coating), deposit hard mask layer 129 and spin coating photoresist 131 thereon then, promptly form for three layers in so-called three layer process by photoresist layer 131, hard mask layer 129 and bottom anti-reflection layer 127.Usually by silica (SiO
2), siliceous oxide such as silicon oxynitride (SiON), silicon oxide carbide (SiOC) is as hard mask layer 129, organic polymer is as bottom anti-reflection layer 127.
Silica as hard mask layer adopts plasma-assisted chemical vapour deposition method (PECVD) manufacturing, and reacting gas is silane (SiH
4) and nitrous oxide (N
2O), consider that the organic polymer thermal endurance of bottom anti-reflection layer is relatively poor, the depositing temperature of silica requires to be lower than 250 ℃, so this hard mask layer also is low temperature oxide layer.But, as shown in Figure 7, under lower depositing temperature, contain a large amount of Si-H chemical bonds in the silica that deposition forms, as shown in Figure 8, the Si-H chemical bond easily is oxidized into Si-OH when low temperature oxide layer is exposed in the atmosphere, and Si-OH becomes low temperature oxide layer to have more moisture absorption, more seriously, Si-OH in photoetching process can and photoresist 131 reactions, generate residual polyalcohol 132 as shown in Figure 3, be very difficult to remove, influenced the accuracy of photoengraving pattern, thereby caused critical size (critical dimension, CD) deviation, the key size evenness of entire wafer is also relatively poor.
Same, in the technical process that other semiconductors are made, for example make polysilicon grating structure, also can run into the reaction of low temperature oxide layer and photoresist and generate residual polyalcohol, cause photoengraving pattern inaccurate, the problem that key size evenness is relatively poor.
Summary of the invention
The problem that the present invention solves provides a kind of formation method of photoengraving pattern, react with photoresist in photoetching process to solve low temperature oxide layer, generate the difficult residue of removing, influence the accuracy of photoengraving pattern, and then cause the problem of critical size etching deviation.
The present invention also provides a kind of double mosaic structure manufacture method, can avoid low temperature oxide layer and photoresist reaction in photoetching process, to guarantee the accuracy of photoengraving pattern, improves the uniformity of the critical size in the dual-damascene structure.
For addressing the above problem, the invention provides a kind of formation method of photoengraving pattern, comprising:
The semiconductor-based end is provided, and described substrate comprises low temperature oxide layer at least;
Passivation Treatment is carried out on surface to described low temperature oxide layer;
Spin coating photoresist on the low temperature oxide layer after the Passivation Treatment;
Graphical described photoresist forms photoengraving pattern.
Described Passivation Treatment adopts the surface of the plasma bombardment low temperature oxide layer of oxygen carrier.
Described oxygen carrier can be the combination of a kind of in nitrous oxide, oxygen, carbon monoxide, the carbon dioxide or at least two kinds.
Described Passivation Treatment adopts the surface of the plasma bombardment low temperature oxide layer of nitrous oxide, and the flow of described nitrous oxide is 3000sccm to 200000sccm.
Described Passivation Treatment adopts the surface of the plasma bombardment low temperature oxide layer of nitrous oxide, and the power that produces the driving source of described nitrous oxide plasma is 500W to 1000W.
Described Passivation Treatment adopts the surface of the plasma bombardment low temperature oxide layer of nitrous oxide, and the pressure of plasma cavity is 1T to 3T.
Described Passivation Treatment adopts the surface of the plasma bombardment low temperature oxide layer of nitrous oxide, and the processing time is 10s to 60s.
Original position or ex situ are carried out Passivation Treatment after the formation low temperature oxide layer.
Correspondingly, the invention provides a kind of double mosaic structure manufacture method, comprising:
The semiconductor-based end with device layer is provided, and described substrate surface comprises etching stop layer at least, is positioned at the dielectric layer on the described etching stop layer; In described dielectric layer, have groove or through hole; On described dielectric layer and in described groove or the through hole, have bottom anti-reflection layer, and described bottom anti-reflection layer is filled up groove or through hole at least; On the anti-emitting layer in described bottom, has low temperature oxide layer;
Described low temperature oxide layer is carried out Passivation Treatment;
On the low temperature oxide layer after the Passivation Treatment, form photoengraving pattern, and have at least a photoengraving pattern to be positioned at described groove or relevant position, through hole top;
Described photoengraving pattern is transferred in the described dielectric layer, formed dual damascene opening;
In described dual damascene opening, fill metal level.
Described Passivation Treatment adopts the surface of the plasma bombardment low temperature oxide layer of oxygen carrier.
Compared with prior art, above technical scheme has the following advantages:
The formation method of described photoengraving pattern is carried out Passivation Treatment to it after forming low temperature oxide layer, promptly adopt N
2The plasma bombardment low temperature oxide laminar surface of oxygen carriers such as O, N
2The active oxygen ion of high energy makes the Si-H chemical bond scission of link in the low temperature oxide layer in the plasma of oxygen carriers such as O, and replacement hydrogen forms the higher Si-O chemical bond of bond energy, thereby eliminate the unsettled Si-H chemical bond of low temperature oxide laminar surface, become Si-OH by eremacausis when avoiding being exposed to atmosphere, therefore can avoid in follow-up photoetching process, low temperature oxide layer and photoresist react and the formation residual polyalcohol, thereby improve the accuracy of etching, improve the uniformity of critical size.
Described double mosaic structure manufacture method is carried out Passivation Treatment to low temperature oxide layer when forming dual damascene opening, adopt N
2Active oxygen ion in the plasma of oxygen carriers such as O, make surperficial unsettled Si-H be transformed into the Si-O key, avoid in photoetching process, reacting, guarantee the accuracy of photoengraving pattern, can improve the uniformity of the critical size in the dual-damascene structure with photoresist.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing in proportion, focus on illustrating purport of the present invention.
Fig. 1 is the profile of the disclosed a kind of dual-damascene structure of prior art;
Fig. 2 and Fig. 3 are the schematic diagrames of dual-damascene structure in the shop drawings 1;
Fig. 4 to Fig. 6 is the schematic diagram of the formation method of photoengraving pattern in the embodiment of the invention;
Fig. 7 and Fig. 8 are the schematic diagrames of low temperature oxide layer surface state;
Fig. 9 to Figure 16 is the schematic diagram of dual-damascene structure formation method in the embodiment of the invention one;
Figure 17 to Figure 23 is the schematic diagram of dual-damascene structure formation method in the embodiment of the invention two.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, when the embodiment of the invention is described in detail in detail; for ease of explanation; the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Fig. 4 to Fig. 6 is the schematic diagram of the formation method of photoengraving pattern of the present invention, as shown in Figure 4, provides the semiconductor-based end 300, has had the structure of semiconductor device in the described substrate 300; In described substrate 300, form low temperature oxide layer 310, this low temperature oxide layer 310 includes but not limited to the combination of a kind of in silica, silicon oxide carbide, the silicon oxynitride or at least two kinds, adopt the low temperature chemical vapor deposition manufactured, as an example, by plasma-assisted chemical vapour deposition method (PECVD), with silane (SiH
4) and nitrous oxide (N
2O) be reactant, when depositing temperature is lower than 250 ℃, form the low-temperature oxidation silicon layer.
Then Passivation Treatment is carried out on the surface of described low temperature oxide layer 310.Can adopt the plasma of oxygen carrier that the surface of low temperature oxide layer 310 is bombarded, described oxygen carrier includes but not limited to the combination of a kind of in nitrous oxide, oxygen, carbon monoxide, the carbon dioxide or at least two kinds; Described Passivation Treatment can be carried out in low temperature oxide layer deposition back original position, also can ex situ carry out in other Special Equipments.As an example, after deposition forms the low-temperature oxidation silicon layer, in same equipment, adopt nitrous oxide plasma bombardment low-temperature oxidation silicon surface, the power in plasma excitation source is 500W, the flow of nitrous oxide is 1600sccm, the pressure of plasma cavity is 1.5T, and the processing time is 15s.
As shown in Figure 5, on the low temperature oxide layer after the Passivation Treatment 310, adopt automatic double surface gluer rotary coating photoresist layer 320, aim at and exposure sources through sending into after the whirl coating oven dry.
As shown in Figure 6,, send into developing apparatus then photoresist layer 320 is developed, form photoengraving pattern behind the cleaning, drying the exposing substrate behind the spin coating photoresist.
Following examples are described in detail in conjunction with the formation method of double mosaic structure manufacture method to photoengraving pattern of the present invention.
Embodiment one
Fig. 9 to Figure 16 is the profile of the embodiment of the invention one.As shown in Figure 9, provide the substrate 100 with semiconductor device, have first metal interconnecting layer 105 on it, include but not limited to copper or aluminium, medium 115 is with the mutual isolated insulation of metal connecting line.On first metal interconnecting layer 105, form etching stop layer 110, overetch is to first metal interconnecting layer 105 of lower floor in order to the terminal point of determining etching technics and when avoiding its upper strata of etching material, simultaneously also in order to stop the upwards diffusion of metal in the metal interconnecting layer 105, described etching stop layer 110 includes but not limited to the combination of a kind of in silicon nitride, silicon oxynitride, carborundum, the nitrogen-doped silicon carbide or at least two kinds, and preferred etching stopping layer material is a nitrogen doped silicon carbide.Described etching stop layer 110 adopts the chemical vapour deposition technique manufacturing, preferably plasma-assisted chemical vapour deposition method (PECVD) or high-density plasma auxiliary chemical vapor deposition method (HDP-CVD) are 100 dust to 500 dusts according to device property and size design deposit thickness.
On described etching stop layer 110, form the just so-called intermetallic dielectric layer of dielectric layer 120 (Interlayer dielectric) then, in order to different metal level isolated insulations, usually adopt material than low-k, include but not limited to carbon doped silicon oxide, organic silicate glass (Organosilicateglass, OSG), fluorine silex glass (Fluorosilicate glass, FSG), phosphorosilicate glass (Phosphosilicateglass, PSG) a kind of or at least two kinds of combinations in.Described dielectric layer 120 adopts the chemical vapour deposition technique manufacturing, preferably plasma-assisted chemical vapour deposition method (PECVD) or high-density plasma auxiliary chemical vapor deposition method (HDP-CVD) are 500 dust to 3000 dusts according to device property and size design deposit thickness.
Then on described dielectric layer 120, form cover layer 125; in order to the less dielectric layer 120 of protection hardness; dielectric layer 120 is not destroyed by oxygen plasma in follow-up podzolic process; described cover layer 125 includes but not limited to the combination of a kind of in silicon nitride, silica, the carborundum or at least two kinds; this cover layer 125 adopts the chemical vapour deposition technique manufacturing, and thickness is 100 dust to 300 dusts.
In dielectric layer 120, form through hole 123 then as shown in figure 10.Be specially: the spin coating first photoresist layer 126 on described cover layer 125, exposure imaging forms through-hole pattern 123A, described through-hole pattern 123A is positioned at corresponding position, described first metal interconnecting layer, 105 tops, by cover layer 125, the dielectric layer 120 formation through holes 123 of etching corresponding to through-hole pattern, described through hole 123 ends in the etching stop layer 110 after passing cover layer 125, dielectric layer 120, and last ashing is also cleaned and removed the first photoresist layer 126.
Subsequently as shown in figure 11, on described cover layer 125, form bottom anti-reflection layer 127, and fill up through hole 123, described bottom anti-reflection layer 127 is in order to control reflection and standing wave, light reflects at underlying membrane when avoiding photoetching, and the unexposed photoresist that infringement closes on, control causes bad influence to live width.Bottom anti-reflection layer 127 forms for organic polymer spin coating baking back, and thickness is 50 dust to 20000 dusts.
On described bottom anti-reflection layer 127, form low temperature oxide layer 129 then, be equivalent to hard mask, be used to shift etching pattern, described low temperature oxide layer 129 includes but not limited to the combination of a kind of in silica, silicon oxide carbide, the silicon oxynitride or at least two kinds, and preferable material is a silica.Described low temperature oxide layer must adopt low temperature chemical vapor deposition method deposition, and this is because the processing that the organic polymer of the bottom anti-reflection layer 127 of lower floor can not bear high-temperature technology.Preferred technology is plasma-assisted chemical vapour deposition method (PECVD), and reactant is silane (SiH
4) and nitrous oxide (N
2O), be protection bottom anti-reflection layer 127, depositing temperature is controlled at below 250 ℃.But, the low temperature oxide layer 129 of cryogenic conditions deposit contains a large amount of Si-H chemical bonds, in the subsequent technique process, the Si-H chemical bond is easily become Si-OH by eremacausis when being exposed to atmosphere, and Si-OH becomes rete to have more moisture absorption, more seriously, can react with photoresist in photoetching process, photoresist is poisoned, therefore next need low temperature oxide layer 129 is carried out Passivation Treatment.
Described Passivation Treatment process is specially: after the deposition low temperature oxide layer 129, adopt the active oxygen carrier plasma of chemical property low temperature oxide layer 129 surfaces to be carried out the high power bombardment of certain hour, described oxygen carrier includes but not limited to the combination of a kind of in nitrous oxide, carbon monoxide, carbon dioxide and the oxygen or at least two kinds, and preferred oxygen carrier is the very high nitrous oxide of ionization ionization level.Described Passivation Treatment with the deposition low temperature oxide layer same device also can another the device in, for example, silane (SiH
4) and nitrous oxide (N
2O) after PECVD low temperature reaction deposition forms silica, directly in the deposition reaction chamber, adopt N
2O plasma bombardment cryogenic oxidation silicon film surface, preferred technological parameter is: N
2The O gas flow is 3000sccm to 200000sccm, and excitation of plasma power is 500W to 1000W, and reaction pressure is 1T to 3T, and the processing time is 10s to 60s; Above-mentioned Passivation Treatment and film deposition original position in same device is carried out, and helps that technology is integrated to prevent to pollute wafer simultaneously.
N
2The active oxygen ion of high energy makes Si-H chemical bond scission of link in the O plasma, and replaces the higher Si-O chemical bond of hydrogen formation bond energy, thereby eliminates the unsettled Si-H chemical bond of silicon oxide film laminar surface, is become Si-OH by eremacausis when avoiding being exposed to atmosphere.
The oxygen carrier that produces plasma also can adopt the higher and nontoxic oxygen cheaply of ionization ionization level, also can adopt relatively low carbon monoxide of ionization ionization level or carbon dioxide, but the carbon that carbon monoxide or carbon dioxide ionization go out can be combined into hydrocarbon with the hydrogen in the Si-H chemical bond, thereby accelerates to form the reaction speed of Si-O chemical bond.
Then as shown in figure 12, the spin coating second photoresist layer 131 on the low temperature oxide layer after the Passivation Treatment 129, exposure imaging forms channel patterns 132A, described channel patterns 132A is positioned at corresponding position, described through hole 123 tops, then as shown in figure 13, dry etching is transferred to low temperature oxide layer 129 with channel patterns 132A, as shown in figure 14, clean and remove the second photoresist layer 131, etch groove 132 according to projected depth, described groove 132 passes bottom anti-reflection layer 127, cover layer 125, end in the dielectric layer 120, and be connected with through hole 123, clean and remove bottom anti-reflection layer 127 and low temperature oxide layer 129, thereby the dual damascene opening 138 of formation groove 132 and through hole 123.
As shown in figure 15, etch away the remaining etching stop layer 110 in described through hole 123 bottoms, so that first metal interconnecting layer 105 below the etching stop layer 110 exposes, at last as shown in figure 16, plated metal barrier layer 133, metal seed layer 134 and second metal interconnecting layer 135 successively in dual damascene opening 138, and remove unnecessary metal, and grind full consumption and fall cover layer 125 by cmp.
Described dual-damascene structure manufacture method is after forming low temperature oxide layer, low temperature oxide layer is carried out Passivation Treatment, can avoid the low temperature oxide layer and the photoresist of low temperature depositing to react and the formation residual polyalcohol, thereby improve the accuracy of etching, improve the uniformity of critical size.
Among the above embodiment, the manufacture method of dual-damascene structure of the present invention adopts the technology of via-first, in following examples, describes photoengraving pattern formation method of the present invention in detail in conjunction with the manufacture method of the preferential dual-damascene structure of groove.
Embodiment two
Figure 17 to Figure 23 is the profile of the embodiment of the invention two.As shown in figure 17, provide a substrate 200 with semiconductor device, have first metal interconnecting layer 205 on it, include but not limited to copper or aluminium, medium 215 is with the mutual isolated insulation of metal connecting line.On first metal interconnecting layer 205, form etching stop layer 210, overetch is to first metal interconnecting layer 205 of lower floor in order to the terminal point of determining etching technics and when avoiding its upper strata of etching material, simultaneously also in order to stop the upwards diffusion of metal in the metal interconnecting layer 205, described etching stop layer 210 includes but not limited to the combination of a kind of in silicon nitride, silicon oxynitride, carborundum, the nitrogen-doped silicon carbide or at least two kinds, and preferred etching stopping layer material is a nitrogen doped silicon carbide.Described etching stop layer 210 adopts the chemical vapour deposition technique manufacturing, preferably plasma-assisted chemical vapour deposition method (PECVD) or high-density plasma auxiliary chemical vapor deposition method (HDP-CVD) are 100 dust to 500 dusts according to device property and size design deposit thickness.
On described etching stop layer 210, form dielectric layer 220 then, just so-called intermetallic dielectric layer (Interlayer dielectric), in order to different metal level isolated insulations, usually adopt material than low-k, include but not limited to carbon doped silicon oxide, organic silicate glass (Organosilicateglass, OSG), fluorine silex glass (Fluorosilicate glass, FSG), phosphorosilicate glass (Phosphosilicateglass, PSG) one or more combination in.Described dielectric layer 220 adopts the chemical vapour deposition technique manufacturing, preferably plasma-assisted chemical vapour deposition method (PECVD) or high-density plasma auxiliary chemical vapor deposition method (HDP-CVD) are 500 dust to 3000 dusts according to device property and size design deposit thickness.
Then on described dielectric layer 220, form cover layer 225; in order to the less dielectric layer 220 of protection hardness; dielectric layer 220 is not destroyed by oxygen plasma in follow-up podzolic process; described cover layer 225 includes but not limited to the combination of a kind of in silicon nitride, silica, the carborundum or at least two kinds; this cover layer 225 adopts the chemical vapour deposition technique manufacturing, and thickness is 100 dust to 300 dusts.
In dielectric layer 220, form groove 232 then as shown in figure 18.Be specially: the spin coating first photoresist layer 226 on described cover layer 225, exposure imaging forms channel patterns, described channel patterns is positioned at corresponding position, described first metal interconnecting layer, 205 tops, by cover layer 225, the dielectric layer 220 formation grooves 232 of etching corresponding to channel patterns, described groove 232 passes cover layer 225, end in the dielectric layer 220, last ashing is also cleaned and is removed the first photoresist layer 226.
Afterwards as shown in figure 19, on described cover layer 225, form bottom anti-reflection layer 227, and fill up groove 232, described bottom anti-reflection layer 227 is in order to control reflection and standing wave, light reflects at underlying membrane when avoiding photoetching, and the unexposed photoresist that infringement closes on, and control causes bad influence to live width.Bottom anti-reflection layer 227 forms for organic polymer spin coating baking back, and thickness is 50 dust to 20000 dusts.
On described bottom anti-reflection layer 227, form low temperature oxide layer 229 then, it is hard mask layer, be used for etching and shift pattern, described low temperature oxide layer 229 is a silicon-containing material, include but not limited to the combination of a kind of in silica, carborundum, the silicon oxynitride or at least two kinds, preferable material is a silica.Described low temperature oxide layer 229 must adopt low temperature chemical vapor deposition method deposition, and this is because the processing that the organic polymer of the bottom anti-reflection layer 227 of lower floor can not bear high-temperature technology.Preferred technology is plasma-assisted chemical vapour deposition method (PECVD), and reactant is silane (SiH
4) and nitrous oxide (N
2O), be protection bottom anti-reflection layer 227, depositing temperature is controlled at below 250 ℃.But, low temperature oxide layer 229 contains a large amount of Si-H chemical bonds, in the subsequent technique process, the Si-H chemical bond is easily become Si-OH by eremacausis when being exposed to atmosphere, and Si-OH becomes rete to have more moisture absorption, more seriously, can react with photoresist in photoetching process, photoresist is poisoned, therefore next need low temperature oxide layer 229 is carried out Passivation Treatment.
Described Passivation Treatment process is specially: after the deposition low temperature oxide layer 229, adopt the active oxygen carrier plasma of chemical property low temperature oxide layer 229 surfaces to be carried out the high power bombardment of certain hour, described oxygen carrier includes but not limited to the combination of a kind of in nitrous oxide, carbon monoxide, carbon dioxide and the oxygen or at least two kinds, and preferred oxygen carrier is the higher nitrous oxide of ionization ionization level.Described Passivation Treatment with the deposition low temperature oxide layer same device also can another the device in, for example, silane (SiH
4) and nitrous oxide (N
2O) after PECVD low temperature reaction deposition forms silica, directly in the deposition reaction chamber, adopt N
2O plasma bombardment silicon oxide film laminar surface, N
2The active oxygen ion of high energy makes Si-H chemical bond scission of link in the O plasma, and replaces the higher Si-O chemical bond of hydrogen formation bond energy, thereby eliminates the unsettled Si-H chemical bond of silicon oxide film laminar surface, is become Si-OH by eremacausis when avoiding being exposed to atmosphere.The technological parameter that plasma bombardment adopted is: N
2The O gas flow is 3000sccm to 200000sccm, and excitation of plasma power is 500W to 1000W, and reaction pressure is 1T to 3T, and the processing time is 10s to 60s; Preferably, N
2The O gas flow is 15000sccm, and this flow can obtain best N
2O ionization ionization level; Preferably, excitation of plasma power is 500W, can make N under this exciting power
2The abundant ionization of O gas and can at utmost avoid the damage of plasma to the low temperature oxide laminar surface; Preferably, reaction pressure is 1.8T, can guarantee to obtain the reaction environment of low molecular density and high mean free path under this reaction pressure; Processing time is 15s, and this processing time can fully be bombarded the low temperature oxide laminar surface and be avoided damage to surfacing.Above-mentioned Passivation Treatment and low temperature oxide are deposited upon in the same device and carry out, and help that technology is integrated to prevent to pollute wafer simultaneously.
Then as shown in figure 20, the spin coating second photoresist layer 231 on the low temperature oxide layer after the Passivation Treatment 229, exposure imaging forms through-hole pattern 223A, described through-hole pattern 223A is positioned at corresponding position, described groove 232 tops, then as shown in figure 21, dry etching is transferred to low temperature oxide layer 229 with through-hole pattern, clean and remove photoresist layer 231, etch through hole 223 according to projected depth, described through hole 223 passes bottom anti-reflection layer 227, cover layer 225 and dielectric layer 220, ends in the etching stop layer 210.
As shown in figure 22, clean and remove low temperature oxide layer 229, bottom anti-reflection layer 227, etch away the remaining etching stop layer 210 in described through hole 223 bottoms then, so that first metal interconnecting layer 205 below the etching stop layer 210 exposes, form the dual damascene opening 238 that groove 232 is connected with through hole 223
At last as shown in figure 23, plated metal barrier layer 233, metal seed layer 234 and second metal interconnecting layer 235 successively in dual damascene opening 238, and remove unnecessary metal by cmp, and grind full consumption and fall cover layer 225.
Embodiment one and embodiment two have described photoengraving pattern formation method of the present invention in conjunction with the via-first technology (via first) and the groove first process (trench first) of double mosaic structure manufacture method respectively; those skilled in that art can know by inference; the formation method of photoengraving pattern of the present invention also be applicable to dual-damascene structure self-registered technology (Self Aligned), make in the processing procedures such as technology of polysilicon gate, also in protection scope of the present invention.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (10)
1, a kind of formation method of photoengraving pattern is characterized in that, comprising:
The semiconductor-based end, be provided, comprise low temperature oxide layer in the described substrate at least;
Passivation Treatment is carried out on surface to described low temperature oxide layer;
Spin coating photoresist on the low temperature oxide layer after the Passivation Treatment;
Graphical described photoresist forms photoengraving pattern.
2, the formation method of photoengraving pattern according to claim 1 is characterized in that, described Passivation Treatment adopts the surface of the plasma bombardment low temperature oxide layer of oxygen carrier.
3, the formation method of photoengraving pattern according to claim 2 is characterized in that, described oxygen carrier is the combination of a kind of in nitrous oxide, oxygen, carbon monoxide, the carbon dioxide or at least two kinds.
4, the formation method of photoengraving pattern according to claim 1 and 2 is characterized in that, described Passivation Treatment adopts the surface of the plasma bombardment low temperature oxide layer of nitrous oxide, and the flow of described nitrous oxide is 3000sccm to 200000sccm.
5, the formation method of photoengraving pattern according to claim 1 and 2, it is characterized in that, described Passivation Treatment adopts the surface of the plasma bombardment low temperature oxide layer of nitrous oxide, and the power that produces the driving source of described nitrous oxide plasma is 500W to 1000W.
6, the formation method of photoengraving pattern according to claim 1 and 2 is characterized in that, described Passivation Treatment adopts the surface of the plasma bombardment low temperature oxide layer of nitrous oxide, and the pressure of plasma cavity is 1T to 3T.
7, the formation method of photoengraving pattern according to claim 1 and 2 is characterized in that, described Passivation Treatment adopts the surface of the plasma bombardment low temperature oxide layer of nitrous oxide, and the processing time is 10s to 60s.
According to the formation method of each described photoengraving pattern of claim 1 to 3, it is characterized in that 8, original position or ex situ are carried out Passivation Treatment after the formation low temperature oxide layer.
9, a kind of double mosaic structure manufacture method is characterized in that, comprising:
The semiconductor-based end with device layer, be provided, comprise etching stop layer in the described substrate at least, be positioned at the dielectric layer on the described etching stop layer; In described dielectric layer, have groove or through hole; On described dielectric layer and in described groove or the through hole, have bottom anti-reflection layer, and described bottom anti-reflection layer is filled up groove or through hole at least; On the anti-emitting layer in described bottom, has low temperature oxide layer;
Described low temperature oxide layer is carried out Passivation Treatment;
On the low temperature oxide layer after the Passivation Treatment, form photoengraving pattern, and have at least a photoengraving pattern to be positioned at described groove or relevant position, through hole top;
Described photoengraving pattern is transferred in the described dielectric layer, formed dual damascene opening;
In described dual damascene opening, fill metal level.
10, double mosaic structure manufacture method according to claim 9 is characterized in that, described Passivation Treatment adopts the surface of the plasma bombardment low temperature oxide layer of oxygen carrier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101136925A CN101593689B (en) | 2008-05-29 | 2008-05-29 | Photoetch pattern formation method and double mosaic structure manufacture method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101136925A CN101593689B (en) | 2008-05-29 | 2008-05-29 | Photoetch pattern formation method and double mosaic structure manufacture method |
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| Publication Number | Publication Date |
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| CN101593689A true CN101593689A (en) | 2009-12-02 |
| CN101593689B CN101593689B (en) | 2010-12-22 |
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| CN102097361A (en) * | 2009-12-15 | 2011-06-15 | 中芯国际集成电路制造(上海)有限公司 | Forming method of dual-damascene structure |
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| CN102097361A (en) * | 2009-12-15 | 2011-06-15 | 中芯国际集成电路制造(上海)有限公司 | Forming method of dual-damascene structure |
| CN102097361B (en) * | 2009-12-15 | 2013-09-11 | 中芯国际集成电路制造(上海)有限公司 | Forming method of dual-damascene structure |
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| CN102664143A (en) * | 2012-04-20 | 2012-09-12 | 上海华力微电子有限公司 | Method for manufacturing capacitor comprising multilayer metal, silicon oxide and metal |
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| CN102820221A (en) * | 2012-07-03 | 2012-12-12 | 上海华力微电子有限公司 | Formation method of low-temperature silicon dioxide film |
| CN102832119A (en) * | 2012-07-03 | 2012-12-19 | 上海华力微电子有限公司 | Method for forming low temperature silicon dioxide film |
| CN102916093A (en) * | 2012-08-31 | 2013-02-06 | 扬州中科半导体照明有限公司 | Method for depositing high insulating property SiO2 film with low-damage PECVD (Plasma Enhanced Chemical Vapor Deposition) |
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| CN103854962A (en) * | 2012-11-28 | 2014-06-11 | 中芯国际集成电路制造(上海)有限公司 | Cleaning method after wafer etching |
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| CN104155844A (en) * | 2013-05-14 | 2014-11-19 | 台湾积体电路制造股份有限公司 | Photomask with three states for forming multiple layer patterns with a single exposure |
| CN104157565A (en) * | 2013-05-14 | 2014-11-19 | 台湾积体电路制造股份有限公司 | Method to define multiple layer patterns with a single exposure by e-beam lithography |
| CN104155844B (en) * | 2013-05-14 | 2020-07-07 | 台湾积体电路制造股份有限公司 | Photomask having three states for forming multi-layer pattern using single exposure |
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| CN104425210B (en) * | 2013-08-20 | 2018-10-16 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
| CN104425210A (en) * | 2013-08-20 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN104979269A (en) * | 2014-04-03 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
| CN104162528A (en) * | 2014-07-21 | 2014-11-26 | 苏州凯枫瑞电子科技有限公司 | Spinning workshop dust removing system based on wind pressure detection and multi-point monitoring |
| CN106783535A (en) * | 2016-11-28 | 2017-05-31 | 武汉新芯集成电路制造有限公司 | The method and semiconductor structure of a kind of improvement PETEOS film defects |
| CN107331775A (en) * | 2017-07-10 | 2017-11-07 | 陕西师范大学 | A kind of perovskite solar cell of high-quality electron transfer layer and preparation method thereof |
| CN107331775B (en) * | 2017-07-10 | 2019-10-08 | 陕西师范大学 | A kind of perovskite solar cell and preparation method thereof of high quality electron transfer layer |
| CN112201570A (en) * | 2020-09-24 | 2021-01-08 | 上海华力集成电路制造有限公司 | Process method for reducing photoresist poisoning |
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