CN101587744B - Multi-level data redundancy method of large scale FLASH memory array - Google Patents
Multi-level data redundancy method of large scale FLASH memory array Download PDFInfo
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Abstract
The invention provides a multi-level data redundancy method of large scale FLASH memory array, which includes the steps of: dividing the storage cell of large scale FLASH memory array into three levels: page level, FLASH chip level and FLASH chip group level, according to divided levels as well as required fault-tolerant level, choosing different redundancy encodings for storing into reserved dataredundancy spacing in the large scale FLASH memory array; when error is occurred, using redundancy encoding instant correction in the data redundancy spacing; compared with the prior art, the method provided by the invention has the advantages that: against large scale FLASH array application, different redundancy policies are taken for different levels for greatly improving reliability of data storage, and parallel arithmetic capacity of hardware are fully utilized for greatly reducing IO performance reduction induced by adding data redundancy check bit and shortening time for reconstructingdamaged data, moreover systematical reliability and redundancy policy can be determined according to practical situation of user with flexible and convenient configuration for realizing purpose of th e invention.
Description
Technical field
The present invention relates to a kind of data reliable memory method of FLASH storer, particularly a kind of multi-level data redundancy method that is applicable to large scale FLASH memory array data reliable memory.
Background technology
Along with progress of science and technology, the FLASH storer progressively becomes the highest solid-state nonvolatile memory of the present ratio of performance to price.In some fields, such as in aerospace engineering, exist many tasks that might produce mass data at short notice, such as camera, various real time sensors or the like; Owing to limit with the mutual time window of ground receiving station, these data must store earlier waits for passback ground, meanwhile, because space environment very severe, several factors such as the big temperature difference, cosmic rays all might cause the damage of data or lose, and this has just proposed very high requirement to the capacity and the reliability of storer.
Generally speaking, because the application scale of FLASH storer is less, and applied environment is better, and therefore the reliability requirement for the FLASH storer is not very high.In order to reduce cost, the FLASH memory vendor does not guarantee that the FLASH chip internal storage area that dispatches from the factory is available fully, but exist a certain proportion of bad piece, these bad pieces are come out by producer's mark when dispatching from the factory, in use also might produce new bad piece, the bad piece of these new generations needs the user to manage voluntarily.Aspect reliability, producer generally provides the check code of the redundant space of some with the storage some in the FLASH memory inside.So utilize concurrency and pipelining to improve aspects such as access rate when the research of bad block management when existing research emphasis about FLASH storer and controller thereof is placed on small-scale application mostly and suitable check code or large-scale application, and the data reliable memory strategy during to large-scale application is paid close attention to not enough.
The Chinese patent publication number be CN101320592A patent disclosure a kind of high-capacity FLASH solid memory controller, solved the verification and the error correction problem of data in bad block management problem and the FLASH chip page or leaf, but do not related to for the data loss problem of damaging because of piece or the damage of FLASH chip causes.
For another example, the Li Chao of Xian Electronics Science and Technology University is in " high-speed high capacity FLASH design of memory systems " literary composition of the 36th curly hair table in March, 2007 " fire control radar technology ", each FLASH chip is carried out page interior cyclic check coding and deposits coding result in the page or leaf interior redundant area of reserving, simultaneously 16 FLASH chips of same group are carried out checksum coding and coding result deposited in same group the 17th FLASH chip, this data redundancy mode has been strengthened reliability of data storage to a certain extent, but owing to be parallel work-flow, so if having the piece of two and above FLASH relevant position to be damaged on the same group or when having two and above FLASHFLASH chip to be damaged, this scheme is just powerless.
Summary of the invention
The object of the present invention is to provide a kind of multi-level data redundancy method of large scale FLASH memory array, overcome the deficiencies in the prior art,, realize the highly reliable storage of data at extensive, the highly reliable application demand of FLASH storer.
Technical matters solved by the invention can realize by the following technical solutions:
A kind of multi-level data redundancy method of large scale FLASH memory array, it is characterized in that, the storage unit of large scale FLASH memory array is divided into page or leaf level, FLASH chip-scale, three levels of FLASH chipset level, selects different redundancy encodings to deposit in the data redundancy space of reserving in the large scale FLASH memory array according to level of being divided and required fault-tolerant grade; When mistake occurring, utilize the redundancy encoding immediate correction mistake in the data redundancy space.
In one embodiment of the invention, storage unit for page or leaf level in the large scale FLASH memory array, described redundancy encoding adopts Hamming (HAMMING) sign indicating number or RS (Reed-Solomon) sign indicating number, redundancy encoding deposits in the data redundancy space of reserving in the large scale FLASH memory array, when number of errors appears in the data in the page or leaf level storage unit, utilize redundancy encoding immediate correction mistake.
Further, the mistake that the data in page or leaf level storage unit occur exceeds the error correction scope, then utilizes the redundancy encoding error correction of FLASH chip-scale.
In one embodiment of the invention, storage unit for FLASH chip-scale in the large scale FLASH memory array, as one group of parallel work-flow, effectively storage space is the capacity of N-2 piece FLASH chip with N piece FLASH chip, and remaining FLASH chip capacity is as the data redundancy space; Data in every group of FLASH chip are produced two groups of incoherent parity check codes combine as redundancy encoding with the Reed-Solomon sign indicating number, described redundancy encoding is stored in respectively in the data redundancy space of every group of FLASH chip; When taking place smaller or equal to two FLASH chip-scale fault, can complete restore data by described redundancy encoding from all the other N-2 piece FLASH chips that still can operate as normal.
Further, the memory location of described redundancy encoding is distributed in each FLASH chip in every group of FLASH chip by certain strategy.
Further, according to the demand of reliability and system access speed, the FLASH number of chips that is used to store data in every group of FLASH chip can be greater than the N-2 piece to increase degree of parallelism and capacity.
In one embodiment of the invention, storage unit for FLASH chipset level in the large scale FLASH memory array, described redundancy encoding adopts carries out the parity check code that the odd even computing obtains with each bit in the FLASH chip of relevant position in each FLASH chipset, additionally increase a FLASH chipset as the data redundancy space, and described redundancy encoding is deposited in the FLASH chipset of extra increase; When the FLASH chipset of storage data takes place greater than two FLASH chips and even whole group FLASH chip damage, can utilize the complete restore data of FLASH chip of other FLASH chipset by described redundancy encoding.
In one embodiment of the invention, consider influence, the IO of the FLASH chipset of the check bit of storing described parity check code is independently controlled FLASH chipset readwrite performance.
Further, because the read-write of FLASH chipset of the check bit of the described parity check code of storage is more frequent, should suitably increase backup group when using in fairly large application and long-life.
In one embodiment of the invention, write fashionablely in data, should provide the address earlier, when data write buffer memory, read the data and the check code that will cover, when writing data, write the new check bit that three's computing is produced afterwards.
The multi-level data redundancy method of a kind of large scale FLASH memory array of the present invention, compared with prior art, at the large scale FLASH arrayed applications, take different redundancy strategies at different levels, greatly improved reliability of data storage, make full use of the concurrent operation ability of hardware, greatly having reduced the IO performance that adds the data redundancy check bit and cause descends, shortened the time cost that corrupt data is rebuild, and the reliability of system and redundancy strategy can be determined according to actual conditions by the user, flexible configuration, convenience realize purpose of the present invention.
Description of drawings
Fig. 1 is an overall plan block diagram of the present invention;
Fig. 2 is hierarchy at different levels of the present invention and data redundancy strategy synoptic diagram;
Fig. 3 is that page or leaf level data redundancy encoding design RS (255,249) encoding scheme data of the present invention are divided synoptic diagram;
Fig. 4 is page or leaf level data redundancy encoding design RS (255, a 249) scrambler synoptic diagram of the present invention;
Fig. 5 is a FLASH chipset level data redundancy encoding process synoptic diagram of the present invention;
Fig. 6 is a FLASH chip-scale data redundancy cataloged procedure synoptic diagram of the present invention.
Embodiment
For technological means, creation characteristic that the present invention is realized, reach purpose and effect is easy to understand, below in conjunction with concrete diagram, further set forth the present invention.
As shown in Figure 1, a kind of overall plan block diagram of large scale FLASH memory array, but whole large scale FLASH memory array adopts the high-performance FPGA control of flexible configuration, can take different schemes at the different demands of using.
If the grouping of data size be piece (Block) level or more than, then can be at FPGA exterior arrangement one block RAM as metadata cache.Before packet writes RAM, earlier its address is write.When packet writes RAM, the data of this address and the checking data of relevant position are read in RAM from the FLASH storage array, afterwards packet is write this address, computing meanwhile produces new checking data and writes verification FLASH chipset.
If the grouping of data size is page or leaf (Page) level, then need not the configuring external metadata cache, the RAM that utilizes FPGA inside to provide gets final product as buffer memory.To the operation of data and last similar, this situation is applicable to that the order of large-scale data writes continuously.This is owing to the read-write cell and the erase unit of FLASH storage array and does not match: the minimum unit of read-write is page or leaf, and the minimum unit of wiping is a piece.The temporary checking data of the buffer area that can open up a size this moment in FPGA be piece writes data corresponding verification FLASH chip again when writing the buffer zone of a full piece.
The multi-level data redundancy method of a kind of large scale FLASH memory array of the present invention, the storage unit of large scale FLASH memory array is divided into page or leaf level, FLASH chip-scale, three levels of FLASH chipset level, selects different redundancy encodings to deposit in the data redundancy space of reserving in the large scale FLASH memory array according to level of being divided and required fault-tolerant grade; When mistake occurring, utilize the redundancy encoding immediate correction mistake in the data redundancy space.
As shown in Figure 2, hierarchies at different levels of the present invention and data redundancy strategy progressively are described as follows to bottom from top layer: whole FLASH storage array is one group with N FLASH chip, and the quantity of group and the size of N are decided according to the demand of system scale.Each organizes shared data and control bus, at synchronization a group job can only be arranged, N FLASH chip parallel work-flow in the group, redundancy encoding adopts parity check code, be used for the data of FLASH chipset of parity checking of whole array and control interface by independent, can with other FLASH chipset parallel work-flow.When data need write storage array, the checking data that need read the former data of the address that these data will write and relevant position earlier produced new checking data to be used for computing, and concrete operations mode preamble is analyzed.
Each group has N piece FLASHFLASH chip in the FLASH storage array, and wherein the capacity of N-2 piece FLASH chip is used for storing data, and the capacity of two FLASH chips is used for the checking data of storage redundancy.Storage mode is divided into the impartial bar of size (least unit is a page or leaf) according to each FLASH chip of big young pathbreaker of input packet, data set is write wherein four FLASH chips, meanwhile calculate two groups of incoherent checking datas and write remaining two FLASH chip.The FLASH chip that checking data writes according to mode shown in Figure 2 by turns.The generation of two groups of checking datas adopts parity check code and Reed-Solomon sign indicating number as redundancy encoding respectively.If reliability requirement is lower, then each FLASH chipset can use above N-2 piece FLASH chip as the data storage core, can increase degree of parallelism like this and increase power system capacity simultaneously with the read or write speed that improves storage array.
The piece (Block) that each FLASHFLASH chip is not waited by quantity according to capacity is formed, and each piece is made up of 64 pages (Page), and each page is made up of the data storage area of 2048Byte and the redundant memory area of 64Byte.According to reliability and performance requirement, can adopt HAMMING code scheme or RS (Reed-Solomon) as redundancy encoding to the data of 2048Byte; During enforcement, at first the data of 2048Byte are divided into the piece of suitable size, then each piece are encoded, the redundant data region that the checking data of generation deposits 64Byte in gets final product.
Embodiment
Provide the principle that a concrete example further specifies the inventive method below.Wherein, the redundancy encoding of page or leaf level storage unit is taked the Reed-Solomon sign indicating number, and the redundancy encoding of FLASH chip-scale storage unit adopts parity check code to combine with the Reed-Solomon sign indicating number, and the redundancy encoding of FLASH chipset level storage unit adopts parity check code.Each group has 6 FLASH chips, and wherein the capacity of 4 FLASH chips is used to store data, and the capacity of all the other two FLASH chips is used for the data redundancy space as the storage checking data.Original data packet is for being unit with 4 pieces, and an external block RAM is as metadata cache and address command register.
As shown in Figure 3, Figure 4, FLASH storage array page or leaf level data redundancy encoding scheme can be corrected the error in data of 3 Byte, and redundancy encoding can adopt Hamming (HAMMING) sign indicating number or RS (Reed-Solomon) sign indicating number.
As shown in Figure 3, the data of 2048Byte are divided into one group of every 249Byte, totally 9 groups, wherein the 9th group is 56Byte, and not enough 249Byte all mends 0 or 1 and gets final product in calculating process.Every group of data will produce the redundancy check data of 6Byte after computing, amount to 54Byte, and the data redundancy space is 64Byte in the page or leaf, and will be enough fully; When number of errors appears in the data in the page or leaf level storage unit, utilize redundancy encoding immediate correction mistake.
Fig. 4 is RS (255,249) the scrambler synoptic diagram of FLASH storage array page or leaf level data redundancy encoding, and g is a RS coding generator polynomial coefficient.In preceding 249 clock period, switch SW 1 closure, switch SW 2 is closed downwards, and input is admitted to scrambler and carries out computing when directly exporting; In back 6 clock period, switch SW 1 disconnects, and switch SW 2 is upwards closed, output coder operation result, the i.e. remainder of Output Shift Register.So far, data are finished redundancy encodings at different levels, finally send into each FLASHFLASH chip and deposit.
The mistake that data in page or leaf level storage unit occur exceeds the error correction scope, then utilizes the redundancy encoding error correction of FLASH chip-scale.
As shown in Figure 5, FLASH storage array FLASH chip-scale data redundancy cataloged procedure synoptic diagram adopts parity check code to combine as redundancy encoding with the Reed-Solomon sign indicating number, and wherein module E is the parity calculation unit, mainly carries out XOR; Module F is a Reed-Solomon coding computing unit, and the coefficient g among the F is the generator polynomial coefficient of RS coding; Module G is to the data D0 that comes data and module E, F the checking data P1, the P2 that produce the respectively 6 FLASH chips putting into data FLASH chipset in the mode (as shown in Figure 2) of rotating after will encode after D3 carries out page or leaf level data redundancy encoding.
N piece FLASH chip is as one group of parallel work-flow, effectively storage space is the capacity of N-2 piece FLASH chip, remaining FLASH chip capacity is as the data redundancy space, in the present embodiment, each group has 6 FLASH chips, wherein the capacity of 4 FLASH chips is used to store data, and the capacity of all the other two FLASH chips is used for the data redundancy space as the storage checking data; Data in every group of FLASH chip are produced two groups of incoherent check codes as redundancy encoding, and described redundancy encoding is stored in respectively in the data redundancy space of every group of FLASH chip; When taking place smaller or equal to two FLASH chip-scale fault, can complete restore data by described redundancy encoding from all the other FLASH chips that still can operate as normal.
The memory location of described redundancy encoding is distributed in each FLASH chip in every group of FLASH chip by certain strategy.
According to the demand of reliability and system access speed, the FLASH number of chips that is used to store data in every group of FLASH chip can be greater than the N-2 piece to increase degree of parallelism and capacity.
As shown in Figure 6, FLASH storage array FLASH chipset level data redundancy encoding process synoptic diagram, adopt parity check code as redundancy encoding, wherein modules A is the parity calculation unit, and each bit in the FLASH chip of relevant position in each FLASH chipset is carried out the parity check code that the odd even computing obtains; B is external RAM; C is the whole module of Fig. 6 representative, i.e. FLASH on chip redundancy coding module; C
-1Be the contrary module of C, i.e. FLASH on chip redundancy decoder module.
Additionally increase a FLASH chipset as the data redundancy space, and described redundancy encoding is deposited in the FLASH chipset of extra increase; At new data D
New' be written into before the RAM, earlier it is wanted address stored to write address register among the RAM, afterwards at D
New' when writing with the stored legacy data D in this address
OldAnd corresponding old checking data P in the verification FLASH chipset
OldRead, through module C
-1Write RAM after the computing, next with new data D
New' through writing appointed positions behind the module C, meanwhile, three piece of data computings among the RAM obtain writing verification FLASH chipset behind the new checking data process module C, and so circulation is operated.
When the FLASH chipset of storage data takes place greater than two FLASH chips and even whole group FLASH chip damage, can utilize the complete restore data of FLASH chip of other FLASH chipset by described redundancy encoding.
Consider influence, the IO of the FLASH chipset of the check bit of storing described parity check code is independently controlled FLASH chipset readwrite performance; Because the read-write of FLASH chipset of the check bit of the described parity check code of storage is more frequent, should suitably increase backup group when using in fairly large application and long-life.
Write fashionablely in data, should provide the address earlier, when data write buffer memory, read the data and the check code that will cover, when writing data, write the new check bit that three's computing is produced afterwards.
More than show and described ultimate principle of the present invention and principal character and advantage of the present invention.The technician of the industry should understand; the present invention is not restricted to the described embodiments; that describes in the foregoing description and the instructions just illustrates principle of the present invention; without departing from the spirit and scope of the present invention; the present invention also has various changes and modifications; these changes and improvements all fall in the claimed scope of the invention, and the claimed scope of the present invention is defined by appending claims and equivalent thereof.
Claims (10)
1. the multi-level data redundancy method of a large scale FLASH memory array, it is characterized in that, the storage unit of large scale FLASH memory array is divided into the page or leaf level, the FLASH chip-scale, three levels of FLASH chipset level, described page or leaf level data adopt HAMMING code scheme or Reed-Solomon sign indicating number as redundancy encoding, FLASH chip-scale The data parity check code combines as redundancy encoding with the Reed-Solomon sign indicating number, FLASH chipset level data adopt parity check code as redundancy encoding, select different redundancy encodings to deposit in the data redundancy space of reserving in the large scale FLASH memory array according to level of being divided and required fault-tolerant grade; When mistake occurring, utilize the redundancy encoding immediate correction mistake in the data redundancy space.
2. multi-level data redundancy method as claimed in claim 1, it is characterized in that, storage unit for page or leaf level in the large scale FLASH memory array, described redundancy encoding adopts Hamming (HAMMING) sign indicating number or RS (Reed-Solomon) sign indicating number, redundancy encoding deposits in the data redundancy space of reserving in the large scale FLASH memory array, when number of errors appears in the data in the page or leaf level storage unit, utilize redundancy encoding immediate correction mistake.
3. multi-level data redundancy method as claimed in claim 2 is characterized in that, the mistake that the data in page or leaf level storage unit occur exceeds the error correction scope, then utilizes the redundancy encoding error correction of FLASH chip-scale.
4. multi-level data redundancy method as claimed in claim 1, it is characterized in that, storage unit for FLASH chip-scale in the large scale FLASH memory array, with N piece FLASH chip as one group of parallel work-flow, effectively storage space is the capacity of N-2 piece FLASH chip, and remaining FLASH chip capacity is as the data redundancy space; Data in every group of FLASH chip are produced two groups of incoherent parity check codes combine as redundancy encoding with the Reed-Solomon sign indicating number, described redundancy encoding is stored in respectively in the data redundancy space of every group of FLASH chip; When taking place smaller or equal to two FLASH chip-scale fault, can complete restore data by described redundancy encoding from all the other N-2 piece FLASH chips that still can operate as normal.
5. multi-level data redundancy method as claimed in claim 4 is characterized in that, the memory location of described redundancy encoding is distributed in each FLASH chip in every group of FLASH chip by certain strategy.
6. multi-level data redundancy method as claimed in claim 4 is characterized in that, according to the demand of reliability and system access speed, the FLASH number of chips that is used to store data in every group of FLASH chip can be greater than the N-2 piece to increase degree of parallelism and capacity.
7. multi-level data redundancy method as claimed in claim 1, it is characterized in that, storage unit for FLASH chipset level in the large scale FLASH memory array, described redundancy encoding adopts carries out the parity check code that the odd even computing obtains with each bit in the FLASH chip of relevant position in each FLASH chipset, additionally increase a FLASH chipset as the data redundancy space, and described redundancy encoding is deposited in the FLASH chipset of extra increase; When the FLASH chipset of storage data takes place greater than two FLASH chips and even whole group FLASH chip damage, can utilize the complete restore data of FLASH chip of other FLASH chipset by described redundancy encoding.
8. multi-level data redundancy method as claimed in claim 7 is characterized in that, considers the influence to FLASH chipset readwrite performance, and the IO of the FLASH chipset of the check bit of storing described parity check code is independently controlled.
9. multi-level data redundancy method as claimed in claim 8 is characterized in that, because the read-write of FLASH chipset of the check bit of the described parity check code of storage is more frequent, should suitably increase backup group when using in fairly large application and long-life.
10. multi-level data redundancy method as claimed in claim 7, it is characterized in that, write fashionablely in data, should provide the address earlier, when data write buffer memory, read the data and the check code that will cover, when writing data, write the new check bit that three's computing is produced afterwards.
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| CN102944248A (en) * | 2012-10-30 | 2013-02-27 | 埃泰克汽车电子(芜湖)有限公司 | Expanding method of mileage totalized by automobile instruments |
| CN103218271B (en) * | 2013-04-18 | 2015-09-09 | 华为技术有限公司 | A kind of data error-correcting method and device |
| CN109683803B (en) * | 2017-10-19 | 2021-07-13 | 中兴通讯股份有限公司 | Data processing method and device |
| CN110265074B (en) * | 2018-03-12 | 2021-03-30 | 上海磁宇信息科技有限公司 | Hierarchical multiple redundancy magnetic random access memory and operation method thereof |
| CN110837345A (en) * | 2019-11-08 | 2020-02-25 | 杭州华澜微电子股份有限公司 | Bad block table storage method and device |
| CN113157490B (en) * | 2021-04-01 | 2023-12-26 | 深圳市纽创信安科技开发有限公司 | Flash memory embedded in chip and memory control method |
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