CN101583244B - Method for manufacturing circuit board - Google Patents
Method for manufacturing circuit board Download PDFInfo
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- CN101583244B CN101583244B CN2008100995368A CN200810099536A CN101583244B CN 101583244 B CN101583244 B CN 101583244B CN 2008100995368 A CN2008100995368 A CN 2008100995368A CN 200810099536 A CN200810099536 A CN 200810099536A CN 101583244 B CN101583244 B CN 101583244B
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- dielectric layer
- patterning conductor
- conductor layer
- thermoplasticity
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- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention relates to a method for manufacturing a circuit board, which comprises the following steps: firstly, providing a thermoplastic dielectric layer; then, forming a patterned conductor layeron two opposite surfaces of the thermoplastic dielectric layer; and finally, thermally pressing the patterned conductor layer into the thermoplastic dielectric layer.
Description
Technical field
The present invention relates to a kind of manufacture method of wiring board, and be particularly related to a kind of manufacture method that can reduce processing step and improve the wiring board of line density.
Background technology
In recent years, along with making rapid progress of electronic technology, coming out one after another of high-tech electronic industry makes electronic product more humane, with better function constantly weed out the old and bring forth the new, and towards light, thin, short, little trend design.In these electronic products, can dispose wiring board usually with conducting wire.
For the wiring board of generally knowing, its manufacture method is normally prior to being to form required line pattern on the substrate of material with thermosetting (thermoset) dielectric material.Then, on substrate, form second layer thermosetting dielectric material.Then, in second layer thermosetting dielectric material, form opening.Then, on second layer thermosetting dielectric material, form another line pattern, and in opening, form conductive hole (conductive via) so that two line patterns are connected.Afterwards, the demand of looking repeats above-mentioned steps, with line pattern and the conductive hole that forms other.
Yet, often need more processing step with the formed wiring board of said method, and have lower line density.
Summary of the invention
In view of this, purpose of the present invention is exactly that a kind of manufacture method of wiring board is being provided, and can reduce processing step and improve line density.
The present invention proposes a kind of manufacture method of wiring board, and the method is that first thermoplasticity (thermoplastic) dielectric layer is provided earlier.This first thermoplasticity dielectric layer has first surface and with respect to the second surface of first surface.Then, on first surface, form first patterning conductor layer, and on second surface, form second patterning conductor layer.Afterwards, with first patterning conductor layer and the second patterning conductor layer hot pressing (thermal compression) to the first thermoplasticity dielectric layer.
According to the manufacture method of the described wiring board of the embodiment of the invention, the material of the first above-mentioned thermoplasticity dielectric layer for example is Polyetherimide or polyimides.
According to the manufacture method of the described wiring board of the embodiment of the invention, the first above-mentioned patterning conductor layer and the formation method of second patterning conductor layer for example are addition process (additive process).
Manufacture method according to the described wiring board of the embodiment of the invention, above-mentioned after the first thermoplasticity dielectric layer is provided and before in first patterning conductor layer and second patterning conductor layer hot pressing to the first thermoplasticity dielectric layer, can also be prior to forming the conductor bores post on the first surface.Then, in conductor bores post hot pressing to the first thermoplasticity dielectric layer, and with after in first patterning conductor layer and second patterning conductor layer hot pressing to the first thermoplasticity dielectric layer, first patterning conductor layer is connected with the conductor bores post at the same time, and second patterning conductor layer is connected with the conductor bores post.
According to the manufacture method of the described wiring board of the embodiment of the invention, above-mentioned in first patterning conductor layer and second patterning conductor layer hot pressing to the first thermoplasticity dielectric layer after, can also in the first thermoplasticity dielectric layer, form through hole.
Manufacture method according to the described wiring board of the embodiment of the invention, above-mentioned in first patterning conductor layer and second patterning conductor layer hot pressing to the first thermoplasticity dielectric layer after, can also on first surface, form the second thermoplasticity dielectric layer, and on second surface, form the 3rd thermoplasticity dielectric layer.Then, on the second thermoplasticity dielectric layer, form the 3rd patterning conductor layer, and on the 3rd thermoplasticity dielectric layer, form the 4th patterning conductor layer.Afterwards, with the 3rd patterning conductor layer and the 4th patterning conductor layer respectively in hot pressing to the second thermoplasticity dielectric layer with the 3rd thermoplasticity dielectric layer in.
The present invention adopts the thermoplasticity dielectric material to be used as the circuit that mode that dielectric layer in the wiring board and employing increase layer forms multilayer, therefore can produce to have higher line direction density wiring board, and have higher Aligning degree between each layer line road of wiring board.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A to Fig. 1 E is the manufacturing process profile according to the circuit version that one embodiment of the invention illustrated.
Description of reference numerals
200,216,218: the thermoplasticity dielectric layer
202,204: the surface
206,220,228: the conductor bores post
208,210,224,230: patterning conductor layer
212,214,226,232: through hole
Embodiment
Figure 1A to Fig. 1 E is the manufacturing process profile according to the circuit version that another embodiment of the present invention illustrated.At first, please refer to Figure 1A, thermoplasticity dielectric layer 200 is provided, its material for example is Polyetherimide or polyimides.Thermoplasticity dielectric layer 200 has surface 202 and with respect to 202 surface 204, surface.Then, optionally on surface 202, form conductor bores post 206.The material of conductor bores post 206 for example is a copper, and its formation method for example is an addition process.In detail, the formation method of conductor bores post 206 for example is prior to forming patterning photoresist layer on the surface 202.This patterning photoresist layer has the opening that exposes part surface 202.Then, copper is plated in the above-mentioned opening.Afterwards, remove patterning photoresist layer and form conductor bores post 206.
Therefore then, please refer to Figure 1B,, carry out heat pressing process because thermoplasticity dielectric layer 200 has the characteristic of heating after-tack, with 206 hot pressing of conductor bores post to the thermoplasticity dielectric layer 200 with usefulness as conductive hole.Then, in forming patterning conductor layer 208 on the surface 202 and form patterning conductor layer 210 on surface 204, some of patterning conductor layer 208 are connected with conductor bores post 206.Patterning conductor layer 208 for example is a copper with the material of patterning conductor layer 210, and its formation method for example is an addition process.
Then, please refer to Fig. 1 C, carry out heat pressing process, simultaneously with patterning conductor layer 208 and patterning conductor layer 210 hot pressing to dielectric layer 200, and make patterning conductor layer 210 be connected, in thermoplasticity dielectric layer 200, to form required line pattern with conductor bores post 206.
Then, please refer to Fig. 1 D, with patterning conductor layer 208 with after patterning conductor layer 210 hot pressing are to thermoplasticity dielectric layer 200, can also optionally form through hole 212 and through hole 214 in dielectric layer 200, wherein through hole 214 can be in order to be connected patterning conductor layer 208 partly with the patterning conductor layer 210 of part.Through hole 212 for example is that first mode with laser drill or machine drilling forms opening in thermoplasticity dielectric layer 200 with the formation method of through hole 214.Then, carry out electroplating technology, copper is plated in the above-mentioned opening.
Afterwards, please refer to Fig. 1 E, on the surface 202 of thermoplasticity dielectric layer 200, form thermoplasticity dielectric layer 216, and on the surface 204 of thermoplasticity dielectric layer 200, form thermoplasticity dielectric layer 218.The material of thermoplasticity dielectric layer 216,218 is identical with thermoplasticity dielectric layer 200, in this not narration separately.Then, carry out the described step of Figure 1A to Fig. 1 D, in thermoplasticity dielectric layer 216, form conductor bores post 220, patterning conductor layer 224 and through hole 226, and in thermoplasticity dielectric layer 218, form conductor bores post 228, patterning conductor layer 230 and through hole 232.Similarly, if necessary, can repeatedly repeat the described step of Figure 1A to Fig. 1 D, to produce required wiring board.
Owing in above-mentioned steps, all be formed with patterning conductor layer on two surfaces of thermoplasticity dielectric layer 200, that is to say and in same processing step, can make two layer pattern line layers, therefore can reach the purpose of simplifying technology.In addition, in the present embodiment, after forming the ground floor circuit in the thermoplasticity dielectric layer 200, in thermoplasticity dielectric layer 216,218, form second layer circuit and the 3rd layer line road again, therefore can make between each layer line road to have higher Aligning degree.Moreover, when forming second layer circuit or the 3rd layer line road, the conductor bores post can be formed directly into patterning conductor layer directly over, therefore can improve the line density in the wiring board effectively.
In sum, the present invention utilizes the thermoplasticity dielectric material as the dielectric layer in the wiring board, therefore can utilize the mode of hot pressing that circuit is formed in the dielectric layer, and utilize the mode that increases layer to form the circuit of multilayer, make formed wiring board can have higher line density, and can have higher Aligning degree between each layer line road.
Though the present invention discloses as above with embodiment; right its is not in order to limit the present invention; any person of ordinary skill in the field without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when looking being as the criterion that claim of the present invention defines.
Claims (5)
1. the manufacture method of a wiring board comprises:
The first thermoplasticity dielectric layer is provided, and this first thermoplasticity dielectric layer has first surface and with respect to the second surface of this first surface;
On this first surface, form the conductor bores post;
With this conductor bores post hot pressing to this first thermoplasticity dielectric layer;
On this first surface, form first patterning conductor layer, and on this second surface, form second patterning conductor layer; And
This first patterning conductor layer and this second patterning conductor layer hot pressing to this first thermoplasticity dielectric layer, are made this first patterning conductor layer be connected with this conductor bores post, and this second patterning conductor layer is connected with this conductor bores post.
2. the manufacture method of wiring board as claimed in claim 1, wherein the material of this first thermoplasticity dielectric layer comprises Polyetherimide or polyimides.
3. the manufacture method of wiring board as claimed in claim 1, wherein the formation method of this first patterning conductor layer and this second patterning conductor layer comprises addition process.
4. the manufacture method of wiring board as claimed in claim 1 wherein with after this first patterning conductor layer and this second patterning conductor layer hot pressing are to this first thermoplasticity dielectric layer, also is included in this first thermoplasticity dielectric layer and forms through hole.
5. the manufacture method of wiring board as claimed in claim 1 wherein with after this first patterning conductor layer and this second patterning conductor layer hot pressing are to this first thermoplasticity dielectric layer, also comprises:
On this first surface, form the second thermoplasticity dielectric layer, and on this second surface, form the 3rd thermoplasticity dielectric layer;
On this second thermoplasticity dielectric layer, form the 3rd patterning conductor layer, and on the 3rd thermoplasticity dielectric layer, form the 4th patterning conductor layer; And
With the 3rd patterning conductor layer and the 4th patterning conductor layer respectively hot pressing to this second thermoplasticity dielectric layer with the 3rd thermoplasticity dielectric layer in.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100995368A CN101583244B (en) | 2008-05-13 | 2008-05-13 | Method for manufacturing circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100995368A CN101583244B (en) | 2008-05-13 | 2008-05-13 | Method for manufacturing circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101583244A CN101583244A (en) | 2009-11-18 |
| CN101583244B true CN101583244B (en) | 2011-11-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008100995368A Expired - Fee Related CN101583244B (en) | 2008-05-13 | 2008-05-13 | Method for manufacturing circuit board |
Country Status (1)
| Country | Link |
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| CN (1) | CN101583244B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1371240A (en) * | 2001-02-23 | 2002-09-25 | 华泰电子股份有限公司 | Manufacture of multilayer high-density base board |
| CN1532853A (en) * | 2003-03-24 | 2004-09-29 | 阿尔卑斯电气株式会社 | Variable resistor |
| CN101081903A (en) * | 2006-05-30 | 2007-12-05 | 日本油脂公司 | Prepreg and conductive layer-laminated substrate for printed wiring board |
| CN101112140A (en) * | 2005-10-20 | 2008-01-23 | 松下电器产业株式会社 | Multilayer printed wiring board and its manufacturing method |
| CN101151304A (en) * | 2005-04-08 | 2008-03-26 | 三井化学株式会社 | Polyimide film, polyimide metal laminate using the same and method for manufacturing the same |
-
2008
- 2008-05-13 CN CN2008100995368A patent/CN101583244B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1371240A (en) * | 2001-02-23 | 2002-09-25 | 华泰电子股份有限公司 | Manufacture of multilayer high-density base board |
| CN1532853A (en) * | 2003-03-24 | 2004-09-29 | 阿尔卑斯电气株式会社 | Variable resistor |
| CN101151304A (en) * | 2005-04-08 | 2008-03-26 | 三井化学株式会社 | Polyimide film, polyimide metal laminate using the same and method for manufacturing the same |
| CN101112140A (en) * | 2005-10-20 | 2008-01-23 | 松下电器产业株式会社 | Multilayer printed wiring board and its manufacturing method |
| CN101081903A (en) * | 2006-05-30 | 2007-12-05 | 日本油脂公司 | Prepreg and conductive layer-laminated substrate for printed wiring board |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101583244A (en) | 2009-11-18 |
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Granted publication date: 20111109 Termination date: 20120513 |