CN101582823B - Communicated method, communication system and communication routing device based on SPI bus - Google Patents
Communicated method, communication system and communication routing device based on SPI bus Download PDFInfo
- Publication number
- CN101582823B CN101582823B CN200810067210A CN200810067210A CN101582823B CN 101582823 B CN101582823 B CN 101582823B CN 200810067210 A CN200810067210 A CN 200810067210A CN 200810067210 A CN200810067210 A CN 200810067210A CN 101582823 B CN101582823 B CN 101582823B
- Authority
- CN
- China
- Prior art keywords
- clock
- comparator
- slave unit
- main equipment
- instruction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Small-Scale Networks (AREA)
Abstract
The invention discloses a communication method based on an SPI bus, comprising the following steps: providing selection signals of slave equipment through a data line of main equipment; determining the selected slave equipment according to the selection signals; carrying out accessing operation on the selected slave equipment through the main equipment; providing selection signals of a controlled electric unit through the data line of the main equipment; selecting the controlled electric unit according to the selection signals, and generating an open/close control command of the controlled electric unit; sending the control command to the controlled electric unit to control actions of the controlled electric unit. The invention also discloses a communication system based the on the SPI busand a communication routing device used for the communication system. SPI main equipment provides the selection signals through the data line, and determines a selected operation object according to treatment of the signals, therefore, the accessing operation of the main equipment on the slave equipment can be realized only needing the SPI bus of 3 line or 4 line and without arranging more pins on a host end to descend any other control signals.
Description
[technical field]
The present invention relates to the total line traffic control of SPI (serial peripheral interface, Serial Peripheral Interface), be specifically related to a kind of means of communication and communication system based on spi bus.
[background technology]
The spi bus system is the synchronous serial Peripheral Interface, is a kind of common used in industry STD bus, can make main frame and various ancillary equipment carry out information exchange with serial mode through it.For example; The a plurality of probes of the general outfit of the compuscan of medical field; In order to identify probe, can be equipped with the nonvolatile storage or the logical device of the information such as ID sign indicating number that are used to store probe for each probe, with these memory devices as slave unit; The compuscan main frame can conduct interviews obtaining the ID sign indicating number through spi bus, and main frame also can conduct interviews through spi bus to the control of equipment such as power supply on system's probe plate and relay.Spi bus comprises data wire, clock cable and chip selection signal line, and wherein data wire can be one, also can be two, so spi bus divides two types on 4 lines and 3 lines.4 line spi bus are by chip selection signal line SS_n; Serial clock signal line Sclk; The master goes out from going into data wire MOSI (Master Output Slave Input) and master to go into from going out data wire MISO (Master InputSlave Output) to constitute, and bus timing is shown in Fig. 1 a.3 line spi bus then comprise chip selection signal line SS_n, serial clock signal line Sclk and serial data signal line Sdata, and bus timing is shown in Fig. 1 b.Wherein, Sdata is two-way pin, and the data transmission stage is an output pin, and the Data Receiving stage is an input pin, is equivalent to the master in the 4 line spi bus from going into data wire MOSI to go into to unite two into one from going out data wire MISO with main.
Realize the communication of main frame and a plurality of SPI slave units, for example in the application of compuscan, 4 kinds of technical schemes are arranged traditionally, the principle of scheme 1 to scheme 4 is please consulted Fig. 2 to Fig. 5 respectively.As shown in Figure 2; Scheme 1 is the standard means of communication of many SPI equipment; The public clock line SCLK of each SPI slave unit, data wire MOSI and MISO; Each SPI slave unit all has independently chip selection signal line SS_n, and the SPI main equipment is changed to the sheet choosing of a SPI slave unit effectively at every turn, operates and visit this equipment.In addition, for each probe, main frame also needs descending some signals, is used for the power supply of direct control storage or logical device and relay switch of emission path or the like.As shown in Figure 3, scheme 2 has increased logical device (like CPLD, CPLD) on the probe plate; The spi bus main equipment is the CS chip selection signal CS_0～CS_k through coding of a plurality of bit through descending bit wide; Select different spi bus slave units, behind the selected equipment, the spi bus of spi bus main equipment is through behind the CPLD; Appear at the slave unit end, and then operation and access slave.As shown in Figure 4, scheme 3 is on the basis of scheme 2, and power supply that main frame is descending and relay control signal are routed on the corresponding probe by the CS signal controlling.As shown in Figure 5; In the scheme 4; Logical device on the probe plate also can be used as a SPI equipment; Main frame can no longer descending power supply and the control signal of relay like this, but after using the CS signal to choose probe CPLD as slave unit, accomplishes the control of relay on control of probe power supply and the probe plate through spi bus.
In the such scheme, the drawback of scheme 1 and scheme 2 is obvious, because the communication pin of main frame and a plurality of probes is a lot; Take the pin resource of system host end in a large number; If increase probe during upgrading, needing increases more pin, might cause the printed circuit board correcting of main frame.Though scheme 3 has been practiced thrift the number of pins of host side greatly with scheme 4 relative schemes 1 and scheme 2, but when the probe dilatation, also need increase the CS signal at least, therefore needed number of pins is still more, still has drawback in compatible and expandability.
[summary of the invention]
Main purpose of the present invention solves the problems of the prior art exactly, and a kind of means of communication and communication system based on spi bus is provided, and can effectively practice thrift the number of pins of communication system host side.
Another object of the present invention is to solve the problems of the prior art, and a kind of communication route device that is used for this communication system is provided.
For realizing above-mentioned purpose, the present invention provides a kind of means of communication based on spi bus, may further comprise the steps:
A1, the selection signal of slave unit is provided through the main equipment data wire;
B1, according to selecting signal to confirm selected slave unit;
C1, main equipment are to the operation that conducts interviews of selected slave unit.
Said steps A 1 comprises following substep:
A11, judge whether the signal condition of main equipment chip selection signal line jumps to effective status, if then get into next step;
A12, when saltus step takes place, pick up counting, receive data from the main equipment data wire simultaneously, the data that timing is received till the official hour are as selecting signal;
Said step B1 comprises following substep:
B11, preestablish the visit selection instruction of each slave unit;
B12, judgement select the visit selection instruction of signal and which slave unit to be complementary, and visit selection instruction and the slave unit of selecting signal to be complementary are confirmed as selected slave unit.
Further comprising the steps of in step C1 carries out: whether the signal condition of judging main equipment chip selection signal line jumps to disarmed state, if then stop accessing operation, and with the timing zero clearing.
Further comprising the steps of:
A2, the selection signal of controlled electric unit is provided through the main equipment data wire;
B2, according to selecting the selected controlled electric unit of signal, and generate the ON/OFF control command of controlled electric unit;
C2, control command is sent to controlled electric unit, control its action.
Said steps A 2 comprises following substep:
A21, judge whether the signal condition of main equipment chip selection signal line jumps to effective status, if then get into next step;
A22, when saltus step takes place, pick up counting, receive data from data wire simultaneously, the data that timing is received till the official hour are as selecting signal;
Said step B2 comprises following substep:
B21, preestablish the control selection instruction of each controlled electric unit;
B22, judgement select the control selection instruction of signal and which controlled electric unit to be complementary, and control selection instruction and the electric unit of selecting signal to be complementary are confirmed as selected electric unit;
B25, generate the ON/OFF control command according to control signal.
For realizing above-mentioned purpose; The present invention also provides a kind of communication system based on spi bus; Comprise spi bus main equipment and a plurality of spi bus slave unit; Also comprise the communication routing apparatus that is arranged on slave unit one end; Is connected with at least one circuit-switched data line through one road clock cable, one road chip selection signal line between said main equipment and the communication routing apparatus, is connected with at least one circuit-switched data line through one road clock cable between said communication routing apparatus and each slave unit, said communication routing apparatus be used for basis in the specified time limit that the data wire of said main equipment receives or the data in the specific length resolve as the selection signal; Confirm selected slave unit, and the access path between said main equipment and the selected slave unit is provided.
In one embodiment; Said communication routing apparatus comprise select the signal resolution unit and with the addressed location of the corresponding one by one setting of said slave unit; The data wire of said main equipment, chip selection signal line and clock cable connect the input of said selection signal resolution unit; The output of said selection signal resolution unit connects the Enable Pin of said each addressed location respectively; The data wire and the clock cable of the said main equipment of input termination of said each addressed location, the output of said each addressed location is coupled to the input of corresponding slave unit.
Said selection signal resolution unit is used for also when the signal condition that detects said chip selection signal line is transformed into effective status, confirming that a signal resolution begins, and confirms that when the signal condition that detects said chip selection signal line is transformed into disarmed state this time accessing operation finishes.
Also comprise a plurality of controlled electric unit of corresponding setting and corresponding to a plurality of logic control elements of controlled electric unit with slave unit; The output of said selection signal resolution unit also connects the input of said each logic control element respectively; The output of said each logic control element is coupled to the signal input end of corresponding controlled electric unit; Resolve the data that receive from said main equipment in specified time limit said selection signal resolution unit as the selection signal; Confirm selected electric unit, and send the control useful signal and give corresponding logic control element that said logic control element provides the ON/OFF control command to selected electric unit.
For realizing above-mentioned purpose; The present invention also provides a kind of communication route device; Between spi bus main equipment and spi bus slave unit and be arranged on slave unit one end; Said communication routing apparatus comprise select the signal resolution unit and with the addressed location of the corresponding one by one setting of said slave unit; One circuit-switched data line of said main equipment, one road chip selection signal line and one road clock cable connect the input of said selection signal resolution unit; The output of said selection signal resolution unit connects the Enable Pin of said each addressed location respectively, the data wire and the clock cable of the said main equipment of input termination of said each addressed location, and the output of said each addressed location is coupled to the input of corresponding slave unit; Said selection signal resolution unit is used for the data that receive from main equipment in specified time limit are resolved as the selection signal; Confirm selected slave unit, and send the access permission signal and give selected slave unit corresponding addressed location that said addressed location provides the access path between said main equipment and the corresponding slave unit.
In one embodiment; Said device also comprises a plurality of controlled electric unit of corresponding setting with slave unit and corresponding to a plurality of logic control elements of controlled electric unit; The output of said selection signal resolution unit also connects the input of said each logic control element respectively; The output of said each logic control element is coupled to the signal input end of corresponding controlled electric unit; Resolve the data that receive from said main equipment in specified time limit said selection signal resolution unit as the selection signal; Confirm selected electric unit, and send the control useful signal and give corresponding logic control element that said logic control element provides the ON/OFF control command to selected electric unit.
The invention has the beneficial effects as follows:
The present invention has increased a communication route device between spi bus main equipment and spi bus slave unit; And the communication route device is arranged on slave unit one end; Main equipment only uses the standard signal line (data wire, clock cable and chip selection signal line) of spi bus and slave unit to carry out communication; In the each access process to slave unit, the SPI main equipment provides the selection signal of slave unit earlier through the SPI data wire, and the communication route device is judged according to this selection signal; Confirm selected slave unit, and provide main equipment to the passage the selected slave unit by the communication route device.Therefore; Type according to employed spi bus; Between main equipment and slave unit, only need 3 lines or 4 lines, more pin need not be set come descending other any control signal, just can realize the accessing operation of SPI main equipment the SPI slave unit; Thereby effectively practice thrift the number of pins of communication system host side, be convenient to the expansion of slave unit.
Further; Main equipment can also only use SPI standard signal line to control electric unit (like electric equipments such as power supply and relays); In each control procedure to electric unit; Main equipment provides the selection signal through the SPI data wire earlier, and the communication route device selects signal to judge the electric unit of desire control according to this, and generates the open/close instruction of this electric unit of control; More pin equally also need not be set come descending other control signal, just can realize that the SPI main equipment is to the switch control like electric components such as mains switch, relays.
[description of drawings]
Fig. 1 a and Fig. 1 b are respectively 4 lines and 3 line spi bus sequential sketch mapes;
Fig. 2～Fig. 5 is respectively the theory diagram of main frame and SPI slave unit in the scheme 1～4, power circuit, relay circuit communication;
Fig. 6 is the theory diagram of a kind of embodiment that the present invention is based on the communication system of spi bus;
Fig. 7 a is a kind of embodiment flow chart that the present invention is based on the means of communication of spi bus;
Fig. 7 b is another the embodiment flow chart (electric unit control section) that the present invention is based on the means of communication of spi bus;
Fig. 8 is the circuit theory diagrams of a kind of embodiment of communication route device of the present invention;
Fig. 9 is the spi bus sequential chart of SPI main equipment access slave in an embodiment of the present invention;
Figure 10 is the circuit theory diagrams of another embodiment of communication route device of the present invention;
Figure 11 is the spi bus sequential of SPI main equipment control of electrical equipment in an embodiment of the present invention;
Figure 12 directly connects the theory diagram of slave unit for SPI main equipment in an embodiment of the present invention (compatible ground).
[embodiment]
Characteristic of the present invention and advantage will combine accompanying drawing to be elaborated through embodiment.
Please refer to Fig. 6, a kind of communication system based on spi bus comprises SPI main equipment 110, a plurality of (n) SPI slave unit 201 and a plurality of electric unit, and each electric unit is positioned at power circuit 202 and relay circuit 203.Power circuit 202 has the power interface to 201 power supplies of each SPI slave unit, and relay circuit 203 comprises a plurality of relays, and the mains switch on each power interface is the electric unit in the communication system with each relay.Also comprise communication route device 215; SPI main equipment 110 is through 4 line spi bus---chip selection signal line m_ss_n, serial clock signal line m_sclk, master go out from going into data wire m_mosi and leading from going out data wire m_miso---, and be connected with the input of communication route device 215, communication route device 215 corresponding outputs connect spi bus---the chip selection signal line s of each SPI slave unit 201 respectively
k_ ss_n, serial clock signal line s
k_ sclk, master go out from going into data wire s
k_ mosi and master go into from going out data wire s
k_ miso, k=1 wherein, 2 ..., n.Communication route device 215 corresponding outputs also connect the signal input end Power_control_0～Power_control_n of power circuit 202 about each SPI slave unit 201 mains switch respectively, and connect the signal input end Relay_control_0～Relay_control_n of relay circuit 203 about each relay respectively.
Please refer to Fig. 7 a, based on the means of communication of spi bus, be applied to comprise the communication system based on spi bus of main frame (containing the SPI main equipment) and SPI slave unit, these means of communication are implemented according to following steps:
Step S11, main equipment provide the selection signal of slave unit through the main equipment data wire
Whether the signal condition of a) judging main equipment chip selection signal line jumps to effective status, if then get into next step;
B) when saltus step takes place, pick up counting, receive data from SPI main equipment data wire simultaneously, the data that timing is received till the official hour are as selecting signal.
Step S12, according to selecting signal to confirm selected slave unit
C) preestablish the visit selection instruction of each slave unit;
D) judgement selects the visit selection instruction of signal and which slave unit to be complementary, and visit selection instruction and the slave unit of selecting signal to be complementary are confirmed as selected slave unit.
Step S13, main equipment are to the operation that conducts interviews of selected slave unit
In this process, judge also whether the signal of main equipment chip selection signal line jumps to disarmed state, if then stop accessing operation, and with the timing zero clearing.
Please refer to Fig. 6 b, in improved embodiment, further comprising the steps of based on the means of communication of spi bus:
Step S21, main equipment provide the selection signal of controlled electric unit through the main equipment data wire
Whether the signal condition of a) judging main equipment chip selection signal line jumps to effective status, if then get into next step;
B) when saltus step takes place, pick up counting, receive data from data wire simultaneously, the data that timing is received till the official hour are as selecting signal.
Step S22, according to selecting signal to confirm controlled electric unit, and generate the ON/OFF control command of controlled electric unit
A) preestablish the control selection instruction of each controlled electric unit;
B) judgement selects the control selection instruction of signal and which controlled electric unit to be complementary, and control selection instruction and the electric unit of selecting signal to be complementary are confirmed as selected electric unit;
C) generate the ON/OFF control command according to control signal.
Step S23, control command is sent to controlled electric unit, control its action.
Simultaneously, judge whether the signal condition of main equipment chip selection signal line jumps to disarmed state, if then with the timing zero clearing.
Please refer to Fig. 8, communication route device 215 adopts CPLD to realize, comprises and selects signal resolution unit and a plurality of addressed location.Select the signal resolution unit to comprise clock counter 501, clock comparator 503, shift register 502 and a plurality of first instruct comparator 504, first and the logical block 507 and first programmable register 505 with each SPI slave unit 201 is provided with correspondingly.First programmable register 505 both can be the d type flip flop of band Enable Pin and asynchronous reset end, also can be the latch etc. of being with the asynchronous reset end.Each addressed location is and each SPI slave unit 201 combinational logic 506 one to one.The input end of clock of clock counter 501 and shift register 502 all meets SPI main equipment 110 serial clock signal line m_sclk; The asynchronous reset end all meets SPI main equipment 110 chip selection signal line m_ss_n; The data input pin of shift register 502 meets SPI main equipment 110 masters and goes out from going into data wire m_mosi; The output of shift register 502 connects the input of each first instruction comparator 504 respectively; The input of the output termination clock comparator 503 of clock counter 501; The output of the output of clock comparator 503 and each first instruction comparator 504 connect respectively each first with two inputs of logical block 507; First with the clock Enable Pin of output termination first programmable register 505 of logical block 507, the input end of clock of first programmable register 505 connects SPI main equipment 110 serial clock signal line m_sclk, the Enable Pin of the output termination combinational logic 506 of first programmable register 505.The master of SPI main equipment 110 goes out from going into data wire m_mosi, main going into from going out data wire m_miso and serial clock signal line m_sclk is coupled to each SPI slave unit 201 respectively through each combinational logic 506.The first instruction comparator 504, first and logical block 507, first programmable register 505 and combinational logic 506 respectively have a plurality of; Corresponding one by one with each SPI slave unit 201 respectively; And clock counter 501, clock comparator 503 and shift register 502 can only be provided with one respectively, shared its output signal of late-class circuit.
The bus timing of SPI main equipment 110 visit SPI slave units 201 sees also Fig. 9.During SPI main equipment 110 visit SPI slave units 201, SPI main equipment 110 through communication route device 215 with its spi bus final route to the SPI slave unit 201 of required visit, operation principle is following.In advance with main go out from go into data wire m_mosi transmission selection instruction (being that CPLD instructs) during be set at m clock; From the time sequential routine, can see; When not having the SPI transmission; Chip selection signal line m_ss_n is in disarmed state, is high level, and clock counter 501 is in reset mode with shift register 502.When SPI main equipment 110 chip selection signal line m_ss_n jump to effective low level; Expression has the transmission of SPI signal; Clock counter 501 begins the clock accumulated counts; 503 of clock comparators constantly compare count results that receives and preset value m, when comparative result when being identical, and clock comparator 503 output high level signals.Simultaneously, in this m clock, shift register 502 goes out to carry out shift LD from the serial data of going into data wire m_mosi reception with main, converts parallel data to and exports to each first instruction comparator 504.Each first instruction comparator 504 compares the parallel data of receiving with the predefined visit selection instruction that belongs to each SPI slave unit 201, if comparative result is identical, then export high level signal.The output of clock comparator 503 and each first instruction comparator 504 respectively as each first with the input of logical block 507; When one of them first instruction comparator 504 is output as high level; And when counting down to m clock; First is high level with two inputs of logical block 507, promptly exports the clock Enable Pin of high useful signal to the first programmable register 505.Utilize this enable signal; First programmable register 505 can latch the Enable Pin of useful signal of output to corresponding combinational logic; Thereby connection SPI main equipment 110 is connected with corresponding SPI slave unit 201; Make spi bus only appear at this SPI slave unit 201 ends, realized the bus route of the accessing operation of 110 pairs of SPI slave units 201 of SPI main equipment.
Preceding m clock, what SPI main equipment 110 sent is the CPLD instruction, is used to operate communication route device 215 internal registers, this section SPI signal waveform can not appear at SPI slave unit 201 ends.If the success of SPI main equipment 110 operation communication route devices 215 internal registers according to different CPLD instructions, judges that its visit selection instruction with which slave unit 201 of presetting conforms to, and then is routed to this SPI slave unit 201 ends with spi bus.From m+1 clock, SPI configure waveforms afterwards will appear at this SPI slave unit 201 ends.
The asynchronous reset end of clock counter 501, shift register 502 and first programmable register 505 links to each other with SPI main equipment 110 chip selection signal line m_ss_n; When chip selection signal line m_ss_n saltus step is invalid high level signal; Represent that an accessing operation finishes; This moment, first programmable register 505 automatically reset, and exported invalid level signal, and the SPI signal of slave unit 201 ends blocks automatically.The zero clearing that also resets simultaneously of clock counter 501 and shift register 502 when the arrival of access request next time, restarts work.
Please refer to Figure 10, among the preferred embodiment, communication route device 215 also comprises a plurality of logic control elements corresponding to each controlled electric unit, is used for the switch control of 110 pairs of slave unit 201 power supplys of SPI main equipment and relay.Select the signal resolution unit comprise clock counter 501, clock comparator 503, shift register 502, with the corresponding one by one a plurality of first instruction comparators 504 that are provided with of each SPI slave unit 201, first and the logical block 507 and first programmable register 505, and instruct comparator 510, second and the logical block 508 and second programmable register 511 with a plurality of second of the corresponding one by one setting of each controlled electric unit.Second programmable register 511 can be the d type flip flop with synchronous set and synchronous reset, also can be latch etc., only instructs the level of control output end through parsing CPLD.Logic control element is and each controlled electric unit combinational logic 512 one to one.Be that with the difference of previous embodiment the asynchronous reset end of second programmable register 511 does not link to each other with SPI main equipment 110 chip selection signal line m_ss_n, (also can have SPI main equipment 110 ends that specific asynchronous reset signal is provided) on the shelf.In addition; The output of input termination second programmable register 511 of combinational logic 512; The signal input end of its output termination controlled device, combinational logic 512 and the spi bus that is not used in SPI main equipment 110 are coupled to each controlled device to realize data access operation.In the present embodiment, SPI main equipment 110 is the control that realizes slave unit 201 power circuits 202 and relay circuit 203 through the operation of spi bus.
The bus timing of SPI control operation please refer to Figure 11.At this moment; Communication route device 215 self is a pure SPI slave unit; Operate its inner register according to CPLD instruction (selection signal), after the pin output of the useful signal that is produced through combinational logic 512, control corresponding SPI slave unit 201 mains switches or relay.The process of concrete operation principle and SPI main equipment 110 visit SPI slave units 201 is very similar.Preceding m clock; The SPI main equipment sends the CPLD instruction; Select this CPLD instruction of signal resolution unit resolves; When the signal of in judging this m clock, being received conforms to the mains switch of a certain slave unit 201 or the preset control selection instruction of a certain relay, latch useful signal of output through corresponding second programmable register 511, after the combinational logic 512 corresponding with it received this useful signal; Export signal a to power circuit 202 and/or a relay circuit 203 that is used to carry out ON/OFF control, control the action of this mains switch and/or relay.After the SPI control operation finished, the output of second programmable register 511 still was significant level, and promptly after a control operation was accomplished, controlled device kept its current state.When SPI main equipment 110 sent reset command through spi bus, the output of second programmable register 511 just can become inactive level.
Among the present invention; The SPI main equipment only uses the standard signal line (data wire, clock cable and chip selection signal line) of spi bus and slave unit, electric unit to carry out communication, in once visit or control procedure, and the selection signal that the SPI main equipment provides through the SPI data wire earlier; System is judged according to this signal; Confirm selected object, next selected object is operated, therefore by the SPI main equipment; More pin need not be set come descending other any control signal, just can realize the accessing operation of SPI main equipment subordinate equipment.Therefore, to the SPI main equipment of band SPI standard signal line, the present invention can support to expand the electric equipment that the SPI slave unit of arbitrary number maybe need be controlled, and has good expandability and compatibility.
Realizing through the communication route device on the basis of SPI main equipment and subordinate equipment bus route; The present invention can also directly be connected the SPI main equipment with SPI slave unit, controlled electric unit etc. as existing scheme 1 equally, and is shown in figure 12; Like this; Under the abundant situation of the number of host side communication pin, also can select to adopt the mode of individual sheets choosing to realize the communication of SPI main equipment and subordinate equipment, thereby avoid when increasing less SPI slave unit, changing continually the communication route device; Make communication system SPI main equipment 110 compatibility better, use convenient.
Select the signal resolution unit further to realize through other modes, for example comprise MUX, the selection signal outputs to the control end of MUX, addressed location and/or logic control element that MUX is different according to different selection signal gatings.
Equally, can also connect through the spi bus structure of 3 line types between main equipment and the slave unit.
Obviously; Among the present invention; The SPI main equipment of band SPI standard signal line can support to expand the SPI slave unit (the for example probe plate on the compuscan probe socket) and the electric equipments such as power supply and relay of arbitrary number; Can directly connect slave unit (for example adopting the traditional wired scheme of existing scheme 1) by compatible SPI main equipment in addition, therefore also have favorable compatibility and expandability.
The present invention can be used for controlling the application scenario of a plurality of SPI equipment, and through on portable coloured silk ultra (expanding two probe systems) and a car-type color ultra (three probe systems, and can be extended to four probe systems), making an experiment, the result proves feasible fully.The present invention is particularly useful for ultrasonic diagnostic equipment, and in this application, compuscan SPI main equipment is the SPI main equipment, and the memory device of the probe ID sign indicating number of each probe is the SPI slave unit.
Above content is to combine concrete preferred implementation to the further explain that the present invention did, and can not assert that practical implementation of the present invention is confined to these explanations.For the those of ordinary skill of technical field under the present invention, under the prerequisite that does not break away from the present invention's design, can also make some simple deduction or replace, all should be regarded as belonging to protection scope of the present invention.
Claims (17)
1. the means of communication based on spi bus is characterized in that, may further comprise the steps:
A1, the selection signal of slave unit is provided through the main equipment data wire;
B1, the preset communication route device that is positioned at slave unit one end are confirmed selected slave unit according to said selection signal; Said communication route device comprise select the signal resolution unit and with the addressed location of the corresponding one by one setting of said slave unit; The data wire of said main equipment, chip selection signal line and clock cable connect the input of said selection signal resolution unit; The output of said selection signal resolution unit connects the Enable Pin of said each addressed location respectively; The data wire and the clock cable of the said main equipment of input termination of said each addressed location; The output of said each addressed location is coupled to the input of corresponding slave unit; Wherein, A plurality of first instruction comparators, clock counters that said selection signal resolution unit comprises shift register, be provided with said slave unit correspondingly, clock comparator and with a plurality of first and logical block of the corresponding one by one setting of slave unit; It is parallel data that said shift register is used for said selection conversion of signals, and exports to the said first instruction comparator, and the said first instruction comparator is used for visit selection instruction and said parallel data that corresponding slave unit is set are compared; The output of the said first instruction comparator is coupled to first and logical block; Said clock counter is used for the clock signal from said main equipment is counted, and said clock comparator is used for the clock number of setting and the count value of said clock counter are compared, and the output of said clock comparator is coupled to first and logical block; Said each first carry out logic and operation with output signal that logical block is respectively applied for corresponding first instruction comparator and said clock comparator, and export the logic and operation result addressed location of correspondence to;
C1, main equipment are to the operation that conducts interviews of selected slave unit.
2. the means of communication based on spi bus as claimed in claim 1 is characterized in that, said steps A 1 comprises following substep:
A11, judge whether the signal condition of main equipment chip selection signal line jumps to effective status, if then get into next step;
A12, when saltus step takes place, pick up counting, receive data from the main equipment data wire simultaneously, the data that timing is received till the official hour are as selecting signal;
Said step B1 comprises following substep:
B11, preestablish the visit selection instruction of each slave unit;
B12, judgement select the visit selection instruction of signal and which slave unit to be complementary, and visit selection instruction and the slave unit of selecting signal to be complementary are confirmed as selected slave unit.
3. the means of communication based on spi bus as claimed in claim 2; It is characterized in that; Further comprising the steps of in step C1 carries out: whether the signal condition of judging main equipment chip selection signal line jumps to disarmed state, if then stop accessing operation, and with the timing zero clearing.
4. like each described means of communication in the claim 1 to 3, it is characterized in that based on spi bus, further comprising the steps of:
A2, the selection signal of controlled electric unit is provided through the main equipment data wire;
B2, according to selecting the selected controlled electric unit of signal, and generate the ON/OFF control command of controlled electric unit;
C2, control command is sent to controlled electric unit, control its action.
5. the means of communication based on spi bus as claimed in claim 4 is characterized in that, said steps A 2 comprises following substep:
A21, judge whether the signal condition of main equipment chip selection signal line jumps to effective status, if then get into next step;
A22, when saltus step takes place, pick up counting, receive data from data wire simultaneously, the data that timing is received till the official hour are as selecting signal;
Said step B2 comprises following substep:
B21, preestablish the control selection instruction of each controlled electric unit;
B22, judgement select the control selection instruction of signal and which controlled electric unit to be complementary, and control selection instruction and the electric unit of selecting signal to be complementary are confirmed as selected electric unit;
B23, generate the ON/OFF control command according to control signal.
6. the means of communication based on spi bus as claimed in claim 5 is characterized in that, said controlled electric unit is slave unit mains switch and/or relay.
7. communication system based on spi bus; Comprise spi bus main equipment and a plurality of spi bus slave unit; It is characterized in that; Also comprise the communication routing apparatus that is arranged on slave unit one end; Is connected with at least one circuit-switched data line through one road clock cable, one road chip selection signal line between said main equipment and the communication routing apparatus, is connected with at least one circuit-switched data line through one road clock cable between said communication routing apparatus and each slave unit, said communication routing apparatus be used for basis in the specified time limit that the data wire of said main equipment receives or the data in the specific length resolve as the selection signal; Confirm selected slave unit, and the access path between said main equipment and the selected slave unit is provided; Said communication routing apparatus comprise select the signal resolution unit and with the addressed location of the corresponding one by one setting of said slave unit; The data wire of said main equipment, chip selection signal line and clock cable connect the input of said selection signal resolution unit; The output of said selection signal resolution unit connects the Enable Pin of said each addressed location respectively; The data wire and the clock cable of the said main equipment of input termination of said each addressed location, the output of said each addressed location is coupled to the input of corresponding slave unit; A plurality of first instruction comparators, clock counters that said selection signal resolution unit comprises shift register, be provided with said slave unit correspondingly, clock comparator and with a plurality of first and logical block of the corresponding one by one setting of slave unit; It is parallel data that said shift register is used for said selection conversion of signals; And export to said first the instruction comparator; The said first instruction comparator is used for visit selection instruction and said parallel data that corresponding slave unit is set are compared; The output of the said first instruction comparator is coupled to first and logical block; Said clock counter is used for the clock signal from said main equipment is counted; Said clock comparator is used for the clock number of setting and the count value of said clock counter are compared; The output of said clock comparator is coupled to first and logical block, said each first be respectively applied for logical block the first corresponding instruction comparator and the output signal of said clock comparator carried out logic and operation, and export the logic and operation result addressed location of correspondence to.
8. the communication system based on spi bus as claimed in claim 7; It is characterized in that; Said selection signal resolution unit is used for also when the signal condition that detects said chip selection signal line is transformed into effective status, confirming that a signal resolution begins, and confirms that when the signal condition that detects said chip selection signal line is transformed into disarmed state this time accessing operation finishes.
9. like claim 7 or 8 described communication systems based on spi bus; It is characterized in that; The said first instruction comparator also is used for visit selection instruction and said parallel data that corresponding slave unit is set are compared; When comparative result when being identical, the said first instruction comparator is to the Enable Pin output access enabling signal of the addressed location of correspondence.
10. the communication system based on spi bus as claimed in claim 9 is characterized in that, the chip selection signal line of the said main equipment of termination that resets of said shift register, said clock counter and said addressed location.
11. the communication system based on spi bus as claimed in claim 7; It is characterized in that; Also comprise a plurality of controlled electric unit of corresponding setting and corresponding to a plurality of logic control elements of controlled electric unit with slave unit; The output of said selection signal resolution unit also connects the input of said each logic control element respectively; The output of said each logic control element is coupled to the signal input end of corresponding controlled electric unit, and resolve the data that receive from said main equipment in specified time limit said selection signal resolution unit as the selection signal, confirm selected electric unit; And send the control useful signal and give corresponding logic control element, said logic control element provides the ON/OFF control command to selected electric unit.
12. the communication system based on spi bus as claimed in claim 11; It is characterized in that; A plurality of first instruction comparators that said selection signal resolution unit comprises shift register, clock counter, clock comparator, be provided with said slave unit correspondingly and a plurality of first with logical block and with each controlled electric unit corresponding one by one be provided with a plurality of second instruct comparators and second and logical block; It is parallel data that said shift register is used for said selection conversion of signals; And export to respectively said first the instruction comparator and second the instruction comparator; The said first instruction comparator is used for visit selection instruction and said parallel data that corresponding slave unit is set are compared; The output of the said first instruction comparator is coupled to first and logical block; Said clock counter is used for the clock signal from said main equipment is counted; Said clock comparator is used for the clock number of setting and the count value of said clock counter are compared, and the output of said clock comparator is coupled to first and logical block, said each first be respectively applied for logical block and instruct the output signal of comparator and said clock comparator to carry out logic and operation corresponding first; And export the logic and operation result to corresponding addressed location; Said second instruction comparator the control selection instruction and the said parallel data that are used for corresponding electric unit is set compares, and said second instructs the output of comparator to be coupled to second and logical block, and the output of said clock comparator also is coupled to second and logical block; Said each second carry out logic and operation with output signal that logical block is respectively applied for corresponding second instruction comparator and said clock comparator, and export the logic and operation result logic control element of correspondence to.
13. the communication system based on spi bus as claimed in claim 11 is characterized in that, said controlled electric unit is slave unit mains switch and/or relay.
14. like any described communication system based on spi bus of claim 7 to 13, it is characterized in that said main equipment is the compuscan main equipment, said slave unit is the ID sign indicating number memory device of compuscan probe.
15. communication route device; Between spi bus main equipment and spi bus slave unit and be arranged on slave unit one end; It is characterized in that; Said communication routing apparatus comprise select the signal resolution unit and with the addressed location of the corresponding one by one setting of said slave unit, a circuit-switched data line of said main equipment, one road chip selection signal line and one road clock cable connect the input of said selection signal resolution unit, the output of said selection signal resolution unit connects the Enable Pin of said each addressed location respectively; The data wire and the clock cable of the said main equipment of input termination of said each addressed location; The output of said each addressed location is coupled to the input of corresponding slave unit, and said selection signal resolution unit is used for the data that receive from main equipment in specified time limit are resolved as the selection signal, confirms selected slave unit; And send the access permission signal and give selected slave unit corresponding addressed location, said addressed location provides the access path between said main equipment and the corresponding slave unit; A plurality of first instruction comparators that said selection signal resolution unit comprises shift register, clock counter, clock comparator, be provided with said slave unit correspondingly and a plurality of first and logical block; It is parallel data that said shift register is used for said selection conversion of signals; And export to said first the instruction comparator; The said first instruction comparator is used for visit selection instruction and said parallel data that corresponding slave unit is set are compared; The output of the said first instruction comparator is coupled to first and logical block; Said clock counter is used for the clock signal from said main equipment is counted; Said clock comparator is used for the clock number of setting and the count value of said clock counter are compared; The output of said clock comparator is coupled to first and logical block, said each first be respectively applied for logical block the first corresponding instruction comparator and the output signal of said clock comparator carried out logic and operation, and export the logic and operation result addressed location of correspondence to.
16. communication route device as claimed in claim 15; It is characterized in that; Also comprise a plurality of controlled electric unit of corresponding setting and corresponding to a plurality of logic control elements of controlled electric unit with slave unit; The output of said selection signal resolution unit also connects the input of said each logic control element respectively; The output of said each logic control element is coupled to the signal input end of corresponding controlled electric unit, and resolve the data that receive from said main equipment in specified time limit said selection signal resolution unit as the selection signal, confirm selected electric unit; And send the control useful signal and give corresponding logic control element, said logic control element provides the ON/OFF control command to selected electric unit.
17. communication route device as claimed in claim 16; It is characterized in that; Said selection signal resolution unit also comprises and the corresponding one by one a plurality of second instruction comparators that are provided with of each controlled electric unit and second and logical block; It is parallel data that said shift register also is used for said selection conversion of signals; And export to said second the instruction comparator; Said second instruction comparator the control selection instruction and the said parallel data that are used for corresponding electric unit is set compares, and said second instructs the output of comparator to be coupled to second and logical block, and the output of said clock comparator also is coupled to second and logical block; Said each second carry out logic and operation with output signal that logical block is respectively applied for corresponding second instruction comparator and said clock comparator, and export the logic and operation result logic control element of correspondence to.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810067210A CN101582823B (en) | 2008-05-13 | 2008-05-13 | Communicated method, communication system and communication routing device based on SPI bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810067210A CN101582823B (en) | 2008-05-13 | 2008-05-13 | Communicated method, communication system and communication routing device based on SPI bus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101582823A CN101582823A (en) | 2009-11-18 |
| CN101582823B true CN101582823B (en) | 2012-09-05 |
Family
ID=41364792
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200810067210A Active CN101582823B (en) | 2008-05-13 | 2008-05-13 | Communicated method, communication system and communication routing device based on SPI bus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101582823B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102929826A (en) * | 2012-11-16 | 2013-02-13 | 深圳市建恒测控股份有限公司 | System and method for transmitting multiple ultrasonic signals with single ultrasonic signal bus |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4957813B2 (en) * | 2010-01-26 | 2012-06-20 | 株式会社デンソー | Communication slave and communication network system |
| CN102262604B (en) * | 2011-07-25 | 2017-04-26 | 中兴通讯股份有限公司 | Concurrent access method, system and interface device |
| CN103064815B (en) * | 2012-12-29 | 2015-09-02 | 广东志成冠军集团有限公司 | A kind of single spi bus controls the control method of many CAN interface |
| CN103412845B (en) * | 2013-07-31 | 2016-01-20 | 中国电子科技集团公司第四十一研究所 | A kind of serial bus system |
| CN103684950B (en) * | 2013-12-17 | 2016-08-03 | 唐山轨道客车有限责任公司 | Multisensor multiplex bus system and method |
| ES2643437T3 (en) * | 2014-09-26 | 2017-11-22 | Oberthur Technologies | Serial peripheral interface |
| CN105024900B (en) * | 2015-08-03 | 2018-11-27 | 艾德克斯电子（南京）有限公司 | A kind of Multi-Machine Synchronous communication system and method |
| CN105468563B (en) * | 2015-12-28 | 2018-06-01 | 杭州士兰控股有限公司 | SPI slave devices, SPI communication system and SPI communication method |
| CN105719469A (en) * | 2016-01-26 | 2016-06-29 | 苏州迈瑞微电子有限公司 | SPI (serial peripheral interface) protocol based network relay system and operation method thereof |
| CN107203189A (en) * | 2016-11-30 | 2017-09-26 | 英业达科技有限公司 | A kind of monitoring system, monitoring method and server |
| CN107832249B (en) * | 2017-10-29 | 2020-07-03 | 北京联合大学 | System and method for three-wire realization and communication with peripheral equipment with SPI interface |
| CN108255160B (en) * | 2018-03-12 | 2023-09-08 | 深圳市博诺技术有限公司 | 38PIN interface automobile bus communication line selection system and method |
| WO2020150954A1 (en) * | 2019-01-24 | 2020-07-30 | 深圳市汇顶科技股份有限公司 | Method and apparatus for spi-based asynchronous handling of events, and storage medium |
| CN115174804B (en) * | 2019-06-28 | 2024-02-20 | 华为技术有限公司 | SPI-based data transmission system |
| CN110704089A (en) * | 2019-10-21 | 2020-01-17 | 深圳市友华通信技术有限公司 | Multi-CPLD online upgrading method and device |
| CN110880998B (en) * | 2019-12-03 | 2022-09-20 | 锐捷网络股份有限公司 | Message transmission method and device based on programmable device |
| CN111159077B (en) * | 2019-12-20 | 2021-06-29 | 深圳星康医疗科技有限公司 | Cooperative method and system for SPI double-master device to access same slave device |
| US11308023B2 (en) * | 2020-03-24 | 2022-04-19 | Microchip Technology Incorporated | Method and system for enhanced SPI communication |
| EP4033370B1 (en) * | 2021-01-22 | 2023-11-15 | Aptiv Technologies Limited | Communications system and method of operating the same |
| CN116821005A (en) * | 2023-08-24 | 2023-09-29 | 常州星宇车灯股份有限公司 | Bus communication addressing system and method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2710264Y (en) * | 2004-03-09 | 2005-07-13 | 国电南京自动化股份有限公司 | Time-division multiple real-time communication bus |
| CN101154209A (en) * | 2007-09-12 | 2008-04-02 | 埃派克森微电子(上海)有限公司 | Principal controller pin multiplex circuit and control method thereof |
-
2008
- 2008-05-13 CN CN200810067210A patent/CN101582823B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2710264Y (en) * | 2004-03-09 | 2005-07-13 | 国电南京自动化股份有限公司 | Time-division multiple real-time communication bus |
| CN101154209A (en) * | 2007-09-12 | 2008-04-02 | 埃派克森微电子(上海)有限公司 | Principal controller pin multiplex circuit and control method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102929826A (en) * | 2012-11-16 | 2013-02-13 | 深圳市建恒测控股份有限公司 | System and method for transmitting multiple ultrasonic signals with single ultrasonic signal bus |
| CN102929826B (en) * | 2012-11-16 | 2016-05-11 | 深圳市建恒测控股份有限公司 | A kind of single ultrasonic signal bus transfer multiplex ultrasonic signal system and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101582823A (en) | 2009-11-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101582823B (en) | Communicated method, communication system and communication routing device based on SPI bus | |
| CN102104515B (en) | Coupling devices, system comprising a coupling device and method for use in a system comprising a coupling device | |
| ATE382526T1 (en) | LOAD CONTROL CENTER FOR ELECTRICAL CONSUMERS | |
| CN107256198A (en) | Server and the method for server hard disc board distribution I2C addresses | |
| RU2005138024A (en) | NETWORK TOPOLOGY AND METHOD OF ROUTING PACKAGES USING LOW VOLTAGE ELECTRICAL WIRING | |
| WO2013178249A1 (en) | Optical communications network for high voltage direct current power transmission | |
| US20180358887A1 (en) | Control device and control method for large power conversion | |
| CN104124880A (en) | Distributed controllers for power electronics converter | |
| JP2014166091A (en) | Merging unit and protection and control system | |
| CN102970335B (en) | Communication system | |
| WO2003085899A1 (en) | Automatic, successive configuring of slave modules in a data bus network | |
| CN102545550A (en) | Control device for auxiliary current transformer and auxiliary current transformer system | |
| US8169346B2 (en) | Apparatus and method for processing parallel digital input signals from plurality of circuit breakers | |
| CN101847135B (en) | Series-connected communication system and communication method thereof | |
| CN207896980U (en) | Communication structure and communication system | |
| CN101009542A (en) | Extension device of data network node device port | |
| CN115663549B (en) | Multi-interface conversion device and vehicle | |
| CN106338938B (en) | A kind of backplane bus communication addressing system and method | |
| CN209015137U (en) | Bridge communications circuit | |
| CN106850069A (en) | Data optical fiber cascade unit and system | |
| CN113596189B (en) | Parallel addressing method, battery pack and parallel addressing system | |
| CN207817688U (en) | A kind of serial communication bus interface circuit of compatible different agreement | |
| CN103473206A (en) | Data transmission method and I2C (Inter-Integrated Circuit) interface extender | |
| CN101552930A (en) | Power supply system of MicroTCA and transmission method of management power supply | |
| CN208888804U (en) | A kind of multi-processor electronic device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20180601 Address after: 518057 the 1-4 floor of MINDRAY building, science and technology south twelve Road, Nanshan District high tech Industrial Park, Shenzhen, Guangdong. Co-patentee after: SHENZHEN MINDRAY SCIENTIFIC Co.,Ltd. Patentee after: SHENZHEN MINDRAY BIO-MEDICAL ELECTRONICS Co.,Ltd. Address before: 518057 MINDRAY science and technology south twelve road MINDRAY high tech Industrial Park, Shenzhen, Guangdong Patentee before: SHENZHEN MINDRAY BIO-MEDICAL ELECTRONICS Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20091118 Assignee: Shenzhen Mindray Animal Medical Technology Co.,Ltd. Assignor: SHENZHEN MINDRAY BIO-MEDICAL ELECTRONICS Co.,Ltd. Contract record no.: X2022440020009 Denomination of invention: Communication method, communication system and communication routing device based on SPI bus Granted publication date: 20120905 License type: Common License Record date: 20220804 |
|
| EE01 | Entry into force of recordation of patent licensing contract |