CN101577529B - There is AB class output stage and the method thereof of variable bias point control - Google Patents
There is AB class output stage and the method thereof of variable bias point control Download PDFInfo
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- CN101577529B CN101577529B CN200810099005.9A CN200810099005A CN101577529B CN 101577529 B CN101577529 B CN 101577529B CN 200810099005 A CN200810099005 A CN 200810099005A CN 101577529 B CN101577529 B CN 101577529B
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Abstract
A kind of AB class output stage with variable bias point control, in order to drive a high-order side transistor and a low level side transistor, comprise a driver, one first bias generator, one second bias generator and a control circuit, it is characterized in that: described driver, output one first output signal and one second output signal drive described high-order side and low level side transistor respectively; Described first bias generator, in order to provide the level of the first output signal described in one first bias voltage offset; Described second bias generator, in order to provide the level of the second output signal described in one second bias voltage offset; Described control circuit, in order to regulate first and second bias voltage described.
Description
Technical field
The present invention relates to a kind of AB class output stage, specifically, is a kind of AB class output stage and method thereof with variable bias point control.
Background technology
Fig. 1 shows typical AB class output stage 10, AB class output stage 10 in order to drive the high-order side transistor MP that is connected between power Vcc and earth terminal GND and low level side transistor MN with from output LX output current to load RL, wherein transistor MP and MN is large-sized transistor, in AB class output stage 10, driver 12 provides output signal U H and UL to drive high-order side transistor MP and low level side transistor MN respectively, driver 12 comprises operational amplifier 14 and produces output signal U H and UL according to the voltage on input signal VB and output LX, bias generator 16 and 18 provides bias voltage VOS1 and VOS2 with the level of offset output signal UH and UL respectively, bias voltage VOS1 and VOS2 will affect static (quiescent) electric current and total harmonic distortion (TotalHarmonicDistortion, THD), quiescent current refers to when non-loaded RL, the electric current that power Vcc consumes.Because AB class output stage 10 will drive ohmic load RL, therefore it must be considered simultaneously hand over more (crossover) distortion, the stability in the power consumption that transistor MP and MN causes and loop, Fig. 2 shows the operating space of AB class output stage 10, wherein X-axis represents bias voltage VOS1 and VOS2, the Y-axis of left represents THD, the Y-axis of right represents quiescent current IQ, curve 20 represents the relation between THD and bias voltage VOS1 and VOS2, curve 22 represents the relation between quiescent current IQ and bias voltage VOS1 and VOS2, can be found out by curve 20 and 22, when bias voltage VOS1 and VOS2 increases, THD is less but quiescent current IQ is larger, otherwise, THD is larger, quiescent current IQ is less, the ideal design district 24 that the part come is then bias voltage VOS1 and VOS2 is enclosed with dotted line, lower quiescent current IQ and preferably THD usefulness is had in this design district 24, but, bias voltage VOS1 and VOS2 is likely because of the off-design district 24 to processing procedure change, therefore a kind of method is needed to allow bias voltage VOS1 and VOS2 get back to the design district 24 of target to resist processing procedure change.
Johnson is at United States Patent (USP) the 5th, 481, No. 213 propose a kind of " the mutual conductance protective circuit (cross-conductionpreventioncircuitforpoweramplifieroutput stage) of power amplifier output-stage " and obtain best THD usefulness and suitable quiescent current, but, the method of Johnson needs increase by one group of control circuit and one group of alternative (fill-in) circuit, therefore circuit is comparatively complicated, and also can interfere with each other between these two groups of circuit, thus not easily stablize, in addition, in the circuit of Johnson, bias point cannot adjust, therefore the error that process drift causes cannot be revised.
Therefore known AB class output stage also exists above-mentioned all inconvenience and problem.
Summary of the invention
Object of the present invention, is to propose a kind of AB class output stage and method thereof with variable bias point control.
For achieving the above object, technical solution of the present invention is:
There is an AB class output stage for variable bias point control, in order to drive a high-order side transistor and a low level side transistor, comprise a driver, one first bias generator, one second bias generator and a control circuit, wherein,
Described driver, exports one first output signal and one second output signal drives described high-order side and low level side transistor respectively;
Described first bias generator, in order to provide the level of the first output signal described in one first bias voltage offset;
Described second bias generator, in order to provide the level of the second output signal described in one second bias voltage offset;
Described control circuit, in order to regulate first and second bias voltage described.
The AB class output stage with variable bias point control of the present invention can also be further achieved by the following technical measures.
The aforesaid AB class output stage with variable bias point control, wherein said driver comprises an operational amplifier and produces first and second output signal described according to two input signals.
The aforesaid AB class output stage with variable bias point control, wherein said control circuit comprises:
One first current source, provides the first electric current that is variable;
One second current source, provides the second electric current that is variable;
One the 3rd current source, provides one the 3rd electric current, described 3rd electric current with by the electric current of described high-order side transistor, there is proportionate relationship;
One the 4th current source, provides one the 4th electric current, described 4th electric current with by the electric current of described low level side transistor, there is proportionate relationship;
One logical circuit, first and second bias voltage according to described first electric current and the first difference of the 3rd electric current and the second difference generation one the 3rd output signal adjustment of described second electric current and the 4th electric current.
The aforesaid AB class output stage with variable bias point control, wherein said 3rd current source comprises one and has the transistor of proportionate relationship with the size of described high-order side transistor.
The aforesaid AB class output stage with variable bias point control, wherein said 4th current source comprises one and has the transistor of proportionate relationship with the size of described low level side transistor.
The aforesaid AB class output stage with variable bias point control, wherein said logical circuit is by choosing one of them in described first difference and the second difference as described 3rd output signal.
The aforesaid AB class output stage with variable bias point control, wherein said logical circuit comprises chooses minimum value in described first difference and the second difference as described 3rd output signal.
A variable bias point control method for AB class output stage, is characterized in that, comprise the following steps:
Step one: provide one first bias voltage and one second bias voltage to offset the level of first and second output signal described respectively;
Step 2: variable first electric current and a second variable electric current are provided;
Step 3: provide one with the 3rd electric current by the electric current of described high-order side transistor with proportionate relationship;
Step 4: provide one with the 4th electric current by the electric current of described low level side transistor with proportionate relationship;
Step 5: produce one the 3rd according to described first electric current and the first difference of described 3rd electric current and the second difference of described second electric current and described 4th electric current and output signal and regulate first and second bias voltage described.
The AB class output stage method with variable bias point control of the present invention can also be further achieved by the following technical measures.
The aforesaid AB class output stage method with variable bias point control, the step that wherein said generation 1 the 3rd outputs signal comprises is used as described 3rd output signal by choosing one of them in first and second difference described.
The aforesaid AB class output stage method with variable bias point control, wherein saidly comprises the minimum value chosen in first and second difference described be used as described 3rd output signal by choosing one of them step being used as described 3rd output signal in first and second difference.
After adopting technique scheme, the AB class output stage with variable bias point control of the present invention has the following advantages:
1. due to initially by position higher or lower for bias point setting, therefore without the need to worrying the problem of process drift.
2. increase by one group of control circuit, therefore the problem do not interfered with each other, therefore easily stablize.
Accompanying drawing explanation
Fig. 1 shows typical AB class output stage;
Fig. 2 shows the operating space of AB class output stage in Fig. 1;
Fig. 3 shows embodiments of the invention;
Fig. 4 shows the operating space of AB class output stage in Fig. 3.
Embodiment
Below in conjunction with embodiment and accompanying drawing thereof, the present invention is illustrated further.
Now refer to Fig. 3, Fig. 3 shows embodiments of the invention, as shown in the figure, in described AB class output stage 30, driver 32 provides output signal U H and UL to drive respectively to be connected on high-order side transistor MP between power Vcc and earth terminal GND and low level side transistor MN, described driver 32 comprises an operational amplifier 34 and produces output signal U H and UL according to the voltage on input signal Vin and node LX, bias generator 36 and 38 provides variable bias voltage VOS1 and VOS2 to carry out the level of offset output signal UH and UL respectively, and control circuit 40 is in order to regulate bias voltage VOS1 and VOS2.In described control circuit 40, electric current generation current Id1 on the high-order side transistor MP of transistor MP2 mirror, electric current generation current Id2 on transistor MN2 mirror low level side transistor MN, wherein the size of transistor MP2 and transistor MP has proportionate relationship, therefore electric current I d1 with also there is proportionate relationship by the electric current of transistor MP, equally, the size of transistor MN2 and transistor MN also has proportionate relationship, therefore, electric current I d2 with by the electric current of transistor MN, there is proportionate relationship, the difference i2 generation current i3 of the current i o that the difference i1 of the current i o that logical circuit 46 provides according to electric current I d1 and current source 42 and electric current I d2 and current source 44 provide regulates bias voltage VOS1 and VOS2, the current i o that wherein current source 42 and 44 provides can be adjusted by outside.
Refer to Fig. 4 again, Fig. 4 shows the operating space of AB class output stage in Fig. 3, wherein X-axis represents bias voltage VOS1 and VOS2 or current i o, the Y-axis of left represents THD, the Y-axis of right represents quiescent current IQ, curve 50 represents the relation between THD and bias voltage VOS1 and VOS2, and curve 52 represents the relation between quiescent current IQ and bias voltage VOS1 and VOS2, and region B represents desirable design district.Bias generator 36 and 38 is allowed to provide larger bias voltage VOS1 and VOS2 to drop in the region A of B right, region to make bias point at the beginning, therefore, even if there is process drift also can guarantee the right of bias point at region B, as shown in Figure 4 when bias point in region a time, there is good THD usefulness, but the quiescent current IQ on transistor MP and MN will be larger, because excessive quiescent current IQ is bad, therefore the current i o regulating current source 42 and 44 to provide makes bias point shift to region B by region A, larger current i o will cause larger quiescent current IQ and good THD usefulness, otherwise, less current i o will cause less quiescent current IQ and poor THD usefulness.With reference to Fig. 3, after electric current I d1 on transistor MP2 deducts the current i o that current source 42 provides, generation current i1 is to logical circuit 46, after electric current I d2 on transistor MN2 deducts the current i o that current source 44 provides, generation current i2 is to logical circuit 46, logical circuit 46 selects less electric current as current i 3 to regulate bias voltage VOS1 and VOS2 of bias generator 36 and 38 from current i 1 and i2, if, when current i 1 and i2 are very large, the current i 3 that logical circuit 46 exports will be very large, thus bias voltage VOS1 and VOS2 is reduced, and then the quiescent current IQ reduced on transistor MP and MN, the ratio of electric current I d1 and electric current I d2 also will diminish, last current i 1, i2, balance will be reached between i3 and io, therefore the bias point that current i o can change AB class output stage 30 is changed.In this embodiment, be that bias voltage VOS1 and VOS2 that setting is larger drops in the region A of B right, region to make bias point at the beginning, in other embodiments, also can setting less bias voltage VOS1 and VOS2 with the left making bias point drop on region B at the beginning.
AB class output stage 30 can adjust bias voltage VOS1 and VOS2 by changing current i o, and then allow bias point get back to desirable design district B, in addition, owing to initially bias point being set higher or lower position, therefore without the need to worrying the problem of process drift, and only increase by one group of control circuit 40 therefore the problem do not interfered with each other, therefore easily stablize.
Above embodiment is used for illustrative purposes only, but not limitation of the present invention, person skilled in the relevant technique, without departing from the spirit and scope of the present invention, can also make various conversion or change.Therefore, all equivalent technical schemes also should belong to category of the present invention, should be limited by each claim.
Element numbers explanation
10AB class output stage
12 drivers
14 operational amplifiers
16 bias generators
18 bias generators
Relation curve between 20THD and bias voltage VOS1 and VOS2
Relation curve between 22 quiescent current IQ and bias voltage VOS1 and VOS2
24 design districts
30AB class output stage
32 drivers
34 operational amplifiers
36 bias generators
38 bias generators
40 control circuits
42 current sources
44 current sources
46 logical circuits
Relation curve between 50THD and bias voltage VOS1 and VOS2
Relation curve between 52 quiescent current IQ and bias voltage VOS1 and VOS2
Claims (9)
1. have an AB class output stage for variable bias point control, in order to drive a high-order side transistor and a low level side transistor, comprise a driver, one first bias generator, one second bias generator and a control circuit, is characterized in that,
Described driver, exports one first output signal and one second output signal drives described high-order side and low level side transistor respectively;
Described first bias generator, in order to provide the level of the first output signal described in one first bias voltage offset;
Described second bias generator, in order to provide the level of the second output signal described in one second bias voltage offset;
Described control circuit, in order to regulate first and second bias voltage described;
Wherein, described control circuit comprises:
One first current source, provides the first electric current that is variable;
One second current source, provides the second electric current that is variable;
One the 3rd current source, provides one the 3rd electric current, described 3rd electric current with by the electric current of described high-order side transistor, there is proportionate relationship;
One the 4th current source, provides one the 4th electric current, described 4th electric current with by the electric current of described low level side transistor, there is proportionate relationship;
One logical circuit, first and second bias voltage according to described first electric current and the first difference of the 3rd electric current and the second difference generation one the 3rd output signal adjustment of described second electric current and the 4th electric current.
2. AB class output stage as claimed in claim 1, is characterized in that, described driver comprises an operational amplifier and produces first and second output signal described according to two input signals.
3. AB class output stage as claimed in claim 1, is characterized in that, described 3rd current source comprises one and has the transistor of proportionate relationship with the size of described high-order side transistor.
4. AB class output stage as claimed in claim 1, is characterized in that, described 4th current source comprises one and has the transistor of proportionate relationship with the size of described low level side transistor.
5. AB class output stage as claimed in claim 1, it is characterized in that, described logical circuit is by choosing one of them in described first difference and the second difference as described 3rd output signal.
6. AB class output stage as claimed in claim 5, is characterized in that, described logical circuit comprises chooses minimum value in described first difference and the second difference as described 3rd output signal.
7. the variable bias point control method of an AB class output stage, this AB class output stage provides one first output signal and one second output signal to drive a high-order side transistor and a low level side transistor respectively, it is characterized in that, this variable bias point control method comprises the following steps:
Step one: provide one first bias voltage and one second bias voltage to offset the level of first and second output signal described respectively;
Step 2: variable first electric current and a second variable electric current are provided;
Step 3: provide one with the 3rd electric current by the electric current of described high-order side transistor with proportionate relationship;
Step 4: provide one with the 4th electric current by the electric current of described low level side transistor with proportionate relationship;
Step 5: produce one the 3rd according to described first electric current and the first difference of described 3rd electric current and the second difference of described second electric current and described 4th electric current and output signal and regulate first and second bias voltage described.
8. variable bias point control method as claimed in claim 7, is characterized in that, the step that described generation 1 the 3rd outputs signal comprises is used as described 3rd output signal by choosing one of them in first and second difference described.
9. variable bias point control method as claimed in claim 8, it is characterized in that, describedly comprise the minimum value chosen in first and second difference described be used as described 3rd output signal by choosing one of them step being used as described 3rd output signal in first and second difference.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810099005.9A CN101577529B (en) | 2008-05-09 | 2008-05-09 | There is AB class output stage and the method thereof of variable bias point control |
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| CN200810099005.9A CN101577529B (en) | 2008-05-09 | 2008-05-09 | There is AB class output stage and the method thereof of variable bias point control |
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| CN101577529B true CN101577529B (en) | 2016-01-27 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US10789895B2 (en) * | 2018-06-15 | 2020-09-29 | Novatek Microelectronics Corp. | Differential difference amplifier circuit having variable transconductance |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5481213A (en) * | 1993-12-17 | 1996-01-02 | National Semiconductor Corporation | Cross-conduction prevention circuit for power amplifier output stage |
| US6255909B1 (en) * | 2000-11-02 | 2001-07-03 | Texas Instruments Incorporated | Ultra low voltage CMOS class AB power amplifier with parasitic capacitance internal compensation |
| CN1402904A (en) * | 1999-12-02 | 2003-03-12 | 雅马哈株式会社 | Differential amplifier |
| US6788147B1 (en) * | 2002-11-05 | 2004-09-07 | National Semiconductor Corporation | Operational amplifier with class-AB+B output stage |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3936952B2 (en) * | 2004-11-26 | 2007-06-27 | 株式会社半導体理工学研究センター | AB class CMOS output circuit |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5481213A (en) * | 1993-12-17 | 1996-01-02 | National Semiconductor Corporation | Cross-conduction prevention circuit for power amplifier output stage |
| CN1402904A (en) * | 1999-12-02 | 2003-03-12 | 雅马哈株式会社 | Differential amplifier |
| US6255909B1 (en) * | 2000-11-02 | 2001-07-03 | Texas Instruments Incorporated | Ultra low voltage CMOS class AB power amplifier with parasitic capacitance internal compensation |
| US6788147B1 (en) * | 2002-11-05 | 2004-09-07 | National Semiconductor Corporation | Operational amplifier with class-AB+B output stage |
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| CN101577529A (en) | 2009-11-11 |
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