CN101576817B - Processor system and working method thereof - Google Patents
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- CN101576817B CN101576817B CN2008100961821A CN200810096182A CN101576817B CN 101576817 B CN101576817 B CN 101576817B CN 2008100961821 A CN2008100961821 A CN 2008100961821A CN 200810096182 A CN200810096182 A CN 200810096182A CN 101576817 B CN101576817 B CN 101576817B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
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Abstract
The embodiment of the invention provides a processor system and a working method thereof. The processor system comprises an instruction transmitting unit, an address mapping unit connected with the instruction transmitting unit through an external component interconnection bus, and a memory device connected with the address mapping unit, wherein the instruction transmitting unit is used for receiving the instruction of a processor and pointing the instruction of the processor to the external component interconnection bus; and the address mapping unit is used for responding to the instruction and mapping the address accessed by the instruction to the memory device. The processor system has the advantage that the processor in the processor system provided by the embodiment of the invention can be started through a PCI bus. Because the band width of the PCI bus is farther larger than that of an LPC, when the processor system is started through the PCI bus, the starting speed of the systemis greatly improved.
Description
Technical field
The present invention relates to the processor technical field, relate in particular to a kind of processor system and method for work thereof.
Background technology
The Embedded Application field is adopted PowerPC, MIPS (Millions ofInstructions Per Second usually; MIPS), the Reduced Instruction Set Computer of framework such as ARM, 68K (Reduced Instruction Set Computer; RISC) processor; Along with the continuous development of communication facilities, more and more stronger to the demand of high operational performance and high bulk density processor, the risc processor of conventional architectures can not satisfy the demand; The substitute is CISC (Complex Instruction Set Computer, the CISC) processor of the X86 framework that is celebrated with high operational performance.
See also Fig. 1; For existing X 86 processor system forms synoptic diagram; Central processing unit (CPU) 101 through Front Side Bus (Front Side Bus, FSB) 102 link to each other with north bridge 103, north bridge 103 inside are mainly integrated Memory Controller Hub and high speed bus interface; Pass through Hublink or DMI between north bridge 103 and the south bridge 104 (because of difference different bus 105 connections of producer, chipset; The low pin count amount of south bridge 104 (Low Pin Count, LPC) interface 106 connect Basic Input or Output System (BIOS)s (BasicInput Output System, BIOS) equipment 107; The PATA of south bridge 104 or SATA interface 108 connect hard disk 109, and hard disk 109 is used for deposit operation system and data file.In addition, south bridge 104 also provides the peripheral component interconnect that is used to connect external unit 111 (Peripheral ComponentInterconnect, PCI) interface 110.
After CPU101 shown in Figure 1 resets; The system address place instruction fetch that the instruction that CPU101 sends will be removed 0xFFFF FFF0; And this system address is mapped to by south bridge 104 in the system space of BIOS equipment 107 correspondences, and therefore, X 86 processor shown in Figure 1 at first will read the partial code in the BIOS equipment 107; Accomplish configuration and a series of self check operation of CPU101 and north and south bridge 103,104; Then, other codes in the BIOS equipment 107 are realized the startup of X 86 processor system with guiding CPU 101 load operation system from hard disk 109 to internal memory.
In research and practice process to prior art, the inventor finds that there is following problem in prior art:
Existing X 86 processor system starts through the LPC interface; But the LPC interface rate low (clock is 33MHZ, the data line that data and address multiplex are 4, and per 7 clock period just can read a byte; Efficient is extremely low), directly influenced the toggle speed of X 86 processor system.
Summary of the invention
The technical matters that the embodiment of the invention will solve provides a kind of processor system and method for work thereof, can improve the toggle speed of processor system.
The embodiment of the invention provides a kind of processor system, comprising:
The instruction delivery unit, the address mapping unit that is connected with said instruction delivery unit through the peripheral component interconnect bus, and the memory storage that is connected with said address mapping unit;
Said instruction delivery unit is used for the instruction of receiving processor, and said peripheral component interconnect bus is pointed in the instruction of processor;
Said address mapping unit is used to respond said instruction, and the map addresses of said instruction access is arrived said memory storage.
The present invention implements to draw a kind of processor system method of work also is provided, and comprising:
The instruction of receiving processor on the peripheral component interconnect bus;
The instruction of the processor of said peripheral component interconnect bus is pointed in the instruction of said processor for the instruction delivery unit;
Address mapping unit responds the instruction of said processor, with the map addresses of the instruction access of said processor to memory storage;
If said memory storage comprises the enabled instruction storage space, the instruction that then said address mapping unit responds said processor comprises:
When the address space of the first memory of the external bus nucleus module of said address mapping unit comprise processor be used to read the address of enabled instruction visit of BIOS the time, the external bus nucleus module of said address mapping unit responds the enabled instruction of said processor;
The map addresses of the instruction access of said processor is specially to memory storage:
The address space of the first memory of the enabled instruction of processor visit is mapped to the enabled instruction storage space of said memory storage.
Technique scheme has following beneficial effect:
In the technical scheme that the embodiment of the invention provides; The instruction delivery unit that links to each other with processor can point to the instruction of processor external component interconnected (PCI) bus; Address mapping unit through being connected on the pci bus responds this instruction, and the map addresses of this instruction access is arrived memory storage, makes processor to start through pci bus; Because the bandwidth of pci bus is much larger than the bandwidth of LPC; Therefore, start processor system, improved system start-up speed greatly from pci bus.
Description of drawings
Fig. 1 forms synoptic diagram for the X 86 processor system that prior art provides;
Fig. 2 forms synoptic diagram for the processor system that the embodiment of the invention provides;
Fig. 3 forms synoptic diagram for the X 86 processor system that the embodiment of the invention provides;
The map addresses figure that Fig. 4 provides for the embodiment of the invention;
The processor system method of work process flow diagram that Fig. 5 provides for the embodiment of the invention.
Embodiment
For the purpose that makes the embodiment of the invention, technical scheme, and advantage clearer, below the technical scheme that the embodiment of the invention provides is elaborated with reference to accompanying drawing.
See also Fig. 2, a kind of processor system that the embodiment of the invention provides comprises: processor 201, instruction delivery unit 202, address mapping unit 203, memory storage 204.
Peripheral component interconnect (Peripheral Component Interconnect; PCI) pci interface of a termination of bus 205 instruction delivery unit 202; Address mapping unit 203 is connected on the pci bus 205, and memory storage 204 links to each other with address mapping unit 203 through bus 206.
When processor system electrifying startup shown in Figure 2, instruction delivery unit 202 points to pci bus 205 with the instruction that processor 201 sends, and address mapping unit 203 responses should instruction, and with the map addresses of instruction access to memory storage 204.
In embodiments of the present invention, the instruction delivery unit 202 that links to each other with processor 201 can point to pci bus 205 with the instruction that processor 201 sends, through being connected address mapping unit 203 these instructions of response on the pci bus 205; And with the map addresses of this instruction access to memory storage 204, make processor 201 to start, because bandwidth (the typical pci bus: 32bit*33MHz of pci bus through pci bus 205; Bandwidth＞1Gbps; Actual data transfer rate＞64MB/s) much larger than the bandwidth of LPC (4bit*33MHz, bandwidth＜132Mbps is simultaneously because 4 interfaces are that data/address/command is multiplexing; Actual data transfer rate＜6MB/s); Therefore, start processor system, improved system start-up speed greatly from pci bus.
The processor system that more than provides for the embodiment of the invention, wherein, instruction delivery unit 202 is a functional entity of south bridge; And in this embodiment, the north and south bridge chip is integrated in together; In other embodiment of the present invention, if the north and south bridge chip is not integrated in together, then said system need further comprise: north bridge; North bridge links to each other with processor, and the instruction that processor 201 sends is sent to the instruction delivery unit 202 of south bridge through north bridge.
Below in conjunction with specific embodiment, the processor system that the embodiment of the invention provides is done further introduction in detail.
See also Fig. 3; In the X 86 processor system that the embodiment of the invention provides, processor 301 links to each other with chipset 302 through FSB bus 305, chipset 302 is integrated north bridge 3021 and south bridge 3022; Link to each other through Hublink or DMI (each producer, each chipset call inconsistent) bus between north bridge 3021 and the south bridge 3022; South bridge 3022 comprises instruction delivery unit and a Starting mode base pin selection, and when processor system electrifying startup shown in Figure 3, south bridge 3022 detects the level of Starting mode base pin selections; When the level of Starting mode base pin selection be low level (Starting mode base pin selection ground connection) or for high level (the Starting mode base pin selection connects power supply; Such as, the 3.3V power supply) time, the instruction delivery unit of south bridge 3022 points to pci bus 306 with the instruction that processor 301 sends.
The address mapping unit 303 that is connected on the pci bus 306 is realized PCI slave unit function, is used to respond the instruction of pointing to pci bus 306, and the map addresses of instruction access is arrived memory storage 304.
Below the concrete implementation of X 86 processor shown in Figure 3 system is described in detail.
In practical application; Address mapping unit 303 comprises at least: external bus core (PCI Core) module; And, complete compatible with PCI 2.1 standards 2 of the PCI Core module that the embodiment of the invention provides, PCI Core module; Be used to realize the seamless link with pci bus 306, and the instruction of the processor 301 of pci bus 306 is pointed in response.
In order to make processor 301 read BIOS through pci bus; The memory storage 304 that the embodiment of the invention provides has comprised: be used for the storage system enabled instruction (promptly; System bios) enabled instruction storage space, address mapping unit 303 comprises: address mapping module;
When processor 301 transmissions are used to read the enabled instruction of BIOS; For make PCI Core module can answer processor 301 enabled instructions of sending; Need be one section first memory of PCI Core module assignment (PCI_MEM1); The address that comprises the enabled instruction visit of processor 301 in the address space of PCI_MEM1, and, the enabled instruction storage space of PCI_MEM1 corresponding stored device 304.
After PCI Core module receives enabled instruction; Find to comprise in the address space of PCI_MEM1 the enabled instruction visit the address (such as; When bar was got instruction headed by the enabled instruction, the address space of PCI_MEM1 comprised that first is got the address 0xFFFF FFF0 that refers to instruction access), so; The effective DEVSEL# of PCI Core module states it oneself is the target device of this transaction; Wherein, DEVSEL# is the pci bus signal, effectively DEVSEL# show that target device decoding answer processor 301 sends enabled instruction.
After the enabled instruction that PCI Core module responds processor sends; Address mapping module; The address space of the first memory of enabled instruction visit is mapped to the enabled instruction storage space, comprises that getting the address 0xFFFF FFF0 that refers to instruction access with first is mapped to the enabled instruction storage space.
In addition; Utilize hard disk storing operating system in the prior art; Drive formula and upper application software, big (2W～20W), toggle speed slow (more than 15 seconds), shortcomings such as reliability is low, volume is big, cost height are not suitable for the Embedded Application field and there is power consumption in hard disk.
For addressing the above problem; The embodiment of the invention adopt jumbo storage chip able to programme (such as, EEPROM or FLASH) as memory storage 304, memory storage 304 further comprises: the system information storage space; This space is used for the deposit operation system, drives formula and upper application software.
In order to make processor 301 can pass through pci bus load operating operating system from the system information storage space; Driver; And application software, need be space, one section second memory block of PCI Core module assignment (PCI_MEM2), the system information storage space of PCI_MEM2 corresponding stored device 304; And PCI_MEM2 comprises the address of system information reading command visit.
When the level of the Starting mode base pin selection of south bridge 301 be low level (Starting mode base pin selection ground connection) or for high level (the Starting mode base pin selection connects power supply; Such as; 3.3V in the time of power supply), the instruction delivery unit of south bridge 3022 points to pci bus with the system information reading command that processor 301 sends.
After PCI Core module receives the system information reading command, when comprising the address of system information reading command visit in the address space of discovery PCI_MEM2, respond this system information reading command.
After PCI Core module responds system information reading command, address mapping module is mapped to the address space of the second memory of system information reading command visit the system information storage space of said memory storage 304.
Below introduce the working mechanism of the address mapping module that the embodiment of the invention provides.
For the address space in the two segment memory spaces that make address mapping unit 303 can keep under the condition of same addressing order; Parallelly be mapped in the memory storage 304 corresponding storage space; The embodiment of the invention adopts totalizer to realize map addresses, and said method comprises:
If the address among the processor 303 visit PCI_MEM1: PCI_MEM1; PCI Core module detects the back and finds that PCI_MEM1 hits the address space of PCI_MEM1 in the base address; Address mapping module is mapped as PCI_MEM1+ first offset address with PCI_MEM1; Be that address mapping module adds first offset address on PCI_MEM1, obtain the address of enabling address storage space.
If the address in the processor access PCI_MEM2 space: PCI_MEM2; PCI Core module detects the back and finds that PCI_MEM2 hits the address space of PCI_MEM2 in the base address; Then address mapping module is mapped as PCI_MEM2+ second offset address with PCI_MEM2; Be that address mapping module adds second offset address on PCI_MEM2, obtain the address of system information storage space.
More than introduce the implementation of the X 86 processor system that the embodiment of the invention provides, below introduced the configuration mode of the address space in the PCI Core module storage space that the embodiment of the invention provides for example.
The size of supposing the enabled instruction storage space is 8MB; The size of system information storage space is 248M, and then the address of PCI_MEM1 starts from 0xFF800000, ends at 0xFFFF FFFF; Be total to the space of 8MB; The address of PCI_MEM2 originates in 0xF0000000, ends at 0xFF7FFFFF, altogether the space of 248MB.
See also table 1, be the logical address allocation table of two sections storage spaces of PCI Core module.
| Space segment | Base address register | Start address | The end address | Space segment |
| PCI_MEM1 | BAR0 | 0xFF800000 | 0xFFFF?FFFF | 8MB |
| PCI_MEM2 | BAR1 | 0xF0000000 | 0xFF7F?FFFF | 248MB |
| PCI_IO | BAR2 | System configuration | System configuration | 64Byte |
| Configuration space | 00h | FFh | 256Byte |
See also Fig. 4, be the mapping relations figure of the address space of the storage space of the address space of the storage space of the PCI_Core module shown in the table 1 and memory storage.
In practical application, by the start address of base address register BAR0 record PCI_MEM1, and this address writes when logical design extremely, i.e. after the X 86 processor system reset, BAR0 just is assigned 0xF,F80 0000.The start address of base address register BAR1 record PCI_MEM2.
And some position in the PCI Core modules configured space need reset the back with regard to assignment at processor system, see also table 2, the information in the PCI Core modules configured space that provides for the embodiment of the invention.
Table 2
Mapping relations shown in Figure 4 and table 1 are merely the technical scheme that the clearer explanation embodiment of the invention provides, and should not be regarded as the restriction to the embodiment of the invention.
It should be noted that; In practical application; If address mapping unit 303 be complex programmable (Complex Programmable Logic Device, CPLD) logical device functional entity, memory storage 304 are flash (FLASH) memory storages; Then address mapping unit 303 links to each other with memory storage 304 through memory interface 307; At this moment, address mapping unit 303 further comprises: the read-write operation modular converter is used for converting the read-write operation on the pci bus on the memory interface read-write operation.
The processor system that more than provides for the embodiment of the invention, below processor method of work that the embodiment of the invention is provided introduce.
See also Fig. 5, the processor system method of work for the embodiment of the invention provides comprises:
Step 501: the instruction of receiving processor on the peripheral component interconnect bus, wherein, the instruction of the processor of said peripheral component interconnect bus is pointed in the instruction of said processor for the instruction delivery unit;
Step 502: respond the instruction of said processor, with the map addresses of the instruction access of said processor to memory storage.
Step 502: respond said instruction, and the map addresses of instruction access is arrived memory storage.
One of ordinary skill in the art will appreciate that all or part of step that realizes in the foregoing description method is to instruct relevant hardware to accomplish through program; Described program can be stored in a kind of computer-readable recording medium; This program comprises the method step that preamble has been stated when carrying out.
The above-mentioned storage medium of mentioning can be a read-only memory device, disk or CD etc.
More than a kind of processor system provided by the present invention and method of work thereof have been carried out detailed introduction; For one of ordinary skill in the art; Thought according to the embodiment of the invention; The part that on embodiment and range of application, all can change, in sum, this description should not be construed as limitation of the present invention.
Claims (10)
1. a processor system is characterized in that, comprising:
The instruction delivery unit, the address mapping unit that is connected with said instruction delivery unit through the peripheral component interconnect bus, and the memory storage that is connected with said address mapping unit;
Said instruction delivery unit is used for the instruction of receiving processor, and said peripheral component interconnect bus is pointed in the instruction of processor;
Said address mapping unit is used to respond said instruction, and the map addresses of said instruction access is arrived said memory storage;
Wherein, said memory storage comprises the enabled instruction storage space, and said address mapping unit specifically comprises: external bus nucleus module, address mapping module;
When the address space of the first memory of said external bus nucleus module being used to of comprising that processor sends read the address of enabled instruction visit of BIOS, said external bus nucleus module responded said enabled instruction;
After said external bus nucleus module responded said enabled instruction, said address mapping module was used for the address space of the first memory of said enabled instruction visit is mapped to said enabled instruction storage space.
2. the system of claim 1; It is characterized in that; Said instruction delivery unit is a functional entity of south bridge; Said south bridge comprises the Starting mode base pin selection, when said Starting mode base pin selection ground connection perhaps connects power supply, and the instruction directed outwards parts interconnected bus that said instruction delivery unit sends processor.
3. like claim 1 or 2 described systems, it is characterized in that said memory storage further comprises the system information storage space, said system information storage space is used for deposit operation system, driver and application software;
When the address space of the second memory of said external bus nucleus module comprised the address of the system information reading command visit that processor sends, said external bus nucleus module responded said system information reading command;
After said external bus nucleus module responded said system information reading command, said address mapping module was used for the address space of the second memory of said system information reading command visit is mapped to said system information storage space.
4. according to claim 1 or claim 2 system; It is characterized in that; If said address mapping unit is a functional entity of complex programmable device; Said memory storage is a flash memory devices, and then said address mapping unit links to each other with said flash memory devices through memory interface, and said address mapping unit further comprises:
The read-write operation modular converter is used for converting the read-write operation on the said peripheral component interconnect bus on the memory interface read-write operation.
5. a processor system method of work is characterized in that, said method comprises:
The instruction of receiving processor on the peripheral component interconnect bus;
The instruction of the processor of said peripheral component interconnect bus is pointed in the instruction of said processor for the instruction delivery unit;
Address mapping unit responds the instruction of said processor, with the map addresses of the instruction access of said processor to memory storage;
If said memory storage comprises the enabled instruction storage space, the instruction that then said address mapping unit responds said processor comprises:
When the address space of the first memory of the external bus nucleus module of said address mapping unit comprise processor be used to read the address of enabled instruction visit of BIOS the time, the external bus nucleus module of said address mapping unit responds the enabled instruction of said processor;
The map addresses of the instruction access of said processor is specially to memory storage:
The address space of the first memory of the enabled instruction of processor visit is mapped to the enabled instruction storage space of said memory storage.
6. method as claimed in claim 5; It is characterized in that; If said instruction delivery unit is a functional entity in the south bridge, said south bridge comprises a Starting mode base pin selection, and the instruction delivery unit comprises the instruction directed outwards parts interconnected bus of processor:
Said south bridge detects the level of said Starting mode base pin selection, when said pin is high level or low level, and the instruction directed outwards parts interconnected bus that the instruction delivery unit of said south bridge sends said processor.
7. like claim 5 or 6 described methods, it is characterized in that the enabled instruction storage space that the address space of the first memory of the enabled instruction of processor visit is mapped to said memory storage comprises:
On the address space of the first memory that said enabled instruction is visited, add first offset address, obtain the address of said enabled instruction storage space.
8. like claim 5 or 6 described methods; It is characterized in that; Said memory storage comprises: the system information storage space, and said system information storage space is used for methods of storage operating, driver and application software, and the instruction that then said address mapping unit responds said processor comprises:
When the address space of the second memory of the external bus nucleus module of address map unit comprised the address of system information reading command visit of processor, the external bus nucleus module of said address mapping unit responded the system information reading command of said processor;
The map addresses of the instruction access of said processor is specially to memory storage:
The address space of the second memory of the system information reading command of processor visit is mapped to the system information storage space of said memory storage.
9. method as claimed in claim 8 is characterized in that, the system information storage space that the address space of the second memory of said system information reading command visit with processor is mapped to said memory storage comprises:
On the address space of the second memory that the system information reading command of said processor is visited, add second offset address, obtain the address of said system information storage space.
10. like claim 5 or 6 described methods; It is characterized in that; If instruction by address mapping unit receiving processor on the peripheral component interconnect bus; And said memory storage is a flash memory devices, and then said address mapping unit links to each other with said flash memory devices through memory interface, and said method further comprises:
Convert the read-write operation on the said peripheral component interconnect bus on the memory interface read-write operation.
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| CN2008100961821A CN101576817B (en) | 2008-05-09 | 2008-05-09 | Processor system and working method thereof |
| PCT/CN2009/071698 WO2009135443A1 (en) | 2008-05-09 | 2009-05-08 | Processor system and its working method |
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| CN2008100961821A CN101576817B (en) | 2008-05-09 | 2008-05-09 | Processor system and working method thereof |
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| CN103713709A (en) * | 2013-11-11 | 2014-04-09 | 青岛中科英泰商用***有限公司 | Touch industrial tablet computer with qualified and unqualified control switches and audio ports |
| CN103713707A (en) * | 2013-11-11 | 2014-04-09 | 青岛中科英泰商用***有限公司 | Multifunctional touch-screen industry tablet computer provided with qualified product and unqualified product control switches |
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| CN101021815A (en) * | 2007-03-19 | 2007-08-22 | 威盛电子股份有限公司 | Storage access system and its memory access method |
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| US5608876A (en) * | 1995-05-22 | 1997-03-04 | International Business Machines Corporation | Add-in board with enable-disable expansion ROM for PCI bus computers |
| CN1157661C (en) * | 2001-11-27 | 2004-07-14 | 矽统科技股份有限公司 | System and method for computer system to adopt image card memory as expanding memory |
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| CN101021815A (en) * | 2007-03-19 | 2007-08-22 | 威盛电子股份有限公司 | Storage access system and its memory access method |
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