CN101572891A - System and method for filtering 3G data packet based on FPGA - Google Patents

System and method for filtering 3G data packet based on FPGA Download PDF

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Publication number
CN101572891A
CN101572891A CNA2009100331431A CN200910033143A CN101572891A CN 101572891 A CN101572891 A CN 101572891A CN A2009100331431 A CNA2009100331431 A CN A2009100331431A CN 200910033143 A CN200910033143 A CN 200910033143A CN 101572891 A CN101572891 A CN 101572891A
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module
packet
characteristic information
data
gtp
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CN101572891B (en
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黄杰
秦中元
张晓晓
孙婷婷
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Southeast University
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Southeast University
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Abstract

The invention discloses a system and a method for filtering a 3G network data packet based on FPGA, and belongs to a data filter method in the field of TD-SCDMA network security. The system comprises an EMAC hardcore module and a user processing logic module, wherein the user processing logic module comprises a control packet analysis module, two GTP data packet analysis modules, a read-write control module, a characteristic information search engine, a characteristic information storage module and two forward control modules. The method comprises a control packet processing method and a GTP data packet processing method. The processing capability is strong, and the universality is high.

Description

3G packet filtering system and method based on FPGA
Technical field
Invention relates to a kind of 3G network packet filtering system and method based on FPGA, belongs to the data filtering method of TD-SCDMA network safety filed.
Background technology
3-G (Generation Three mobile communication system) is IMT-2000, and the 3G air interface standard is named as IMT-2000 wireless interface technology standard in May, 2000, and this standard comprises code division multiple access (CDMA) and time division multiple access (TDMA) two big classes totally five kinds of technology.Wherein CDMA is the mainstream technology of generally acknowledging, comprises Frequency Division Duplexing (FDD) (FDD) and time division duplex (TDD) technology.The TD-SCDMA system is the flexible combination of TDMA and two kinds of basic transmission modes of CDMA, and (CWTS) proposes and obtain the wireless communication standard that ITU passes through by the China Wireless Telecommunication Standar tissue.This system is particularly suitable for providing in the urban population compact district the big capacity voice of high density, data and multimedia service.System can run separately, to satisfy the requirement of ETSI/UMTS and ITU/IMT-2000, also can be used with other wireless access technologys.
In the TD-SCDMA network, when mobile station MS or cell phone use Packet data service, send request or communication data to Serving GPRS Support Node (SGSN), SGSN adopts GPRS Tunnel Protocol (GTP) to send to GGSN (GGSN) after the packing data, is routed to the Internet network of user's request after GGSN unpacks the GTP packet and re-assembly.When TD-SCDMA provided the Packet data service of high QoS, its interconnectivity, opening and anonymity made that also the information of its propagation is very different, and information security issue can not be ignored.The packet filtering technology is the important topic in the information security, its basic principle is that the network data message is unpacked the legitimacy that detects judgment data, transmit control accordingly according to testing result, guarantee the fail safe of the network information, prevent and control propagation illegal, harmful information.Packet filtering need be checked respectively and filters usually heading and message body, existing mainstream technology is that five-tuple filters, extract the IP source address in the packet, the IP destination address, protocol type, application layer source port number and destination slogan, be used for the shunting and the filtration of IP packet, be packet filter firewall and router, do not track the user, and most packet filtering algorithm is (as Hicuts, Hierarchical Tries etc.) realize at software, do not consider the characteristics of hardware, and along with the raising of network speed and increasing of regular number, software processes speed relatively lags behind.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of 3G network packet filtering system and method based on FPGA at the defective that prior art exists.
The present invention adopts following technical scheme for achieving the above object:
The present invention is based on the 3G network packet filtering system of FPGA, it is characterized in that comprising EMAC stone module and user's processing logic module, wherein user's processing logic module comprises the controlling packet parsing module, two GTP packet parsing modules, the read-write control module, the characteristic information search engine, characteristic information memory module and two forwarding control modules, the controlling packet parsing module, the input of two GTP packet parsing modules connects the output of EMAC stone module respectively, the output of the one GTP packet parsing module connects the input that read-write control module and first is transmitted control module respectively, the input of the output termination read-write control module of controlling packet parsing module, the output of the 2nd GTP packet parsing module connects the input that read-write control module and second is transmitted control module respectively, the input of the output termination characteristic information search engine of read-write control module, the output of characteristic information search engine connects first respectively and transmits the input that control module and second is transmitted control module, the characteristic information search engine is connected with the characteristic information memory module is two-way, and first output of transmitting the control module and the second forwarding control module connects the input of EMAC stone module respectively.
The filter method of described 3G network packet filtering system based on FPGA is characterized in that comprising the processing method of controlling packet processing method and GTP packet, and wherein the controlling packet processing method comprises the steps:
A) controlling packet of all 3G packets on the link of the reception client-side interface reception gateway node GGSN of employing EMAC stone module and support node SGSN and data supervision subsystem;
B) controlling packet of the described data of step a supervision subsystem is extracted controlled characteristic information through the controlling packet parsing module, controlling packet parsing module and will inserting/deleted marker, IMSI/IP flag set;
C) adopt read-write control module detected characteristics information storage module,, then the described controlling features information of step b is passed to the characteristic information search engine when the characteristic information memory module is not carried out read operation;
D) the characteristic information search engine detects control signal corresponding:
1. work as and insert flag set, then whether respective memory locations is empty in the detected characteristics information storage module: (1) then ceases respective memory locations in the memory module with the described controlling features information stores of step b to reference when respective memory locations is sky; (2) when respective memory locations be not empty, then the base address is added that offset address obtains new address, returns new address to step (1) as memory address;
2. when deleted marker set, then whether the data of respective memory locations equate with data to be tested in the detected characteristics information storage module: (3) equate then this memory location content zero clearing when the data of memory location with data to be tested; (4) unequal when the data and the data to be tested of memory location, then the base address is added that offset address obtains new address, returns new address to step (3) as memory address;
The processing method of GTP packet comprises the steps:
E) with the described 3G packet of step a, promptly the GTP packet extracts the data characteristics information that obtains through GTP packet parsing module;
F) adopt the read-write control module that the described data characteristics information of step e is passed to the characteristic information search engine;
G) adopt the correction data and step e described data characteristics information contrast of characteristic information search engine with respective stored address in the characteristic information memory module: (5) equate that with the described data characteristics information of step e then employing forwarding control module abandons the packet of the described data characteristics information of step e correspondence when correction data; (6) do not wait when correction data and the described data characteristics information of step e, then the base address is added that offset address obtains new address, step (5) is returned as memory address in new address, when the described data characteristics information of correction data and step e does not wait for the second time, then adopt and transmit the packet that control module is transmitted the described data characteristics information of step e correspondence.
Beneficial effect of the present invention is as follows:
The 3G network packet filtering system that the present invention is based on FPGA is when interception, analysis and filter packets numeric field data bag, need extract characteristic information in the designated packet numeric field data bag, and search supervision and tabulate, realize the filtration of packet, tackle illegal user's data bag, and packet filtering system is series between SGSN and the GGSN group, and the handle packet of linear speed does not influence the communication of normal users.
The present invention mainly is based on on-site programmable gate array FPGA and realizes.Realized when the multi-user is online the supervision of communication user has been reached the high speed processing ability of 1.6Gbps.
The method that the present invention proposes has realized between SGSN, GGSN on the one hand to specifying the filtration of supervision user data package; On the other hand, cascade by network interface, can increase FPGA equipment expands, can increase the number of users that filter algorithm supports by this kind mode, have certain flexibility and upgradability, can be by on hardware of now having developed or software, revising a little, allow filter filter the application service of appointment or it is carried out flow restriction, and can be in the various data environments of packet domain gateway such as packet data serving node with filter application, the function that is similar to fire compartment wall is provided, and this filter method portable is used to different platforms, is particularly suited for hardware platform.So the 3G network packet filtering system and the method that the present invention is based on FPGA have suitable application prospects.
Description of drawings
Fig. 1 filter plant position view in supervisory systems;
Fig. 2 filter plant overall structure schematic diagram;
Fig. 3 filter plant user processing logic structural representation;
Fig. 4 GTP processing data packets flow chart;
Fig. 5 controlling packet process chart;
Fig. 6 characteristic information storage format preliminary treatment schematic diagram;
Fig. 7 characteristic information address slice is selected the computational methods schematic diagram;
Fig. 8 control data packet format.
Embodiment
On chip was selected, we had adopted the Virtex-5 LX50T field programmable gate array of Xilinx company, and its main hardware parameter is as follows:
Array is in the configurable logic block (CLB): 120 * 30; Slice is: 7200, comprise four LUT and four triggers among each slice; Maximum distribution formula RAM is: 480Kb;
Block RAM module is 2160Kb to the maximum
Ethernet mac number of modules: 4
RocketIO GTP transceiver number: 12, the speed of service is 100Mb/s~3.2Gb/s, the full duplex serial transceiver
I/O organizes sum: 15
Maximum user I/O number: 480
Be elaborated below in conjunction with the technical scheme of accompanying drawing to invention:
As shown in Figure 1, the position of the present invention in supervisory systems integral body as can be known, filter plant is series between SGSN, the GGSN, guarantee that the data link between SGSN and the GGSN is unobstructed, the disposal ability of filter plant will reach linear speed, promptly handling capacity and SGSN are suitable; The data that filter plant can be transmitted after handling are surrounded by two whereabouts: purpose GSN and reconstitution device; After the distributed data analytical system is carried out content analysis to legal user's data bag, illegal user's data bag is sent to data supervision subsystem, user profile is inserted database, and according to user's active state of this moment, send control commands corresponding and calculate child node to any one, the calculating child node is removed the TCP/IP head of control command, and the controlling packet of arranging form is sent to filter plant, and filter plant is operated supervising to tabulate according to corresponding order.
But custom IC IMSI unique identification user, this information is present in the user and links foundation for the first time, if stop the user to set up link once more, can store this characteristic information as filtering foundation; If illegal user has set up link and carried out data communication always, do not contain IMSI in the packet this moment, can filter according to the mobile IP corresponding with IMSI, as shown in table 1.
Table 1
Type of data packet The packet title Message Type Characteristic information
GTP-C Create PDP Context Request 16 IMSI
GTP-C Update PDP Context Request 18 IMSI
GTP-C PDU Notification Request 27 IMSI
GTP-U G-PDU 255 Mobile IP
The peripheral hardware that is adopted among the present invention with based on the connected mode of the filter plant of FPGA and filtration system internal structure as shown in Figure 2, the selection of physical layer interface can adjust according to the difference of peripheral hardware in the reality, GMII (Gigabit Media Independent Interface) can be operated under the 10/100/1000Mbps pattern of auto-negotiation, and RocketIO GTP transceiver can be operated in 100Mbps~3.75Gbps.The embedded ethernet MAC nuclear that EMAC provides for Xilinx, the packet that physical layer can be received is put into client with the form of whole frame and is received FIFO, user's processing logic uses interface to distinguish each packet by user logic, puts into client after handling accordingly and sends FIFO.
User's processing logic structural representation as shown in Figure 3, it is the core of finishing the 3G network Packet Filtering, receive the flow direction of the packet of being stored of FIFO according to client, the packet parsing module is connected to corresponding client and receives on FIFO and the transmission FIFO, carry out the parsing of packet according to corresponding operating process, finish the flow direction of packet and determine, and the reservation of the packet connector after will handling, join with recombination module.This part is to finish the main part of filtration, mainly comprise six parts: controlling packet parsing module, GTP packet parsing module, read-write control module, characteristic information search engine, characteristic information memory module, forwarding control module, wherein, the controlling packet parsing module, characteristic information extraction, the row operation of going forward side by side is delivered to the read-write control module with insertion, deleted marker and the storage format that calculates, base address, chip selection signal, the offset address of set.GTP (GPRS Tunneling Protocol) packet parsing module, judge the attribute of packet according to information type (Message type), the laggard row operation of characteristic information extraction is delivered to the read-write control module with storage format, base address, chip selection signal, the offset address that calculates.The read-write control module produces corresponding read-write and enables according to storage format, base address, chip selection signal, the offset address of the characteristic information of packet parsing module transmission, is delivered to the characteristic information search engine.The characteristic information search engine is carried out read-write operation according to the read-write enable signal and the control corresponding clock of read-write control module to the characteristic information memory module, and, comparison result is passed to the forwarding control module with data and the comparison of pending characteristic information that the characteristic information memory module is taken out.The read-write that the characteristic information memory module receives the transmission of characteristic information search engine enables, address information, carries out the read-write operation of characteristic information.The forwarding control module determines that according to the result of characteristic information search engine search the GTP packet is to continue to transmit or be dropped.
Concrete processing data packets flow process such as Fig. 4, shown in Figure 5.
1) processing of controlling packet
A) after new controlling packet arrives and receives FIFO, enter the controlling packet parsing module, insertion/deleted marker, IMSI (IMSI International Mobile Subscriber Identity that this module will reset according to the value of controlled flag position (FLAG), International Mobile Subscriber Identity)/the IP flag set, according to the sign characteristic information extraction, mode according to Fig. 6, Fig. 7 in the accompanying drawing is carried out computing to characteristic information, obtain storage format, base address, chip selection signal, the offset address of characteristic information, and communicate information to the read-write control module.
When b) the read-write control module detects new characteristic information and need store, detect the respective stored module and whether carrying out read operation, do not read to enable and switch clock if having read operation then produce; If read operation is arranged, wait for that then read operation finishes the back and switches clock, simultaneously, will read to enable, chip selection signal, base address be passed to the characteristic information search engine.
C) search engine detects control signal corresponding: whether 1. if insert flag set, then detecting respective memory locations is empty, and during for sky, generation is write and enabled, and switches to write port, and write operation is carried out in this address of characteristic information memory module; Then do not add that according to the base address offset address obtains new address for sky, read operation is carried out in this address, whether be empty, during for sky, generation is write and enabled if detecting respective memory locations, switch to write port, write operation is carried out in this address of characteristic information memory module, and address switchover is not to the base address when not being empty, and generation is write and enabled, switch to write port, write operation is carried out in this address of characteristic information memory module.2. as if deleted marker set, whether the data that then detect respective memory locations equate that with data to be tested when equating, generation is write and enabled, and switches to write port, this address of characteristic information memory module is carried out write Z-operation, that is, and the whole zero clearings of this memory cell; Unequally then add that according to the base address offset address obtains new address, read operation is carried out in this address, whether the data that detect respective memory locations equate with data to be tested, when equating, generation is write and is enabled, switch to write port, this address of characteristic information memory module is carried out write Z-operation, do not wait and then withdraw from operation; After operation is all over, enters the controlling packet parsing module and wait for that new controlling packet arrives.
2) processing of GTP packet
A) after new GTP packet arrives and receives FIFO, enter GTP packet parsing module, this module is divided into user communication data bag (GTP-U) and control signaling packet (GTP-C) according to the Message type of GTP protocol headers with packet, Message type 255 is judged to GTP-U, extracts mobile IP information wherein; Other Message type values are judged to GTP-C, Message type is 16,18,27 o'clock, extract IMSI information, after finishing, extraction characteristic information is carried out computing according to the mode of Fig. 6, Fig. 7, obtain storage format, base address, chip selection signal, the offset address of characteristic information, be passed to the read-write control module, other Message type packets are left intact, and are passed to the forwarding control module.
B) the read-write control module receives new data to be compared, produces and reads to enable, and will read the control clock (total SGSN->GGSN and GGSN->SGSN both direction) that clock switches to this communication link, the hunting action of controlling features information search engine.
C) the characteristic information search engine is carried out read operation according to base address and chip selection signal to the characteristic information memory module, data are taken out back and signal fusing to be detected, equal then set abandons sign, do not wait then and obtain new address according to base address and offset address, generation reads to enable to take out new data and signal fusing to be detected, equal then set abandons sign, do not wait then set to transmit sign, and sign is passed to the forwarding control module.
D) transmit control module and follow the flow direction that determines packet to be sent according to the sign as a result of comparison, transmit the packet of flag set and put into transmission FIFO, wait to be sent; The packet that abandons flag set is not put into transmit queue, turns back to GTP packet parsing module after operation is finished, and waits for that new GTP packet arrives.
Among Fig. 4, Fig. 5 relevant for account form such as Fig. 6, shown in Figure 7 of storage format, address and chip selection signal.The 64bits that the nibble of IMSI divide to be about to IMSI among Fig. 6 divides for one group according to 4bits, and the compression back is 32bits, and the 32bits of IP all stores, and does not carry out any processing.The address of IMSI and IP and sheet choosing are calculated and are all adopted method shown in Figure 7, and computing formula is as follows:
(A, B C) isolate signal A/B/C with Hash function H, m is an address size, and n is the chip selection signal figure place, obtains memory address address and chip selection signal chip_se behind the A/B/C combination XOR, step for the skew step-length, if address in data are arranged, with (address+step) as the address.
H(A,B,C)=A*2 24-m+B*2 24-m-n+C(A∈[0,2 m],B∈[0,2 n],C∈[0,2 24-m-n])
{address,chip_se}={A,B}^(~C)
(wherein, { } expression combination, ^ represents XOR ,~expression inverted sequence)
Even bit set in the step={ address computation part }.
The control data packet format as shown in Figure 8.
The form of controlling packet is appointed in advance by data supervision subsystem and FPGA filter plant, because data supervision subsystem needs long-range transmission supervision order, but building the ICP/IP protocol stack in FPGA can reduce processing speed and increase resource cost, so, data supervision subsystem reaches arbitrary earlier with control command and calculates child node, after destroying the ICP/IP protocol head, child node is sent to FPGA by calculating, because the first byte of the MAC Address of the network packet that the calculating child node transmits might repeat mutually with control signaling sign (FLAG), 12 bytes copy MAC Address to fill arbitrarily before the institute, and the 13rd byte is control signaling sign.Because the IP address is 4B, remaining 4B takes the strategy of filling arbitrarily.
Should be understood that, for those of ordinary skills, can preferred embodiments according to the present invention with and technical conceive make various possible changes or replacement, and all these changes or replace the protection range that all should belong to claims of the present invention.

Claims (3)

1, a kind of 3G network packet filtering system based on FPGA, it is characterized in that comprising EMAC stone module and user's processing logic module, wherein user's processing logic module comprises the controlling packet parsing module, two GTP packet parsing modules, the read-write control module, the characteristic information search engine, characteristic information memory module and two forwarding control modules, the controlling packet parsing module, the input of two GTP packet parsing modules connects the output of EMAC stone module respectively, the output of the one GTP packet parsing module connects the input that read-write control module and first is transmitted control module respectively, the input of the output termination read-write control module of controlling packet parsing module, the output of the 2nd GTP packet parsing module connects the input that read-write control module and second is transmitted control module respectively, the input of the output termination characteristic information search engine of read-write control module, the output of characteristic information search engine connects first respectively and transmits the input that control module and second is transmitted control module, the characteristic information search engine is connected with the characteristic information memory module is two-way, and first output of transmitting the control module and the second forwarding control module connects the input of EMAC stone module respectively.
2, a kind of filter method of the 3G network packet filtering system based on FPGA as claimed in claim 1 is characterized in that comprising the processing method of controlling packet processing method and GTP packet, and wherein the controlling packet processing method comprises the steps:
A) controlling packet of all 3G packets on the link of the reception client-side interface reception gateway node GGSN of employing EMAC stone module and support node SGSN and data supervision subsystem;
B) controlling packet of the described data of step a supervision subsystem is extracted controlled characteristic information through the controlling packet parsing module, controlling packet parsing module and will inserting/deleted marker, IMSI/IP flag set;
C) adopt read-write control module detected characteristics information storage module,, then the described controlling features information of step b is passed to the characteristic information search engine when the characteristic information memory module is not carried out read operation;
D) the characteristic information search engine detects control signal corresponding:
1. when inserting flag set, then whether respective memory locations is empty in the detected characteristics information storage module: (1) when respective memory locations for empty, then with the described controlling features information stores of step b respective memory locations to the characteristic information memory module; (2) when respective memory locations be not empty, then the base address is added that offset address obtains new address, returns new address to step (1) as memory address;
2. when deleted marker set, then whether the data of respective memory locations equate with data to be tested in the detected characteristics information storage module: (3) equate then this memory location content zero clearing when the data of memory location with data to be tested; (4) unequal when the data and the data to be tested of memory location, then the base address is added that offset address obtains new address, returns new address to step (3) as memory address;
The processing method of GTP packet comprises the steps:
E) be that the GTP packet extracts the data characteristics information that obtains through GTP packet parsing module with the described 3G packet of step a;
F) adopt the read-write control module that the described data characteristics information of step e is passed to the characteristic information search engine;
G) adopt the correction data and step e described data characteristics information contrast of characteristic information search engine with respective stored address in the characteristic information memory module: (5) equate that with the described data characteristics information of step e then employing forwarding control module abandons the packet of the described data characteristics information of step e correspondence when correction data; (6) do not wait when correction data and the described data characteristics information of step e, then the base address is added that offset address obtains new address, step (5) is returned as memory address in new address, when the described data characteristics information of correction data and step e does not wait for the second time, then adopt and transmit the packet that control module is transmitted the described data characteristics information of step e correspondence.
3, the filter method of the 3G network packet filtering system based on FPGA according to claim 2, it is characterized in that the parsing of GTP packet process GTP packet parsing module obtains user communication data bag GTP-U and control signaling packet GTP-C among the step e, GTP packet parsing module also extracts mobile IP information among the user communication data bag GTP-U and the IMSI information among the control signaling packet GTP-C, and mobile IP information and IMSI information are the composition data characteristic information.
CN2009100331431A 2009-06-15 2009-06-15 System and method for filtering 3G data packet based on FPGA Expired - Fee Related CN101572891B (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102387160A (en) * 2011-12-13 2012-03-21 曙光信息产业(北京)有限公司 System and method based on IP message quintuple filtering strategy
CN102497372A (en) * 2011-12-13 2012-06-13 曙光信息产业(北京)有限公司 System and method based on Internet protocol (IP) message destination port filtering strategy
CN102646084A (en) * 2012-03-06 2012-08-22 上海纳轩电子科技有限公司 Efficient network packet storage method implemented based on FPGA (field programmable gate array)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102387160A (en) * 2011-12-13 2012-03-21 曙光信息产业(北京)有限公司 System and method based on IP message quintuple filtering strategy
CN102497372A (en) * 2011-12-13 2012-06-13 曙光信息产业(北京)有限公司 System and method based on Internet protocol (IP) message destination port filtering strategy
CN102387160B (en) * 2011-12-13 2014-10-22 曙光信息产业(北京)有限公司 System and method based on IP message quintuple filtering strategy
CN102646084A (en) * 2012-03-06 2012-08-22 上海纳轩电子科技有限公司 Efficient network packet storage method implemented based on FPGA (field programmable gate array)

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