CN101572539A - Bias-voltage generating circuit for high-speed narrow-band voltage-controlled oscillators (VCO) - Google Patents
Bias-voltage generating circuit for high-speed narrow-band voltage-controlled oscillators (VCO) Download PDFInfo
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- CN101572539A CN101572539A CNA2009100436429A CN200910043642A CN101572539A CN 101572539 A CN101572539 A CN 101572539A CN A2009100436429 A CNA2009100436429 A CN A2009100436429A CN 200910043642 A CN200910043642 A CN 200910043642A CN 101572539 A CN101572539 A CN 101572539A
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Abstract
The invention discloses a bias-voltage generating circuit for high-speed narrow-band voltage-controlled oscillators (VCO). By using a common-source common-gate structure as a load of an amplifier, the bias circuit reduces the slope of output bias voltage Vbias of the amplifier relative to the changes of control voltage VC, enhances the control capability of the control voltage VC over the VCO, and ensures that the output bias voltage Vbias has small changes near a given voltage value, thereby reducing the output jitter of the VCO.
Description
Technical field
The present invention relates generally to the voltage controlled oscillator field in the narrow band phase lock loop circuit such as clock and data recovery, refers in particular to the bias-voltage generating circuit that is used for differential delay unit tail current source.
Background technology
(Voltage-Controlled-Oscillator VCO) is the key modules of phase-locked loop, clock data recovery circuit, clock generation circuit etc. to voltage controlled oscillator.Wherein, clock data recovery circuit requires frequency height, narrow bandwidth, and this just requires voltage controlled oscillator can be operated under the very high centre frequency, and has narrower frequency-tuning range, and promptly gain sensitivity is lower.
Be used for voltage controlled oscillator (VCO) the magnetic tape trailer current source the difference symmetric delay unit as shown in Figure 1, its structure is the differential inverter of a band balanced load, M21 pipe and M22 pipe are the difference input pipe of two symmetries, and for balance power consumption, the size of M21 and M22 pipe is identical.Their grid meets input IN+ and IN-respectively.And IN+ and IN-meet the output OUT-and the OUT+ of previous stage difference unit respectively, form loop configuration like this.There is a tail current source differential delay unit of this structure, is made up of the M20 pipe, and its grid meets a bias voltage Vbias.In order to guarantee that differential pair tube M21 and M22 are complementary, we must guarantee that tail current pipe M20 always works in saturation condition, i.e. Vbias-Vp＜V
TH, V
THThreshold voltage for the M20 pipe.Therefore, be necessary for tail current source an accurate bias voltage Vbias is provided.
Owing in the high-frequency clock data recovery circuit, require voltage controlled oscillator (VCO) to be operated near a certain higher frequency, in order to improve voltage controlled oscillator (VCO) noise resisting ability, require the gain sensitivity of voltage controlled oscillator lower, promptly require the control change in voltage scope of voltage controlled oscillator (VCO) bigger, and corresponding frequency change is less, this just requires bias voltage Vbias to change with the control voltage linear, and changes more smooth.In addition in order to improve the ability of voltage controlled oscillator (VCO) opposing power supply noise, need the variation that bias voltage can offset supply voltage, make that the frequency of oscillation of voltage controlled oscillator (VCO) is constant, thereby reduced the power supply noise sensitivity of voltage controlled oscillator (VCO), improved the jitter performance of voltage controlled oscillator (VCO).
For bias voltage being provided for voltage controlled oscillator (VCO), strengthen its antijamming capability simultaneously, adopt as Fig. 2 or biasing circuit shown in Figure 3 usually.Among Fig. 2 because the drain electrode of M14 is connected to the grid of half duplicate circuit current source M1 in the grid of left side feedback loop M10 and the right feedback loop simultaneously, make this biasing circuit when VC variation or mains voltage variations, the Vbias change in voltage is bigger, and Vbias can be very little when VC is very big, therefore this conventional biasing circuit makes Vbias very big with the Vc excursion, the clock jitter that can cause voltage controlled oscillator (VCO) like this is very big, and being not suitable for provides biasing to the voltage controlled oscillator in the high-speed narrow-band phase-locked loop (VCO).
In Fig. 3, because no start-up circuit, cause the circuit can't operate as normal probably, though have the advantage of simplifying circuit, but there is not feedback loop, make the inhibition poor ability of circuit, an accurately rational bias voltage can not be provided, also be not suitable for providing biasing certainly to the voltage controlled oscillator in the high-speed narrow-band phase-locked loop (VCO) to power supply noise.
Summary of the invention
The problem to be solved in the present invention just is: the technical problem at prior art exists provides a kind of bias-voltage generating circuit that is applicable to the voltage controlled oscillator (VCO) of high-speed narrow-band phase-locked loop.
For solving the problems of the technologies described above, the solution that the present invention proposes is: a kind of biasing circuit that is applicable to the voltage controlled oscillator (VCO) of high-speed narrow-band phase-locked loop, it is characterized in that: half duplicate circuit of differential delay load is made up of M1, M2, M3, M4, an output of amplifier is connected to the grid of M4, and another output output provides bias voltage Vbias; The start-up circuit of differential amplifier is made up of M5, M6, M7, M8, M9, and M10, M11, M12 formation bleeder circuit finally make the tail current pipe M13 of differential amplifier obtain a suitable current for the current mirror of M12, M13 provides bias voltage; M14, M15 are the difference input pipe of amplifier, and the grid of M14 meets VC, and M15 connects the drain electrode of M3; M16, M17, M18, M19 are the load of amplifier, and the source-drain electrode of M17, M18 links to each other; Wherein the drain electrode of M14 is connected to the grid of M10, M4 simultaneously, form two feedback loops, along with the VC inverse change, it is less to change slope simultaneously a proper voltage for assurance Vbias, guarantees that the tail current source bias voltage of the delay cell of voltage controlled oscillator (VCO) changes less; Dual feedback loops guarantees that circuit is when mains voltage variations in addition, Vbias also can respective change, the frequency that guarantees voltage controlled oscillator (VCO) is constant, thereby has strengthened the ability of the anti-power supply noise of voltage controlled oscillator (VCO), has improved the jitter performance of voltage controlled oscillator (VCO).
Compared with prior art, advantage of the present invention just is:
1, Vbias near a suitable magnitude of voltage with the VC inverse change, and the slope that changes is little, the control change in voltage that guarantees voltage controlled oscillator (VCO) tail current source is less, and voltage controlled oscillator (VCO) gain sensitivity is reduced, and reduces the output jitter of voltage controlled oscillator (VCO).
2, the dicyclo feedback loop guarantees circuit when mains voltage variations, and Vbias is respective change also, guarantees that the frequency of voltage controlled oscillator (VCO) is constant, thereby has strengthened the ability of the anti-power supply noise of voltage controlled oscillator (VCO).
3, the start-up circuit module of Zeng Jiaing can improve the reliability of voltage controlled oscillator (VCO).
Description of drawings
Fig. 1 is classical bias structure delay cell schematic diagram;
Fig. 2 is the offset generating circuit structural representation;
Fig. 3 is the offset generating circuit structural representation of not tape starting circuit;
Fig. 4 is improved bias structure differential delay cell schematics;
Fig. 5 is the structural representation of biasing circuit of the present invention.
Embodiment
Below with reference to accompanying drawing and concrete enforcement the present invention is described in further details.
As shown in Figure 5, the present invention is a kind of bias-voltage generating circuit that is applicable to the voltage controlled oscillator (VCO) of high-speed narrow-band phase-locked loop, it comprises metal-oxide-semiconductor M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, M17, M18 and M19.Wherein half duplicate circuit of differential delay load is made up of M1, M2, M3, M4, and an output of amplifier is connected to the grid of M4, and another output output provides bias voltage Vbias; The start-up circuit of differential amplifier is made up of M5, M6, M7, M8, M9, and M10, M11, M12 formation bleeder circuit finally make the tail current pipe M13 of differential amplifier obtain a suitable current for the current mirror of M12, M13 provides bias voltage; M14, M15 are the difference input pipe of amplifier, and the grid of M14 meets VC, and M15 connects the drain electrode of M3; M16, M17, M18, M19 are the load of amplifier, and the source-drain electrode of M17, M18 links to each other; Wherein the drain electrode of M14 is connected to the grid of M10, M4 simultaneously, form two feedback loops, along with the VC inverse change, it is less to change slope simultaneously a proper voltage for assurance Vbias, guarantees that the tail current source bias voltage of the delay cell of voltage controlled oscillator (VCO) changes less; Dual feedback loops guarantees circuit when mains voltage variations in addition, and Vbias also can respective change, guarantees that the frequency of voltage controlled oscillator (VCO) is constant, thereby has strengthened the ability of the anti-power supply noise of voltage controlled oscillator (VCO).
Finally realized when control voltage VC changes, can producing a bias voltage Vbias that variation is more smooth, realization is to the linear regulation of voltage controlled oscillator (VCO) in higher Frequency point and narrower frequency range, the bias voltage that has solved traditional biasing circuit changes greatly the problem with the noise inhibiting ability difference, the frequency jitter of reduction voltage controlled oscillator (VCO); Because the dicyclo feedback loop in this structure guarantees circuit when mains voltage variations, and Vbias is respective change also, guarantee that the frequency of voltage controlled oscillator (VCO) is constant simultaneously, thereby strengthened the ability of the anti-power supply noise of voltage controlled oscillator (VCO).
Claims (1)
1, a kind of bias-voltage generating circuit that is used for high-speed narrow-band voltage controlled oscillator (VCO) is characterized in that:
Half duplicate circuit 3 of differential delay load is made up of (M1), (M2), (M3), (M4), an output of amplifier is connected to the grid of (M4), another output output provides the start-up circuit 1 of bias voltage (Vbias) differential amplifier to be made up of (M5), (M6), (M7), (M8), (M9), (M10), to form bleeder circuit be that the current mirror of (M12), (M13) provides bias voltage for (M11), (M12), finally makes suitable current of tail current pipe (M13) acquisition of differential amplifier; (M14), (M15) be the difference input pipe of amplifier, grid (M14) meets (VC), (M15) connects the drain electrode of (M3); (M16), (M17), (M18), (M19) be the load of amplifier, (M17), the source-drain electrode of (M18) links to each other; Wherein the drain electrode of (M14) is connected to the grid of (M10), (M4) simultaneously, form two feedback loops, guarantee (Vbias) a proper voltage along with (VC) inverse change, it is less to change slope simultaneously, guarantees that the tail current source bias voltage of the delay cell of voltage controlled oscillator (VCO) changes less; Dual feedback loops guarantees that circuit is when mains voltage variations in addition, (Vbias) also can respective change, the frequency that guarantees voltage controlled oscillator (VCO) is constant, thereby has strengthened the ability of the anti-power supply noise of voltage controlled oscillator (VCO), has improved the jitter performance of voltage controlled oscillator (VCO).
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2009100436429A CN101572539A (en) | 2009-06-09 | 2009-06-09 | Bias-voltage generating circuit for high-speed narrow-band voltage-controlled oscillators (VCO) |
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| Application Number | Priority Date | Filing Date | Title |
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| CNA2009100436429A CN101572539A (en) | 2009-06-09 | 2009-06-09 | Bias-voltage generating circuit for high-speed narrow-band voltage-controlled oscillators (VCO) |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102270985A (en) * | 2010-06-07 | 2011-12-07 | 中国人民解放军国防科学技术大学 | Configurable differential delay unit circuit |
| CN102843131A (en) * | 2011-06-21 | 2012-12-26 | 中国科学院微电子研究所 | Annular voltage-controlled oscillator |
| CN103078634A (en) * | 2011-10-26 | 2013-05-01 | 瑞昱半导体股份有限公司 | Method and apparatus of common mode compensation for voltage controlled delay circuits |
| CN104601169A (en) * | 2014-11-25 | 2015-05-06 | 中国人民解放军国防科学技术大学 | Biasing circuit for achieving oscillating of voltage-controlled oscillator (VCO) in full working voltage range |
| CN106026975A (en) * | 2016-05-12 | 2016-10-12 | 中国电子科技集团公司第二十四研究所 | Self-biasing circuit |
| CN107547085A (en) * | 2016-06-28 | 2018-01-05 | 英特尔Ip公司 | Scaled for the bias voltage based on frequency of phaselocked loop |
| CN115276608A (en) * | 2022-09-23 | 2022-11-01 | 华南理工大学 | Ring oscillator and control method for constant output common mode voltage thereof |
-
2009
- 2009-06-09 CN CNA2009100436429A patent/CN101572539A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102270985A (en) * | 2010-06-07 | 2011-12-07 | 中国人民解放军国防科学技术大学 | Configurable differential delay unit circuit |
| CN102270985B (en) * | 2010-06-07 | 2013-03-06 | 中国人民解放军国防科学技术大学 | Configurable differential delay unit circuit |
| CN102843131A (en) * | 2011-06-21 | 2012-12-26 | 中国科学院微电子研究所 | Annular voltage-controlled oscillator |
| CN102843131B (en) * | 2011-06-21 | 2015-03-04 | 中国科学院微电子研究所 | Annular voltage-controlled oscillator |
| CN103078634A (en) * | 2011-10-26 | 2013-05-01 | 瑞昱半导体股份有限公司 | Method and apparatus of common mode compensation for voltage controlled delay circuits |
| CN103078634B (en) * | 2011-10-26 | 2015-08-26 | 瑞昱半导体股份有限公司 | Voltage controlled delay circuit and common mode compensation method thereof |
| CN104601169A (en) * | 2014-11-25 | 2015-05-06 | 中国人民解放军国防科学技术大学 | Biasing circuit for achieving oscillating of voltage-controlled oscillator (VCO) in full working voltage range |
| CN104601169B (en) * | 2014-11-25 | 2020-04-21 | 中国人民解放军国防科学技术大学 | Biasing circuit capable of realizing full-working-voltage-range oscillation of voltage-controlled oscillator |
| CN106026975A (en) * | 2016-05-12 | 2016-10-12 | 中国电子科技集团公司第二十四研究所 | Self-biasing circuit |
| CN106026975B (en) * | 2016-05-12 | 2019-02-15 | 中国电子科技集团公司第二十四研究所 | Auto bias circuit |
| CN107547085A (en) * | 2016-06-28 | 2018-01-05 | 英特尔Ip公司 | Scaled for the bias voltage based on frequency of phaselocked loop |
| CN115276608A (en) * | 2022-09-23 | 2022-11-01 | 华南理工大学 | Ring oscillator and control method for constant output common mode voltage thereof |
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