CN101561489A - Chip design method adopting multi-path parallel code phase search of satellite signals - Google Patents
Chip design method adopting multi-path parallel code phase search of satellite signals Download PDFInfo
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- CN101561489A CN101561489A CNA2009100689526A CN200910068952A CN101561489A CN 101561489 A CN101561489 A CN 101561489A CN A2009100689526 A CNA2009100689526 A CN A2009100689526A CN 200910068952 A CN200910068952 A CN 200910068952A CN 101561489 A CN101561489 A CN 101561489A
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Abstract
The invention relates to a chip design method adopting multi-path parallel code phase search of satellite signals, which comprises the following steps: firstly, storing a group of Nbit PN codes under the condition of acquisition treatment and then storing a group of Nbit PN codes again, namely storing two groups of the PN codes which are 2Nbit together; and secondly, inputting a group of data with the length of 2N and two groups of Nbit the PN codes into two sets of same slide-related circuits for parallel search operation, wherein each group of the PN codes completes the search of N code phases so as to realize two paths of parallel code phase search processes. The method has the advantages that the method can increase the unit time code phase search range and reduce the data storage frequency on the basis of properly increasing chip resources so as to improve the acquisition speed of a Big Dipper satellite baseband processing chip; and the method can greatly improve the performance of the whole chip by the addition of proper operating frequency of a system.
Description
Technical field
The present invention relates to receive and the capture technique field, relate to a kind of chip design method that adopts multi-path parallel code phase search of satellite signals especially in Big Dipper satellite signal.
Background technology
The method for designing of the general chip that is used for Big Dipper satellite signal capture all adopts the single channel search, promptly adopts one tunnel AD sampled data and PN sign indicating number to seek correlation peak and carries out catching of satellite-signal.This method has certain influence to satellite signal acquisition speed, but can improve acquisition speed by the clock work frequency that improves system; Yet, the clock work frequency of system also has certain limitation, too high system clock frequency of operation, sequential for chip design, power consumptions etc. all will be brought certain harmful effect, can reduce the chip manufacturing yield rate simultaneously, especially can not once finish and need repeatedly store under the data conditions in the search of all code phases, the simple frequency that improves can not significantly be improved acquisition speed, so can not rely on simple raising chip clock work frequency to solve acquisition speed.
Summary of the invention
At the deficiencies in the prior art, the objective of the invention is, a kind of chip design scheme that adopts multi-path parallel code phase search of satellite signals is provided, promptly on the basis that suitably increases resources of chip, increases unit interval code phase search scope, reduce the data storage number of times.
The common practices of satellite signal acquisition be local code and received signal are slided relevant, by the judgement peak value obtain correct code phase, then the adjusted local code of phase place is given tracking and other modules of back.The relevant portion that wherein slides realizes generally being divided into the relevant two kinds of methods of sliding after the relevant and data storage of real-time slip, when realizing slip correlation capturing Big Dipper signal, because Big Dipper signal code speed comparatively fast, so carries out Calculation Method again after more employing data storage.
For achieving the above object, the technical scheme that the present invention takes is: a kind of chip design method that adopts multi-path parallel code phase search of satellite signals comprises two-way slip interlock circuit, slip interlock circuit and threshold judgement circuit that circuit structure is identical in the chip circuit; It is characterized in that, after chip circuit captures Big Dipper satellite signal, one group of Nbit PN sign indicating number is deposited in after the RAM, store one group of Nbit PN sign indicating number again, two groups of PN sign indicating numbers that are total to 2Nbit promptly, be that the data (Data) of 2N are input to circuit structure identical two-way slip interlock circuit, slip interlock circuit with two groups of Nbit PN sign indicating numbers respectively and carry out parallel search operation then with a group length, every group of PN sign indicating number finished the search of N code phase, thereby realize the parallel code phase search process of two-way, its method comprises the steps:
Step 1: chip circuit captures Big Dipper satellite signal, deposits one group of Nbit PN sign indicating number in RAM earlier; Deposit another group Nbit PN sign indicating number in RAM again;
Step 2: same group of data (Data) signal 1 is sent into slip interlock circuit 4 and slip interlock circuit 5 respectively; Two groups of PN coded signals 2, PN coded signal 3 are sent into slip interlock circuit 4 and slip interlock circuit 5 respectively;
Step 3: by slip interlock circuit 4 make data (Data) signal 1, PN coded signal 2 multiply each other the back integration, the integral result that obtains enters thresholding decision circuit 6; By slip interlock circuit 5 make data (Data) signal 1, PN coded signal 3 multiply each other the back integration, the integral result that obtains enters thresholding decision circuit 6;
Step 4: catch the result by the threshold judgement circuit judges, the PN sequence phase state that output is corresponding is finished the parallel code phase search process of two-way.
The advantage of the inventive method is: can increase unit interval code phase search scope on the basis that suitably increases resources of chip, reduce the data storage number of times, thereby improve the acquisition speed of big-dipper satellite baseband processing chip, add suitable system works frequency, the performance of entire chip is increased substantially.
Description of drawings
Fig. 1, traditional single channel search routine figure;
Fig. 2, the relevant synoptic diagram of traditional single channel slip;
Fig. 3, two-way parallel search process flow diagram, and as Figure of abstract;
Fig. 4, two-way and the line slip synoptic diagram of being correlated with;
Embodiment
Describe implementation process of the present invention in detail below in conjunction with accompanying drawing:
The common practices of satellite signal acquisition be local code and received signal are slided relevant, by the judgement peak value obtain correct code phase, then the adjusted local code of phase place is given tracking and other modules of back.The relevant portion that wherein slides realizes generally being divided into the relevant two kinds of methods of sliding after the relevant and data storage of real-time slip, when realizing slip correlation capturing Big Dipper signal, because Big Dipper signal code speed comparatively fast, so carries out Calculation Method again after more employing data storage.
Sliding correlation method is to catch the most frequently used method, receiving system is when search is synchronous, its sign indicating number sequencer can slide over each other on phase place by time-delay or the method for quickening and the sign indicating number sequence of transmitter, only when detecting the phase place unanimity, just stop, be acquisition success, give subsequent module local PN sign indicating number.
Tradition single channel search as shown in Figure 1, the integral result that the PN sign indicating number only obtains one group of data (Data) and one group of PN sign indicating number (PN_1) enters threshold judgement, the result is caught in judgement.
Received signal data (Data) and the local PN sign indicating number back integration that multiplies each other is obtained their cross correlation value, then with a certain threshold value of threshold judgement circuit relatively, judge whether to capture useful signal; It has utilized the correlation properties of PN sign indicating number sequence, both when two identical sign indicating number sequence phases are consistent, its correlation output is maximum, and phase place when differing by more than 1/2nd chips correlation level off to 0, in case confirm to catch to finish, catch the synchronizing pulse control Search Control clock of indicator signal, adjust PN code weight complex frequency and phase place that the PN code generator produces, make it and the signal received keeps synchronously.
Fig. 2 is traditional single channel way of search, wherein PN sign indicating number memory length is N, data storage length is 2N, the PN sign indicating number slides in the direction of arrows successively then, after each the slip PN sign indicating number and the data of correspondence are carried out the correlation integral operation, up to sliding into dotted line position, so just finished search operation to N code phase.
Fig. 3 is a two-way parallel search process flow diagram, comprises data (Data) input signal 1, PN sign indicating number input signal 2, PN sign indicating number input signal 3, two-way slip interlock circuit 4, slip interlock circuit 5 and threshold judgement circuit 6 that its circuit structure is identical in the chip circuit; Carry out the parallel code phase search process of two-way by two slip interlock circuits 4,5.
(PN_1 PN_2) enters two slip interlock circuits of back to same group of data (Data), and the integral result that obtains enters threshold judgement simultaneously, judges and catches the result with two groups of PN sign indicating numbers respectively.
The multidiameter delay search as shown in Figure 4, many memory lengths are that the PN sign indicating number (PN_2) of N carries out same search operation on the single channel basis, because two dataway operations carry out simultaneously, therefore multidiameter delay can be searched for more code phase than single channel in the identical time, thereby improves whole search speed.
PN code data described above is the local pseudo-random code data that generate, the data that the DATA data obtain after for the signal AD conversion that receives from satellite.
According to the above description, in conjunction with industry technique known, can reproduce the present invention.
Claims (1)
1, a kind of chip design method that adopts multi-path parallel code phase search of satellite signals comprises the identical two-way slip interlock circuit (4) of circuit structure, slip interlock circuit (5), threshold judgement circuit (6) in the chip circuit; After it is characterized in that described chip circuit captures Big Dipper satellite signal, one group of Nbit PN sign indicating number is deposited in after the RAM, store one group of Nbit PN sign indicating number again, two groups of PN sign indicating numbers that are total to 2Nbit promptly, the data Data that with a group length is 2N then is input to the identical two-way slip interlock circuit (4) of circuit structure with two groups of Nbit PN sign indicating numbers respectively, slip interlock circuit (5) carries out the parallel search operation, every group of PN sign indicating number finished the search of N code phase, thereby realize the parallel code phase search process of two-way, its method comprises the steps:
Step 1: chip circuit captures Big Dipper satellite signal, deposits one group of Nbit PN sign indicating number in RAM earlier; Deposit another group NbitPN sign indicating number in RAM again;
Step 2: same group of data Data signal (1) sent into slip interlock circuit (4) and slip interlock circuit (5) respectively; Two groups of PN coded signals (2), PN coded signal (3) are sent into slip interlock circuit (4) and slip interlock circuit (5) respectively;
Step 3: by slip interlock circuit (4) make data Data signal (1), PN coded signal (2) multiply each other the back integration, the integral result that obtains enters thresholding decision circuit (6); By slip interlock circuit (5) make data Data signal (1), PN coded signal (3) multiply each other the back integration, the integral result that obtains enters thresholding decision circuit (6);
Step 4: the result is caught in threshold judgement circuit (6) judgement, and the PN sequence phase state that output is corresponding is finished the parallel code phase search process of two-way.
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103472469A (en) * | 2012-06-06 | 2013-12-25 | 东莞市泰斗微电子科技有限公司 | Pseudo code phase pipeline searching method in GNSS satellite signal capture |
CN107942354A (en) * | 2017-12-29 | 2018-04-20 | 中国电子科技集团公司第二十研究所 | A kind of quick capturing method for being used for satellite communication between standing |
CN109743100A (en) * | 2019-01-15 | 2019-05-10 | 北京理工大学 | The multi-user channel distribution method of capturing information based on Big Dipper short message system |
CN111830541A (en) * | 2020-06-19 | 2020-10-27 | 浙江时空道宇科技有限公司 | Satellite navigation receiving board card, device and system |
-
2009
- 2009-05-21 CN CNA2009100689526A patent/CN101561489A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103472469A (en) * | 2012-06-06 | 2013-12-25 | 东莞市泰斗微电子科技有限公司 | Pseudo code phase pipeline searching method in GNSS satellite signal capture |
CN103472469B (en) * | 2012-06-06 | 2015-09-23 | 泰斗微电子科技有限公司 | Pseudo code phase pipeline searching method in a kind of GNSS satellite signal capture |
CN107942354A (en) * | 2017-12-29 | 2018-04-20 | 中国电子科技集团公司第二十研究所 | A kind of quick capturing method for being used for satellite communication between standing |
CN109743100A (en) * | 2019-01-15 | 2019-05-10 | 北京理工大学 | The multi-user channel distribution method of capturing information based on Big Dipper short message system |
CN111830541A (en) * | 2020-06-19 | 2020-10-27 | 浙江时空道宇科技有限公司 | Satellite navigation receiving board card, device and system |
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Open date: 20091021 |