CN101551988B - Method of operating display in DPMS mode - Google Patents
Method of operating display in DPMS mode Download PDFInfo
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- CN101551988B CN101551988B CN2008100909470A CN200810090947A CN101551988B CN 101551988 B CN101551988 B CN 101551988B CN 2008100909470 A CN2008100909470 A CN 2008100909470A CN 200810090947 A CN200810090947 A CN 200810090947A CN 101551988 B CN101551988 B CN 101551988B
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Abstract
The invention relates to a method of operating a display in a DPMS mode, which is suitable to the operation of the display finishing a working mode and entering the DPMS mode. Under the DPMS mode, if a signal processor of the display senses that a connecting interface has no signal input, the signal processor enters a power-off state and informs a microcontroller to start the sensing function to sense if the connecting interface has single input or not, when not sensing the signal input within continuous time, the microcontroller enters a sleep state so as to achieve the purpose of saving electricity for the display.
Description
Technical field
The present invention relates to a kind of method that reduces power consumption of displays, refer to a kind of method that in the DPMS pattern, reduces power consumption of displays especially.
Background technology
At present, the display electricity-saving function is followed " Energy Star (Energy Star) " specification of Environmental Protection Agency usually, and meets the international (VESA of VESA; Video Electronics StandardsAssociation) " display power manage system standard (the DPMS that is formulated; Display Power ManagementStandard) " just qualified.Wherein, the display power manage system standard (DPMS) provide the display power manage system function, and during without any input signal, this function can protect screen to go forward side by side into battery saving mode to reduce the power that display was consumed at display.
General display power manage system is divided into four kinds of patterns: general (Normal), (Standby), DPMS and close (Off) pattern await orders.As table one, in these four kinds of patterns, the state that signal processor in the display and microcontroller are had nothing in common with each other, and display is also different in the power consumption of these four kinds of patterns.
Table one
General modfel is the mode of operation that display has picture output, the display of display such as liquid crystal display television by using, the different mode of operation of branch is arranged again under general modfel, as television mode and computer model etc., the signal source that different mode of operations is had nothing in common with each other, wherein, standby promptly is that all signal sources are closed, therefore, the existing signal processor of being responsible for detection signal also presents the pass electricity condition, to save power supply.In addition, when display when wherein a kind of mode of operation switches to another kind of mode of operation, display must carry out the switching of signal source, and in handoff procedure, display promptly enters the DPMS pattern, at this moment, display carries out signal detection to signal source, and when not detecting signal as yet, display does not have picture output usually, if detect signal, display promptly enters the mode of operation after the described switching and exports picture.
In the prior art, be to utilize signal processor to carry out the detecting of signal, therefore, in the DPMS pattern, signal processor still is in sleep state, and in order after detecting signal, to accelerate the output of picture, therefore microcontroller remains in duty, so that in described pattern, display still consumes certain electric weight, in case signal processor continues not detect signal, then the power consumption of DPMS pattern is just considerable.At this point, the consumes power that how more to reduce display in the DPMS pattern is to desire the problem of solution earlier for being familiar with this operator.
Summary of the invention
In order to solve the above problems, the present invention discloses the method for a kind of display at the DPMS mode operating, is to utilize microcontroller to cooperate logic gate, can allow display under the DPMS pattern, consumes same charge with standby.
The included step of method that the present invention discloses has: when the DPMS pattern, signal processor detecting connecting interface earlier has the no signal input, if the no signal input, signal processor notice microcontroller start signal detecting function is with the signal input of detecting connecting interface; Signal processor is carried out shutdown programm entering the pass electricity condition, and the notice microcontroller its enter the pass electricity condition; Microcontroller start signal detecting function, and detecting connecting interface have the no signal input; The pin position that microcontroller inspection logic gate is connected to microcontroller has or not potential change, and microcontroller is the potential change detecting connecting interface no signal input with this pin position; If no potential change, microcontroller check whether the pin position does not all have potential change in a schedule time; If the pin position does not all have potential change in this schedule time, then microcontroller enters sleep state, and waits for that potential change takes place in the pin position.
Hence one can see that, technological means of the present invention is when the DPMS pattern, if no signal input, signal processor then enters the pass electricity condition, and utilize microcontroller to replace signal processor detecting connecting interface that the no signal input is arranged, and in continuing for some time no signal when input, microcontroller enters sleep state, reaches purpose of power saving thus.
Above about content of the present invention explanation and the explanation of following embodiment be in order to demonstration with explain spirit of the present invention and principle, and provide patent claim of the present invention further to explain.
Description of drawings
Fig. 1 is a display system block scheme of the present invention;
Fig. 2 A is the DPMS mode operating process flow diagram of display of the present invention; And
Fig. 2 B is the DPMS mode operating process flow diagram of display of the present invention.
The main element symbol description:
10............................... display
101.............................. connecting interface
102.............................. logic gate
103.............................. microcontroller
104.............................. signal processor
The input of step 205 no signal, signal processor notice microcontroller start signal detecting function
The pin position that step 208 microcontroller inspection logic gate is connected to microcontroller has or not potential change
Embodiment
Below in embodiment, be described in detail detailed features of the present invention and advantage, its content is enough to make any related art techniques person of haveing the knack of to understand technology contents of the present invention and implements according to this, and according to the disclosed content of this instructions, claim and graphic, any related art techniques person of haveing the knack of can understand purpose and the advantage that the present invention is correlated with easily.
Hold feature as prior art, display of the present invention is supported four kinds of patterns of display power manage system: general, await orders, DPMS and " shut " mode", technological means of the present invention is to reduce the power consumption of described pattern with the start of the display that changes the DPMS pattern.Please refer to Fig. 1, be display 10 system block diagrams of the present invention, as shown in the figure, display 10 comprises electronic components such as connecting interface 101, logic gate 102, microcontroller 103 and signal processor 104, wherein, connecting interface 101 is coupled to logic gate 102 and signal processor 104, and microcontroller 103 is coupled to logic gate 102 and signal processor 104, and has electric signal transmission between the electronic component that each couples mutually at least.
The present invention utilizes microcontroller 103 to replace signal processor 104 detecting connecting interfaces 101 that the no signal input is arranged in the DPMS pattern, to reach display 10 purpose of power saving.About the DPMS mode operating flow process of display 10 of the present invention please refer to Fig. 2 A and Fig. 2 B, at the beginning, the user switches to second mode of operation (step 201) with display 10 from first mode of operation of general modfel, display 10 meeting FEFO first mode of operations also enter DPMS pattern (step 202), when the DPMS pattern, signal processor 104 is the signal source of detecting second mode of operation earlier, it is connecting interface 101, no signal input (step 203) is arranged, if the signal input is arranged, 10 of displays finish the DPMS pattern and enter second mode of operation, and the picture that signal processor 104 is handled second mode of operation shows (step 204); Hold step 203, if no signal input, signal processor 104 notice microcontrollers 103 start signal detecting functions, signal input (step 205) with detecting connecting interface 101, signal processor 104 is carried out shutdown programms entering the pass electricity condition, and notice microcontroller 103 its enter and close electricity condition (step 206).The program A of hookup 2A, microcontroller 103 start signal detecting functions, and detect the signal source of second mode of operation, it is connecting interface 101, no signal input (step 207) is arranged, the present invention utilizes logic gate 102 to connect microcontroller 103 and connecting interface 101, the pin position that 103 inspections of microcontroller logic gate 102 is connected to microcontroller 103 has or not potential change with detecting connecting interface 101 no signal input (step 208) to be arranged, if potential change is arranged, microcontroller 103 checks whether the potential change number of times reaches a predetermined value (step 209), if the potential change number of times reaches this predetermined value, microcontroller 103 start signal processors 104 then, and the operation workflow that continues is as (step 210) as described in the step 203; Hold step 209, if the potential change number of times do not reach this predetermined value, the operation workflow that then continues is as described in the step 208; Hold step 208, if no potential change, microcontroller 103 check whether the pin position does not all have potential change (step 211) in a schedule time, if the pin position does not all have potential change in this schedule time, then microcontroller 103 enters sleep state, and waits for that potential change (step 212) takes place in the pin position; Hold step 211, if there is potential change the pin position in this schedule time, the operation workflow that then continues is as described in the step 208.
According to a specific embodiment of the present invention, display 10 can be the display of a LCD TV, first mode of operation of its support can be television mode, second mode of operation can be computer model, the signal source of second mode of operation, be connecting interface 101, it can be D type (D-sub) connectivity port, digital visual interface (DVI; Digital Visual Interface), high picture quantity multimedia transmission interface (HDMI; High-DefinitionMultimedia Interface) or unified display interface (UDI; Unified Display Interface) a wherein type.
With D type connectivity port is example, the present invention be from D type connectivity port the tenth, the 11, the 13 and 14 pin positions pull out the pin position that signal wire is connected to logic gate 102 and signal processor 104, wherein the tenth and the 11 pin position belongs to the signal ground of horizontal synchronization (H-Sync), vertical synchronization (V-Sync) respectively; The 13 and 14 pin positions then are responsible for transmitting horizontal synchronization and vertical synchronizing signal respectively.In this embodiment, logic gate 102 is connected to the general I/O (GPIO of microcontroller 103; General PurposeInput/Output) pin position and output signal pin position so far, if this general I/O pin position is the electronegative potential activation, then logic gate 102 can be a NOR type logic gate, that is, when there is not the signal input D type connectivity port, the 13 and 14 pin positions are electronegative potential, and the general I/O pin position that then is connected to the microcontroller 103 of NOR type logic gate 102 outputs is a noble potential; On the other hand, when there was the signal input D type connectivity port, the 13 and 14 pin positions were noble potential, and NOR type logic gate is then exported electronegative potential, and at this moment, microcontroller 103 is enabled.
At the beginning, the user switches to computer model (as step 201) with display 10 from television mode, and display 10 meeting FEFO television modes also enter DPMS pattern (as step 202).When the DPMS pattern, signal processor 104 detecting D type connectivity port earlier has or not horizontal synchronization and vertical synchronizing signal input, promptly detecting the current potential that D type connectivity port is connected to the pin position of signal processor 104 has or not height to change (as step 203), if signal processor 104 has detected horizontal synchronization and vertical synchronizing signal input, 10 of displays finish the DPMS pattern and enter computer model, and the picture that signal processor 104 is handled computer model shows (as step 204); If signal processor 104 does not detect the signal input, signal processor 104 notice microcontrollers 103 start signal detecting functions are with the signal input (as step 205) of detecting D type connectivity port.
Afterwards, signal processor 104 is carried out shutdown programms entering the pass electricity condition, and notice microcontroller 103 its enter and close electricity condition (as step 206).Microcontroller 103 start signal detecting functions, and the output that sees through NOR type logic gate is imported (as step 207) with the signal of detecting D type connectivity port, the pin position that microcontroller 103 inspection NOR type logic gates are connected to microcontroller 103 has or not current potential just to change (as step 208), if NOR type logic gate output electronegative potential, there are horizontal synchronization and vertical synchronizing signal input in expression D type connectivity port, 103 of microcontrollers check whether current potential height change frequency reaches a predetermined value (as step 209), if current potential height change frequency reaches this predetermined value, microcontroller 103 start signal processors 104 then, and the operation workflow that continues is as (as step 210) as described in the step 203; Hold as step 209, if current potential height change frequency does not reach this predetermined value, the operation workflow that then continues is as described in the step 208; Hold as step 208, if no current potential just changes, microcontroller 103 checks whether the pin position does not all have current potential and just change (step 211) in a schedule time, if the pin position does not all have current potential and just changes in this schedule time, then microcontroller 103 enters sleep pattern from mode of operation, and waits for that the pin position current potential takes place just changes (as step 212); Hold step 211, if the pin position has current potential just to change in this schedule time, the operation workflow that then continues is as described in the step 208.
Though the present invention discloses as above with aforesaid embodiment, so it is not in order to limit the present invention.Without departing from the spirit and scope of the present invention, change of being done and retouching all belong to scope of patent protection of the present invention.Please refer to appended claim scope about the protection domain that the present invention defined.
Claims (7)
1. a display is in the method for DPMS mode operating, be applicable to that switching described display as a user desires to enter one second mode of operation from one first mode of operation, and described display finishes described first mode of operation and the running when entering described DPMS pattern, wherein, described first mode of operation is two kinds of different mode of operations that described display has picture output with second mode of operation, it is characterized in that, comprise the following steps:
Utilizing a signal processor to detect a connecting interface has or not corresponding to the input of the signal of described second mode of operation;
If described connecting interface no signal input, described signal processor is notified a microcontroller start signal detecting function;
The shutdown programm of carrying out described signal processor closes electricity condition to enter one;
Open the signal detection function of described microcontroller;
A pin position of checking described microcontroller has or not potential change;
If described pin position does not have potential change, described microcontroller checks whether described pin position does not all have potential change in a schedule time; And
If described pin position does not all have potential change in the described schedule time, then described microcontroller enters a sleep pattern, and waits for that potential change takes place in described pin position.
2. display as claimed in claim 1 is in the method for DPMS mode operating, it is characterized in that, described method is the described pin position that connects described connecting interface and described microcontroller with a logic gate, described logic gate is responded the signal input of described connecting interface, to produce the potential change of described pin position.
3. display as claimed in claim 1 is in the method for DPMS mode operating, it is characterized in that, detecting described connecting interface at described signal processor has or not in the step of importing corresponding to the signal of described second mode of operation, if described connecting interface has the signal input, described display finishes described DPMS pattern and enters described second mode of operation, and the picture of described second mode of operation of described signal processor processes shows.
4. display as claimed in claim 1 is characterized in that in the method for DPMS mode operating, has or not the step of potential change in the described pin position of checking described microcontroller, also includes:
If there is potential change described pin position, described microcontroller checks whether the potential change number of times reaches a preset value; And
If the potential change number of times reaches described preset value, described microcontroller is opened described signal processor, and described signal processor is detected the step that described connecting interface has the no signal input.
5. display as claimed in claim 4 is characterized in that in the method for DPMS mode operating if the potential change number of times does not reach described preset value, described microcontroller checks that described pin position has or not the step of potential change.
6. display as claimed in claim 1 is in the method for DPMS mode operating, it is characterized in that, check at described microcontroller whether described pin position does not all have in the step of potential change in the described schedule time, if there is potential change described pin position in the described schedule time, described microcontroller checks that described pin position has or not the step of potential change.
7. display as claimed in claim 2 is characterized in that in the method for DPMS mode operating described logic gate is a NOR type logic gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100909470A CN101551988B (en) | 2008-03-31 | 2008-03-31 | Method of operating display in DPMS mode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100909470A CN101551988B (en) | 2008-03-31 | 2008-03-31 | Method of operating display in DPMS mode |
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| Publication Number | Publication Date |
|---|---|
| CN101551988A CN101551988A (en) | 2009-10-07 |
| CN101551988B true CN101551988B (en) | 2011-09-21 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2008100909470A Expired - Fee Related CN101551988B (en) | 2008-03-31 | 2008-03-31 | Method of operating display in DPMS mode |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014075473A1 (en) * | 2012-11-14 | 2014-05-22 | 中兴通讯股份有限公司 | Energy-saving display method and device for terminal, lcd module, and terminal |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102010025884B3 (en) * | 2010-07-02 | 2011-07-07 | Siemens Aktiengesellschaft, 80333 | Method for operating processor used for robot in real time environment, involves generating auxiliary signal by timer corresponding to the expiration of difference interval by switching the operation mode |
| CN102346048A (en) * | 2010-08-02 | 2012-02-08 | 纬创资通股份有限公司 | Power-saving sensing device and method |
| KR20130006167A (en) * | 2011-07-08 | 2013-01-16 | 삼성전자주식회사 | Image display apparatus and method for controlling the image display apparatus |
| CN106339063B (en) * | 2016-08-26 | 2019-04-23 | 苏州佳世达电通有限公司 | A kind of display control circuit and control method |
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| US5736873A (en) * | 1994-05-19 | 1998-04-07 | Samsung Electronics Co., Ltd. | Power saving control circuit for a display apparatus |
| CN1206868A (en) * | 1997-06-16 | 1999-02-03 | 三星电子株式会社 | Computer system for controlling monitor screen display under powder source management mode |
| CN1501212A (en) * | 2002-11-15 | 2004-06-02 | Lg������ʽ���� | Power controlling system |
| CN100367344C (en) * | 2002-06-25 | 2008-02-06 | 富士通株式会社 | Display and power-saving controller |
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2008
- 2008-03-31 CN CN2008100909470A patent/CN101551988B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5736873A (en) * | 1994-05-19 | 1998-04-07 | Samsung Electronics Co., Ltd. | Power saving control circuit for a display apparatus |
| CN1206868A (en) * | 1997-06-16 | 1999-02-03 | 三星电子株式会社 | Computer system for controlling monitor screen display under powder source management mode |
| CN100367344C (en) * | 2002-06-25 | 2008-02-06 | 富士通株式会社 | Display and power-saving controller |
| CN1501212A (en) * | 2002-11-15 | 2004-06-02 | Lg������ʽ���� | Power controlling system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014075473A1 (en) * | 2012-11-14 | 2014-05-22 | 中兴通讯股份有限公司 | Energy-saving display method and device for terminal, lcd module, and terminal |
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| CN101551988A (en) | 2009-10-07 |
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