CN101546056A - Liquid crystal display and driving method of liquid crystal display panel - Google Patents
Liquid crystal display and driving method of liquid crystal display panel Download PDFInfo
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- CN101546056A CN101546056A CN200910137642A CN200910137642A CN101546056A CN 101546056 A CN101546056 A CN 101546056A CN 200910137642 A CN200910137642 A CN 200910137642A CN 200910137642 A CN200910137642 A CN 200910137642A CN 101546056 A CN101546056 A CN 101546056A
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Abstract
The present invention discloses a liquid crystal display and a driving method of liquid crystal display panel. The pixel array structure of liquid crystal display provided by the invention is a half source driving structure. The coupling relationship between each pixel and each data wire is arranged ingeniously thereby the pixel array structure of liquid crystal display provided by the invention is directly configured on a gate driver on the substrate of liquid crystal display panel for driving the liquid crystal display panel. Thus not only can the cost of liquid crystal display reduced, but also the mode of time schedule controller for controlling the gate driver and source driver can be reduced.
Description
Technical field
The invention relates to a kind of plane display technique, and particularly relevant for the driving method of a kind of LCD and display panels thereof.
Background technology
In the middle of the pel array of display panels (pixel array) structure now, there is a class to be called as half source drive (half source driving is designated hereinafter simply as HSD) framework.The HSD framework doubles by the number with sweep trace and makes the number of data line to reduce by half, and owing to the number of data line reduces by half, so the making price of source electrode driver (source driver) also can relatively reduce.
Fig. 1 illustrates the part synoptic diagram into a kind of display panels 100 of traditional HSD framework.The display panels 100 that Fig. 2 illustrates to Fig. 1 adopts the part of the panel driving technology of two-wire double-point inversion (two line two dot inversion) to drive sequential chart.Please merge with reference to Fig. 1 and Fig. 2, display panels 100 has a plurality of pixel Pix that arrange with matrix-style, the pixel Pix that wherein is marked with the symbol of R1, G1, B1, R2, G2, B2 is the viewing area AA that is positioned at display panels 100, and the pixel Pix of the symbol of the unmarked R1 of having, G1, B1, R2, G2, B2 is dummy pixel (dummy pixel), and the position is in the periphery of viewing area AA.
In addition, label S1～S4 is a data line; Label Sdum is the dummy data line; Label G1～G9 is a sweep trace; And label Gdum is illusory sweep trace.A plurality of control signal LD, POL, STVD, OE1～OE3, clock signal CLK that provided by time schedule controller (timing controller) are provided the driving sequential chart that Fig. 2 disclosed, and the video data SD that provided of source electrode driver (source driver).Wherein, control signal LD and POL are in order to the Controlling Source driver, and control signal STVD and OE1～OE3 are in order to control gate driver (gate driver).
Can know from Fig. 2 and to find out, time schedule controller must provide manner of execution comparatively complicated control signal STVD and OE1～OE3, be produced on Y side control panel (Y-Board to cause, do not illustrate) on gate drivers distinguished output scanning signal SS to sweep trace G1～G9, and provide control signal corresponding LD and POL more according to this, be produced on X side control panel (X-Board to cause, do not illustrate) on source electrode driver be able to the dotted arrow of Fig. 1 1. 2. 3. 4. the order of mark of passing through, and the video data SD of correspondence is write to each pixel Pix.
Based on above-mentioned as can be known be, though the display panels 100 that Fig. 1 disclosed can allow the number of data line reduce by half, thereby reduce the making price of source electrode driver, but can find from the driving sequential chart that Fig. 2 disclosed, it is quite complicated that the mode of time sequence controller grid driver and source electrode driver seems, and the line buffer of required use when must at least 3 of additional configuration in it being different from the driven panel (its because of source electrode driver with the dotted arrow of Fig. 1 pass through mark 1. 2. 3. 4. order contained the cause of 3 row pixels), use and keep in the required video data SD of per 3 row pixels respectively.In addition, in order will must on Y side control panel, to make the comparatively complicated gate drivers of circuit framework, thereby to make that the making price of gate drivers integral body can be drawn high significantly in response to such type of drive.
Summary of the invention
In view of this, the present invention proposes a kind of LCD, and the picture element array structure of its display panels is the HSD framework, and this display panels can directly be configured in the gate driver drive display panels on the substrate of display panels.
The present invention proposes a kind of LCD, and it comprises display panels.Wherein, display panels comprises multi-strip scanning line, many data lines, and a plurality of pixel of arranging with matrix-style.In an one exemplary embodiment of the present invention, i bar sweep trace couples (4j+1) individual and (4j+3) individual pixel of i row pixel, and i is the odd number positive integer, and j is more than or equal to 0 integer.(i+1) bar sweep trace couples (4j+2) individual and (4j+4) individual pixel of i row pixel.R bar data line couple (2r+1) row and (4k+1) of (2r+2) row pixel individual with (4k+2) individual pixel and (2r+3) row and (2r+4) row pixel (4k+3) individual with (4k+4) pixel, r, k are the integer more than or equal to 0.
The present invention provides a kind of driving method of display panels in addition, wherein display panels has a plurality of pixels of arranging with matrix-style, and described driving method comprises: between the first phase in during a picture of LCD, first sweep signal and second sweep signal to the (4i+1) row pixel (i is the integer more than or equal to 0) are provided simultaneously, use all pixels of opening in (4i+1) row pixel, and provide a plurality of first video datas accordingly to write to all pixels in (4i+1) row pixel respectively; And the second phase in during described picture, second sweep signal to the (4i+1) row pixel is provided, use all dual pixels of opening in (4i+1) row pixel, and provide a plurality of second video datas accordingly to write to all dual pixels in (4i+1) row pixel respectively.
The present invention provides a kind of driving method of display panels in addition, wherein display panels has a plurality of pixels of arranging with matrix-style, and described driving method comprises: between the first phase in during a picture of LCD, first sweep signal and second sweep signal to the i row pixel (i is a positive integer) are provided simultaneously, use all pixels of opening in the i row pixel, and provide a plurality of first video datas accordingly to write to all pixels in the i row pixel respectively; And the second phase in during described picture, second sweep signal and the 3rd sweep signal to the i row and (i+1) row pixel are provided respectively, use open in the i row pixel the odd or dual pixel in odd or dual pixel and (i+1) row pixel, and provide a plurality of second video datas accordingly to write to the odd or dual pixel in the i row pixel respectively.
Based on above-mentioned, the picture element array structure of the display panels of LCD provided by the present invention is the HSD framework, and, thereby make the display panels of LCD provided by the present invention be able to directly to be configured in the gate driver drive display panels on the substrate of display panels by the relation that couples between each pixel of ingenious arrangement and each data line.Thus, not only can reduce the making price of gate drivers integral body, and more can reduce the mode of time sequence controller grid driver and source electrode driver.
Will be appreciated that above-mentioned general description and following embodiment only are exemplary and illustrative, it can not limit the scope that institute of the present invention desire is advocated.
Description of drawings
Fig. 1 illustrates the part synoptic diagram into a kind of display panels 100 of traditional HSD framework;
The display panels 100 that Fig. 2 illustrates to Fig. 1 adopts the part of the panel driving technology of two-wire double-point inversion (two line two dotinversion) to drive sequential chart;
Fig. 3 illustrates the system block diagrams into the LCD 300 of the present invention's one one exemplary embodiment;
The display panels 301 that Fig. 4 illustrates to the present invention's one one exemplary embodiment adopts the part of the panel driving technology of two-wire double-point inversion to drive sequential chart;
Fig. 5 illustrates the driving method process flow diagram into the display panels of the present invention's one one exemplary embodiment.
Wherein Reference numeral is:
100: display panels
300: LCD
301: display panels
303: left gate drivers
305: right gate drivers
307: source electrode driver
309: time schedule controller
311: backlight module
Pix: pixel
AA: viewing area
S1～S4: data line
Sdum: dummy data line
G1～G9: sweep trace
Gdum: illusory sweep trace
LD, POL, STVD, OE1～OE3, VSTL, CKL, XCKL, VSTR, CKR, XCKR: control signal
CLK: clock signal
SS: sweep signal
SD: video data
FP: during the picture
1. 2. 3. 4.: the order that writes video data
T1～T8: during in during the picture
S501, S503: each step of driving method process flow diagram of the display panels of the present invention's one one exemplary embodiment
Embodiment
Now will the example of described one exemplary embodiment be described in the accompanying drawings in detail with reference to one exemplary embodiment of the present invention.In addition, all possibility parts, the identical or similar portions of element/member/symbology of use same numeral in graphic and embodiment.
Fig. 3 illustrates the system block diagrams into the LCD 300 of the present invention's one one exemplary embodiment.Please refer to Fig. 3, LCD 300 comprises display panels 301, left gate drivers 303, right gate drivers 305, source electrode driver 307, time schedule controller 309, and in order to the backlight module 311 of the required backlight of display panels 301 to be provided.Wherein, have multi-strip scanning line G1～G8 in the display panels 301 and (show 8 sweep traces among Fig. 3, but not as restriction), 1 dummy data line Sdum, many data line S1～S4 (show 1 dummy data line Sdum, 4 data lines among Fig. 3, but not as restriction), and a plurality of pixel Pix (being not restriction with the number of pixels that is illustrated among Fig. 3) that forms that arranges with matrix-style.
In this one exemplary embodiment, i bar sweep trace couples (4j+1) individual and (4j+3) individual pixel of i row pixel, and wherein i is the odd number positive integer, and j is more than or equal to 0 positive integer.(i+1) bar sweep trace couples (4j+2) individual and (4j+4) individual pixel of i row pixel.R bar data line couple (2r+1) row and (4k+1) of (2r+2) row pixel individual with (4k+2) individual pixel and (2r+3) row and (2r+4) row pixel (4k+3) individual with (4k+4) pixel, wherein r, k are for more than or equal to 0 positive integer (the 0th data line is the dummy data line Sdum among Fig. 3).
What deserves to be mentioned is that at this number of all sweep traces in the display panels 301 is an even number, and the number of all data lines in the display panels 301 is an odd number.Dummy data line Sdum couples (4k+3) individual and (4k+4) pixel of the 1st row and the 2nd row pixel, and a plurality of in the display panels 301 arrange the viewing area AA that the 1st row and the 2nd row pixel in the pixel that forms is not positioned at display panels 301 with matrix-style, that is to say, these pixels can be regarded as dummy pixel (dummy pixel), can be used for balanced load or consider the arrangement repeatability on the pel array and be provided with.
The pixel array architecture of the display panels 301 that is disclosed from Fig. 3 is half source drive (HSD) framework, so the number of sweep trace can double, and the number of data line can reduce by half.Also also because of so, because the number of data line reduces by half, so the making price of source electrode driver 307 can relatively reduce.
In addition, because the number of sweep trace can double, so if the mode that adopts tradition to make gate drivers on Y side control panel can increase cost of manufacture.In view of this, this one exemplary embodiment directly is formulated in left gate drivers 303 on the substrate (for example glass substrate) of display panels 301 with right gate drivers 305, and use the mode of bilateral driven sweep line, to reduce the making price of gate drivers integral body effectively.
Clearer, left side gate drivers 303 directly is configured in the side (for example left side) on the glass substrate of display panels 301, and couple the odd number bar sweep trace of display panels 301, provide first sweep signal to all the odd number bar sweep traces in all sweep traces in the display panels 301 in order to sequence.Wherein, the running of left gate drivers 303 is controlled by control signal VSTL, CKL, the XCKL that time schedule controller 309 is provided.
In addition, right gate drivers 305 directly is configured in the opposite side (for example right side) on the glass substrate of display panels 301, and couple the even number bar sweep trace of display panels 301, provide second sweep signal to all the even number bar sweep traces in all sweep traces in the display panels 301 in order to sequence.Wherein, the running of right gate drivers 305 is controlled by control signal VSTR, CKR, the XCKR that time schedule controller 309 is provided.Certainly, right gate drivers 305 also can be on the glass substrate that directly is configured in left gate drivers 303 the same sides.
Benly here be, the method that a left side gate drivers 303 and right gate drivers 305 directly are configured on the glass substrate of display panels 301 is preferably when the element of the pixel Pix that makes display panels 301, uses for example film (thin film), photoetching (photo), etching (etching) ... etc. technology be produced on the glass substrate simultaneously.
For the operation principles of LCD 300 will more clearly be described, the display panels 301 that Fig. 4 illustrates to the present invention's one one exemplary embodiment adopts the part of the panel driving technology of two-wire double-point inversion (two line two dotinversion) to drive sequential chart.Please merge with reference to Fig. 3 and Fig. 4, should find out easily from the drive waveforms figure that Fig. 4 disclosed, left side gate drivers 303 is controlled by control signal VSTL, CKL, XCKL and VSTR, CKR, the XCKR that time schedule controller 309 is provided respectively with right gate drivers 305, provides sweep signal SS to display panels 301 interior corresponding scanning line G1～G8 and intersect to cooperate with sequence.
In addition, source electrode driver 307 is controlled by control signal LD and the POL that time schedule controller 309 is provided at least, to provide corresponding video data SD to each data line S1～S4.Thus, source electrode driver 307 will be with the dotted arrow of Fig. 3 1. 2. 3. 4. the order of mark of passing through, and the video data SD of correspondence is write to each pixel Pix.
Clearer, (frame period during a picture of LCD 300, FP) T1 between Nei the first phase, time schedule controller 309 can be controlled a left side and right gate drivers 303 and 305 while output scanning signal SS to sweep trace G1 and G2 (i.e. the 1st row pixel), the active member of using in all pixel Pix that open in the 1st row pixel (for example is thin film transistor (TFT), TFT), and Controlling Source driver 307 provides the first video data SD of a plurality of correspondences, to write to all the pixel Pix in the 1st row pixel respectively.
Then, second phase T2 during same picture in the FP, time schedule controller 309 can be controlled a left side and right gate drivers 303 and 305 difference output scanning signal SS to sweep trace G2 and G3 (i.e. the 1st and the 2nd row pixel), use in active member (TFT) and the 2nd row pixel in all dual pixel Pix that open in the 1st row pixel the active member (TFT) in the odd pixel Pix, and Controlling Source driver 307 provides the second video data SD of a plurality of correspondences to write to all the dual pixel Pix in the 1st row pixel respectively.
Yet, because when second phase T2, right gate drivers 305 can't output scanning signal SS to sweep trace G4 (i.e. the 2nd row pixel), even if so the odd pixel Pix in the 2nd row pixel has been unlocked in second phase T2, a plurality of second video data SD that source electrode driver 307 is provided at this moment can not be written into all the pixel Pix in the 2nd row pixel yet.
Similarly, second phase T3 during same picture in the FP, time schedule controller 309 can be controlled a left side and right gate drivers 303 and 305 while output scanning signal SS to sweep trace G3 and G4 (i.e. the 2nd row pixel), use the active member (TFT) in all pixel Pix that open in the 2nd row pixel, and Controlling Source driver 307 provides the 3rd video data SD of a plurality of correspondences to write to all the pixel Pix in the 2nd row pixel respectively.
Then, T4 between the fourth phase during same picture in the FP, time schedule controller 309 can be controlled a left side and right gate drivers 303 and 305 difference output scanning signal SS to sweep trace G4 and G5 (i.e. the 2nd row and the 3rd row pixel), use the active member (TFT) in all dual pixel Pix that open in the 2nd row and the 3rd row pixel, and Controlling Source driver 307 provides the 4th video data SD of a plurality of correspondences to write to all the dual pixel Pix in the 2nd row pixel respectively.
Yet, during owing to T4 between the fourth phase, right gate drivers 305 can't output scanning signal SS to sweep trace G6 (i.e. the 3rd row pixel), even if so all the dual pixel Pix T4 between the fourth phase in the 3rd row pixel are unlocked, a plurality of the 4th video data SD that source electrode driver 307 is provided at this moment can not be written into all the pixel Pix in the 3rd row pixel yet.
Similarly, T5 between the fifth phase during same picture in the FP, time schedule controller 309 can be controlled a left side and right gate drivers 303 and 305 while output scanning signal SS to sweep trace G5 and G6 (i.e. the 3rd row pixel), use the active member (TFT) in all pixel Pix that open in the 3rd row pixel, and Controlling Source driver 307 provides the 5th video data SD of a plurality of correspondences to write to all the pixel Pix in the 3rd row pixel respectively.
Then, T6 during during same picture in the FP the 6th, time schedule controller 309 can be controlled a left side and right gate drivers 303 and 305 difference output scanning signal SS to sweep trace G6 and G7 (i.e. the 3rd row and the 4th row pixel), use active member (TFT) in the odd pixel Pix of institute that opens in the 3rd row pixel and the active member (TFT) in all the dual pixel Pix in the 4th row pixel, and Controlling Source driver 307 provides the 6th video data SD of a plurality of correspondences to write to the odd pixel Pix in the 3rd row pixel respectively.
Yet, during owing to T6 during the 6th, right gate drivers 305 can't output scanning signal SS to sweep trace G8 (i.e. the 4th row pixel), even if so all the dual pixel Pix T6 during the 6th in the 4th row pixel are unlocked, a plurality of the 6th video data SD that source electrode driver 307 is provided at this moment can not be written into all the pixel Pix in the 4th row pixel yet.
Similarly, T7 during during same picture in the FP the 7th, time schedule controller 309 can be controlled a left side and right gate drivers 303 and 305 while output scanning signal SS to sweep trace G7 and G8 (i.e. the 4th row pixel), use the active member (TFT) in all pixel Pix that open in the 4th row pixel, and Controlling Source driver 307 provides the 7th video data SD of a plurality of correspondences to write to all the pixel Pix in the 4th row pixel respectively.
Then, T8 during during same picture in the FP the 8th, time schedule controller 309 can a control left side (illustrate to sweep trace G8 and G9 with right gate drivers 303 and 305 difference output scanning signal SS, promptly the 4th be listed as and the 5th row pixel), use open in the 4th row pixel the odd pixel Pix in odd pixel and the 5th row pixel, and Controlling Source driver 307 provides the 8th video data SD of a plurality of correspondences to write to the odd pixel Pix in the 4th row pixel respectively.
Yet, during owing to T8 during the 8th, right gate drivers 305 can't output scanning signal SS (illustrate to sweep trace G10, i.e. the 5th row pixel), even if so the odd pixel Pix of the institute T8 during the 8th in the 5th row pixel has been unlocked, a plurality of the 8th video data SD that source electrode driver 307 is provided at this moment can not be written into all the pixel Pix in the 5th row pixel yet.
Similarly, during same picture during the 8th of FP the after the T8, time schedule controller 309 can be circulation with T1～T8 during the above-mentioned the first to the 8th, and a control left side and right gate drivers 303 and 305 and source electrode driver 307, write to per four row pixels with video data SD, till during next picture with correspondence.
For instance, FP during the same picture the 9th to the 16 during, time schedule controller 309 can a control left side and right gate drivers 303 and 305 and source electrode driver 307, write to the 5th row pixel to the 8 row pixels with video data SD with correspondence, wherein the 5th row are identical with the 2nd row pixel with the 1st row with the order that the 6th row pixel is written into corresponding video data SD, and the 7th row are identical with the 4th row pixel with the 3rd row with the order that the 8th row pixel is written into corresponding video data SD.
In addition, between the 17 to the 20 fourth phase of FP during the same picture, time schedule controller 309 can a control left side and right gate drivers 303 and 305 and source electrode driver 307, writes to the 9th row pixel to the 12 row pixels with the video data SD with correspondence, please the rest may be inferred, so repeat no more.
Based on as can be known above-mentioned, the picture element array structure of the display panels 301 of this one exemplary embodiment is the HSD framework, and, thereby make display panels 301 be able to directly to be configured in a left side on the glass substrate of display panels 301 and right gate drivers 303 and 305 drivings by the relation that couples between each pixel of ingenious arrangement and each data line.Thus, not only can reduce a left side and right gate drivers 303 and 305 making prices, and more can reduce time schedule controller 309 control left sides and right gate drivers 303 and 305 and the mode of source electrode driver 307.
In addition, because time schedule controller 309 can a control left side and right gate drivers 303 and 305 and source electrode driver 307, video data SD is write to one by one each row pixel.The line buffer (line buffer) of required use gets final product when therefore, only needing one of additional configuration to be different from the driven panel in the time schedule controller 309 of this one exemplary embodiment.By this, compared to prior art, the cost of the time schedule controller 309 of this one exemplary embodiment also can be reduced effectively.
Moreover, from driving sequential chart that Fig. 4 disclosed as can be seen, in order to the control signal POL that determines every driving polarity on data line S1～S4 only can be during a picture of LCD 100 the FP conversion once.In other words, the driving polarity of the received video data SD of the row of each in the display panels 301 pixels is that FP just changes once during a picture of LCD 100.Thus, the power consumption of source electrode driver 307 integral body can be reduced significantly.
Based on the content that above-mentioned one exemplary embodiment disclosed, below will converge the driving method of putting in order out a kind of display panels.
Fig. 5 illustrates the driving method process flow diagram into the display panels of the present invention's one one exemplary embodiment.Please refer to Fig. 5, the driving method of this one exemplary embodiment is suitable for driving the display panels with a plurality of pixels of arranging with matrix-style, and it comprises: between the first phase in during a picture of LCD, first sweep signal and second sweep signal to the i row pixel (i is a positive integer) are provided simultaneously, use all pixels of opening in the i row pixel, and provide a plurality of first video datas accordingly to write to all pixels (step S501) in the i row pixel respectively; And the second phase in during described picture, second sweep signal and the 3rd sweep signal to the i row and (i+1) row pixel are provided respectively, use open in the i row pixel the odd or dual pixel in odd or dual pixel and (i+1) row pixel, and provide a plurality of second video datas accordingly to write to the odd or dual pixel (step S503) in the i row pixel respectively.
In sum, the picture element array structure of the display panels of LCD provided by the present invention is the HSD framework, and by the relation that couples between each pixel of ingenious arrangement and each data line, thus make the display panels of LCD provided by the present invention be able to directly to be configured on the substrate of display panels gate driver drive it.Thus, not only can reduce the making price of gate drivers integral body, and more can reduce the mode of time sequence controller grid driver and source electrode driver.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (20)
1. a LCD is characterized in that, comprising:
One display panels comprises:
The multi-strip scanning line;
Many data lines; And
A plurality of pixels are arranged with matrix-style;
Wherein, i bar sweep trace couples (4j+1) individual and (4j+3) individual pixel of i row pixel, and i is the odd number positive integer, and j is the integer more than or equal to 0;
(i+1) bar sweep trace couples (4j+2) individual and (4j+4) individual pixel of i row pixel; And
R bar data line couple (2r+1) row and (4k+1) of (2r+2) row pixel individual with (4k+2) individual pixel and (2r+3) row and (2r+4) row pixel (4k+3) individual with (4k+4) pixel, r, k are the integer more than or equal to 0.
2. LCD as claimed in claim 1 is characterized in that, the number of those sweep traces is an even number.
3. LCD as claimed in claim 2 is characterized in that, also comprises:
One first grid driver directly is configured in the side on the substrate of this display panels, and couples the odd number bar sweep trace of those sweep traces, provides one first sweep signal of the odd number bar sweep trace of those sweep traces in order to sequence,
Wherein, this first grid driver and those pixels are for being produced on simultaneously on this substrate.
4. LCD as claimed in claim 3 is characterized in that, also comprises:
One second grid driver directly is configured on this substrate, and couples the even number bar sweep trace of those sweep traces, provides one second sweep signal of even number bar sweep trace in order to sequence,
Wherein, this second grid driver and those pixels are for being produced on simultaneously on this substrate.
5. LCD as claimed in claim 4 is characterized in that, this second grid driver correspondence is arranged on the same side of this first grid driver.
6. LCD as claimed in claim 4 is characterized in that, this second grid driver correspondence is arranged on the offside of this first grid driver.
7. LCD as claimed in claim 4 is characterized in that, each the row pixel in this display panels can receive the video data of a correspondence respectively by those data lines.
8. LCD as claimed in claim 7 is characterized in that, it is to change once during a picture of this LCD that one of this video data that each the row pixel in this display panels is received drives polarity.
9. LCD as claimed in claim 7 is characterized in that, also comprises:
The one source pole driver couples this display panels, provides this video data to those data lines in order to correspondence;
Time schedule controller couples and controls the running of this first grid driver, this second grid driver and this source electrode driver; And
One backlight module is in order to provide this display panels required backlight.
10. LCD as claimed in claim 1 is characterized in that, the number of those data lines is an odd number.
11. LCD as claimed in claim 10 is characterized in that, this display panels also comprises:
One illusory (dummy) data line, couple the 1st row and (4k+3) of the 2nd row pixel individual with (4k+4) pixel, wherein the 1st row is outside pixel is positioned at the 2nd row.
12. the driving method of a display panels is characterized in that, this display panels has a plurality of pixels of arranging with matrix-style, and this driving method comprises:
Between the first phase in during a picture of a LCD, one first sweep signal and one second sweep signal to the (4i+1) row pixel are provided simultaneously, use all pixels of opening in (4i+1) row pixel, and provide a plurality of first video datas accordingly to write to those pixels in (4i+1) row pixel respectively; And
Second phase in during this picture, this second sweep signal to the (4i+1) row pixel is provided, use all dual pixels of opening in (4i+1) row pixel, and provide a plurality of second video datas to write to those dual pixels in the i row pixel respectively accordingly, i is the integer more than or equal to 0.
13. the driving method of display panels as claimed in claim 12 is characterized in that, also comprises:
During this second picture, one the 3rd sweep signal to the (4i+2) row pixel is provided, use the odd pixel of opening in (4i+2) row pixel.
14. the driving method of display panels as claimed in claim 13 is characterized in that, also comprises:
Between the third phase in during this picture, the 3rd sweep signal and one the 4th sweep signal to the (4i+2) row pixel are provided simultaneously, use all pixels of opening in (4i+2) row pixel, and provide a plurality of the 3rd video datas accordingly to write to those pixels in (4i+2) row pixel respectively; And
Between the fourth phase in during this picture, the 4th sweep signal to the (4i+2) row pixel is provided, use all dual pixels of opening in (4i+2) row pixel, and provide a plurality of the 4th video datas accordingly to write to those dual pixels in (4i+2) row pixel respectively.
15. the driving method of display panels as claimed in claim 14 is characterized in that, also comprises:
During the 4th picture, one the 5th sweep signal to the (4i+3) row pixel is provided, use all dual pixels of opening in (4i+3) row pixel.
16. the driving method of display panels as claimed in claim 15 is characterized in that, also comprises:
Between the fifth phase in during this picture, the 5th sweep signal and one the 6th sweep signal to the (4i+3) row pixel are provided simultaneously, use all pixels of opening in (4i+3) row pixel, and provide a plurality of the 5th video datas accordingly to write to those pixels in (4i+3) row pixel respectively; And
During in during this picture the 6th, the 6th sweep signal to the (4i+3) row pixel is provided, use the odd pixel of opening in (4i+3) row pixel, and provide a plurality of the 6th video datas accordingly to write to those the strange pixels in (4i+3) row pixel respectively.
17. the driving method of display panels as claimed in claim 16 is characterized in that, also comprises:
During the 6th, one the 7th sweep signal to the (4i+4) row pixel also is provided, use all dual pixels of opening in (4i+4) row pixel.
18. the driving method of display panels as claimed in claim 17 is characterized in that, also comprises:
During in during this picture the 7th, the 7th sweep signal and one the 8th sweep signal to the (4i+4) row pixel are provided simultaneously, use all pixels of opening in (4i+4) row pixel, and provide a plurality of the 7th video datas accordingly to write to those pixels in (4i+4) row pixel respectively; And
During in during this picture the 8th, the 8th sweep signal to the (4i+4) row pixel is provided, use the odd pixel of opening in (4i+4) row pixel, and provide a plurality of the 8th video datas accordingly to write to those the strange pixels in (4i+4) row pixel respectively.
19. the driving method of display panels as claimed in claim 18 is characterized in that, it is to change once during this picture that one of this video data that each the row pixel in this display panels is received drives polarity.
20. the driving method of a display panels is characterized in that, this display panels has a plurality of pixels of arranging with matrix-style, and this driving method comprises:
Between the first phase in during a picture of a LCD, one first sweep signal and one second sweep signal to the i row pixel are provided simultaneously, use all pixels of opening in the i row pixel, and provide a plurality of first video datas to write to those pixels in the i row pixel respectively accordingly, i is a positive integer; And
Second phase in during this picture, this second sweep signal and one the 3rd sweep signal to the i row and (i+1) row pixel are provided respectively, use the odd or dual pixel in the institute of opening in the i row pixel odd or dual pixel and (i+1) row pixel, and provide accordingly a plurality of second video datas with write to respectively in the i row pixel those very or dual pixels.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN200910137642A CN101546056A (en) | 2009-04-27 | 2009-04-27 | Liquid crystal display and driving method of liquid crystal display panel |
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| CN101777302A (en) * | 2010-03-04 | 2010-07-14 | 友达光电股份有限公司 | Display circuit for monitor and monitor |
| CN102081900A (en) * | 2010-12-27 | 2011-06-01 | 友达光电股份有限公司 | Display device |
| CN102116953A (en) * | 2010-12-30 | 2011-07-06 | 友达光电股份有限公司 | Liquid crystal display and liquid crystal display panel thereof |
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| CN102778797A (en) * | 2012-08-07 | 2012-11-14 | 深圳市华星光电技术有限公司 | Array substrate and liquid crystal display panel |
| CN105096886A (en) * | 2015-07-22 | 2015-11-25 | 友达光电股份有限公司 | Display and driving method thereof |
| CN105096886B (en) * | 2015-07-22 | 2017-11-17 | 友达光电股份有限公司 | Display and driving method thereof |
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