CN101533370B - Memory abnormal access positioning method and device - Google Patents
Memory abnormal access positioning method and device Download PDFInfo
- Publication number
- CN101533370B CN101533370B CN200910058902XA CN200910058902A CN101533370B CN 101533370 B CN101533370 B CN 101533370B CN 200910058902X A CN200910058902X A CN 200910058902XA CN 200910058902 A CN200910058902 A CN 200910058902A CN 101533370 B CN101533370 B CN 101533370B
- Authority
- CN
- China
- Prior art keywords
- access
- memory
- instruction
- access instruction
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000015654 memory Effects 0.000 title claims abstract description 116
- 230000002159 abnormal effect Effects 0.000 title claims abstract description 65
- 238000000034 method Methods 0.000 title claims abstract description 22
- 230000006399 behavior Effects 0.000 claims abstract description 42
- 238000012544 monitoring process Methods 0.000 claims abstract description 20
- 230000000875 corresponding effect Effects 0.000 claims description 26
- 230000009471 action Effects 0.000 claims description 11
- 230000006870 function Effects 0.000 description 14
- 230000008569 process Effects 0.000 description 7
- 238000012545 processing Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
Images
Landscapes
- Debugging And Monitoring (AREA)
- Storage Device Security (AREA)
Abstract
The embodiment of the invention discloses a memory abnormal access positioning method and a device, wherein, the memory abnormal access positioning method comprises the following steps of: monitoring the memory in which the abnormal access occurs, and capturing an access behavior; acquiring an access command in accordance with the access behavior, and positioning the access behavior through the access command; analyzing the access command to obtain an analysis result; and taking the place of the access command to accomplish corresponding operations in accordance with the analysis result. By the embodiment of the invention, efficient positioning can be implemented on the memory abnormal access.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a method and an apparatus for locating abnormal memory access.
Background
MIPS (microprocessor without Interlocked Pipeline Stages) is a CPU architecture, and a CPU adopting the MIPS architecture is called an MIPS CPU. MIPS CPUs are widely used in the fields of broadband devices, wireless networks, portable game machines, digital cameras, digital televisions, and the like.
In a development and scheduling stage of an MIPS CPU, a problem of memory abnormal access exists, where the memory abnormal access refers to that, in a program running process, a certain instruction (or a certain section of code) reads and writes a memory beyond a normal read-write range, and modifies other memories which do not belong to the normal read-write range, and is generally related to problems of memory boundary crossing, memory leakage and the like. When the memory abnormal access phenomenon occurs, the program is usually normal when the program just starts to run, but in the running process, when an instruction wants to normally read and write a memory area with the abnormal access phenomenon, the memory area is illegally modified because of the abnormal access problem, so the program can make an error. For this reason, the memory abnormal access phenomenon has the characteristics of strong concealment, difficulty in positioning and the like.
In the prior art, a memory exception access is generally searched and located by configuring a watchh register set or a JTAG register set to monitor a memory address, for example, referring to fig. 1, which includes the following steps:
1) a configuration register set for capturing access behavior;
2) the system is normally executed;
3) when accessing the monitored memory address, saving the register group;
the instruction that generated the access can be viewed by saving the register set.
4) And resetting the system.
In the process of implementing the invention, the inventor finds that the prior art has at least the following disadvantages:
when accessing the monitored memory address, the system generates an exception, after the exception is processed and returned, the program continues to execute the instruction generating the exception, so that the exception is entered again, and the system can only be reset and the access instruction cannot be captured and analyzed continuously due to the repeated circulation. Meanwhile, because the probability of the occurrence of the memory abnormal access phenomenon is very low, in practice, the access to the monitored memory address is normal access under most conditions, at this time, the instructions analyzed and checked in the prior art are often normal instructions, and thus the illegal access instructions causing the memory abnormal access phenomenon cannot be effectively positioned.
Disclosure of Invention
The embodiment of the invention provides a memory abnormal access positioning method and device, which are used for effectively positioning the memory abnormal access phenomenon and are realized by the following scheme:
monitoring the memory with abnormal access, and capturing access behavior;
obtaining an access instruction according to the access behavior, and positioning the access behavior through the access instruction;
analyzing the access instruction to obtain an analysis result;
and according to the analysis result, replacing the access instruction to complete corresponding action.
And the number of the first and second groups,
the monitoring unit is used for monitoring the memory with abnormal access and capturing access behaviors;
the acquisition unit is used for acquiring an access instruction according to the access behavior and positioning the access behavior through the access instruction;
the analysis unit is used for analyzing the access instruction to obtain an analysis result;
and the replacing unit is used for replacing the access instruction to complete corresponding actions according to the analysis result.
The technical scheme has the following advantages that:
by continuously checking the access instruction and analyzing the access instruction, the abnormal access of the memory can be effectively and timely positioned; and the corresponding action is completed instead of the access instruction, so that the condition that the system needs to be reset is avoided, the program can be continuously executed, and the abnormal access of the memory can be continuously positioned.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic flow chart of an embodiment of the method of the present invention;
FIG. 2 is a schematic flow chart of an embodiment of the method of the present invention;
FIG. 3 is a schematic structural diagram of an embodiment of the apparatus of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to specific embodiments and accompanying drawings.
An embodiment of the present invention provides a method for locating abnormal memory access, which is used to effectively locate abnormal memory access, and referring to fig. 1, the method includes the following steps:
s101, monitoring a memory with abnormal access, and capturing access behaviors;
the memory with abnormal access can be monitored by configuring relevant register sets (such as a WATCH register set or a JTAG register set), and when instructions access the monitored memory, the access behaviors of the instructions are captured.
S102, obtaining an access instruction according to the access behavior, and positioning the access behavior through the access instruction;
when the memory is monitored by configuring the WATCH register group, the access instruction can be obtained by inquiring the EPC register; or,
when monitoring memory by configuring the JTAG register set, the access instruction may be obtained by querying the DEPC register.
S103, analyzing the access instruction to obtain an analysis result;
analyzing characteristics of the access instruction that may affect the register and/or the memory when the access instruction is executed may analyze at least one of the following aspects:
determining the type of the access instruction;
analyzing the bit width operated by the access instruction;
analyzing whether the offset of the register is used;
check if the access instruction is in a delay slot, etc.
And S104, replacing the access instruction to complete corresponding actions according to the analyzed result.
Specifically, the register and/or the memory related to completing the action of the access instruction is modified according to the analyzed result, so that the corresponding action can be completed instead of the access instruction, and the program can be continuously executed.
The embodiment of the invention can also comprise:
analyzing and acquiring the access times of the access instruction, checking the access instruction according to the order of the access times from few to many, and positioning the abnormal access of the memory more quickly; because the probability of an abnormal access occurring is low, it is usually normal access behavior with multiple accesses.
According to the embodiment of the invention, the access instruction is continuously checked and analyzed, so that abnormal access of the memory can be effectively and timely positioned; and the corresponding action is completed instead of the access instruction, so that the condition that the system needs to be reset is avoided, the program can be continuously executed, and the abnormal access of the memory can be continuously positioned. Meanwhile, the access instructions are checked from the order of few access times to many access times, and abnormal access of the memory can be positioned more quickly.
Referring to fig. 2, a flow chart of another embodiment of the present invention includes the following steps:
s201, monitoring the memory with abnormal access, and capturing access behaviors;
the memory area with abnormal access is determined in advance, and in order to locate the memory abnormal access, the memory with abnormal access needs to be monitored to capture the access behavior, namely which instructions access the memory.
Monitoring the memory with abnormal access requires configuring the relevant register set in order to capture the access behavior when the memory access occurs, where the access behavior may include reading and writing the memory or some execution action such as instruction fetching. The related register set may be a WATCH register set or a JTAG register set, for example: the WATCHLO and WATCHHI registers of the WATCH register set may be set and then monitored. When the specified access policy is satisfied, the CPU sets the ExcCode field in the Cause Register to 23, which indicates that the specified access behavior occurs, and jumps to the exception handling code section, thereby capturing the access behavior. The exception handling code segment is a code segment defined and added in advance, and the specific implementation of the exception handling code segment can be different according to the needs of a program, for example, some processing can be performed on memory access exceptions or Cache exceptions.
S202, obtaining an access instruction to obtain an instruction address;
an access instruction refers to an instruction that accesses the memory being monitored. When capturing access behaviors in step S101, it is necessary to acquire addresses of these access instructions that generate the access behaviors. The address to fetch the access instruction may be obtained by querying the associated register, such as by querying an EPC register when capturing access behavior using a WATCH register set. The EPC register is a 64-bit register that holds the address at which the program continues to execute after an exception, and in the event of an access action, the value in the EPC register is the address of the instruction that caused the access action. By capturing access behavior if the JTAG register set is used, the address of the instruction may be obtained by querying the DEPC register.
S203, acquiring the access times of the access instruction;
in the captured access behavior, some accesses are abnormal accesses causing abnormal accesses to the memory; in most cases, normal access is often performed, and the same access instruction may be repeatedly accessed for multiple times, and in this case, the access times of the repeated access instructions can be recorded, which has the advantages that: when the instructions are analyzed subsequently, the analysis can be started from the instructions with less access times, because the access times are less, the probability that abnormal access causes abnormal access of the memory is high, and the instructions are more favorably and quickly positioned.
It should be noted that this step is not a necessary step in the embodiments of the present invention, but is an preferable scheme, and by adding the acquisition of the instruction access times, the instruction causing the memory exception access can be located more quickly.
S204, positioning a function causing abnormal memory access according to the instruction address;
after the address of the access instruction is obtained in step S202, the function where the access instruction is located can be found by looking up the binary file of the program, and if the function is found to be originally not to access the monitored memory, the function is a function that causes abnormal access to the memory.
For example, in the memory assignment function memset (), the first argument is a pointer to the memory first address to be assigned. Assuming that the address of the access instruction is obtained in step S202, and the access behavior is found by looking up the program binary file, which is caused by the memset () function, it can be analyzed whether the first argument of the memset () is error, and if there is no error, it indicates that this is a normal access; on the contrary, if the parameter is found to have a problem, for example, the pointer value has been changed, or becomes a wild pointer with an uncertain value, the access is an abnormal access, that is, the function causing the memory abnormal access is located because the first parameter setting error of the memset () function causes the memory abnormal access, and then the occurrence of the memory abnormal access phenomenon can be avoided by modifying the corresponding parameter.
S205, analyzing the access instruction to obtain an analysis result;
in step S204, the instruction causing the memory access exception is located, but the program is in the exception handling (see step S201, the program jumps to the exception handling when the program has the set access behavior to the monitored memory), and in order to continue the execution of the program, the access instruction needs to be analyzed to obtain an analysis result.
The analysis of the access instruction specifically includes: modifying the register and/or the memory related to completing the action of the access instruction so as to complete the corresponding action instead of the access instruction, and then needing to complete the corresponding action by replacing the access instruction so as to enable the program to continue to execute completely.
Analyzing the access instructions may include at least one of:
1) determining the type of the access instruction;
determining the type of instruction being accessed may be aware of the operation of the instruction on memory or registers. If the instruction type is a LOAD type instruction (LOAD instruction), it can be known that the instruction LOADs the value of the memory into the register; or the instruction type is a STORE type instruction, it can be known that the instruction loads the register value into the memory.
2) Analyzing the bit width operated by the access instruction;
in the MIPS instruction, some instructions can operate only one byte (8 bits), and some instructions can operate one Half Word (16 bits); there are also instructions that can operate on a Word (16 bits) or Double Word (64 bits) that require analysis of which case the access instruction belongs to.
3) Analyzing whether a register-based offset is used;
some instructions (e.g., LOAD type instructions or STORE type instructions) operate on a memory or a register using a register-based offset, such as an lw (LOAD word) instruction in LOAD type instructions, which is used to LOAD a word (signed) from the memory into the register, occupying 32 bits of storage space, wherein the 0 th bit to the 15 th bit are register-based offsets. The analysis of the remaining instructions may refer to the relevant MIPS definitions, which are not described herein.
4) Checking whether the access instruction is in a Delay Slot;
during the execution of a MIPS Pipeline (Pipeline), a conditional branch (conditional branch) usually cannot immediately determine whether to jump; at this point, for the pipeline to function properly, the MIPS pipeline first executes another instruction (or instructions) that is not dependent on the conditional branch, as if a slot is formed between the conditional branch instruction and its jump destination instruction for execution of the other instruction, this slot being referred to as a delay slot.
Checking whether the instruction is in the delay slot, specifically by querying a BD bit in a Cause Register; if the BD bit is 1, the instruction is in the delay slot; otherwise, the instruction is not located in the delay slot.
If the access instruction is in the delay slot, the last instruction is a conditional branch, i.e. there is a jump instruction. When the program returns from the exception processing, the next instruction of the access instruction is not executed, but the jump instruction is executed, but the program executes the instruction in the delay slot due to the existence of the delay slot, and then executes the jump instruction after the exception processing returns, so that the program can generate dead loop repeatedly. In order to prevent this, it is necessary to analyze which instruction is the next instruction of the jump instruction, and then to perform the purpose of jumping to the next instruction instead of the jump instruction.
If the access instruction is not located in the delay slot, there will be no such occurrence of a dead loop, and the program will then execute the next instruction of the access instruction, and therefore, only the access instruction needs to be analyzed.
S206, replacing the access instruction to complete corresponding actions according to the analysis result;
after analyzing the instruction function through step S205, the corresponding action may be performed instead of accessing the instruction according to the analysis result. An instruction may need to modify a register associated with the instruction if it is to perform a corresponding action, or may need to modify the contents of memory associated with the accessed instruction if it is to perform an operation on memory.
In this step, the register related to completing the action of the access instruction is modified, so that the corresponding action can be completed instead of the access instruction, and the program can continue to execute normally.
Taking the function to be completed instead of the LOAD type instruction (such as instructions LW, LL, LWR, etc.) as an example, because the LOAD type instruction needs to read data from the memory into the register, and the operation performed by the access instruction can be known through the analysis in step S105, the value of the corresponding memory can be read according to the analysis result in step S105, and the value of the corresponding register can be changed to replace the function to be completed by the LOAD type instruction. It should be noted that, in practice, some other registers need to be modified according to the function and purpose of the instruction, such as modifying an EPC register, so that the next instruction is executed after the present instruction is executed.
Corresponding actions are completed by replacing access instructions, so that the program can be continuously and normally executed, the condition that the system needs to be reset is avoided, and normal services are not influenced while abnormal access of the memory is positioned.
S207, continuing to monitor the set memory area;
the monitoring of the memory is continued, the access behavior is obtained, and if the access behavior occurs, the execution is continued from step S202.
According to the embodiment of the invention, the access instruction is continuously checked and analyzed, so that abnormal access of the memory can be effectively and timely positioned; and the corresponding action is completed instead of the access instruction, so that the condition that the system needs to be reset is avoided, the program can be continuously executed, and the abnormal access of the memory can be continuously positioned. Meanwhile, the access instructions are checked from the order of few access times to many access times, and abnormal access of the memory can be positioned more quickly.
Referring to fig. 3, an embodiment of the present invention further provides a memory exception access positioning apparatus 30, including:
a monitoring unit 301, configured to monitor a memory with abnormal access and capture an access behavior;
an obtaining unit 302, configured to obtain an access instruction according to the access behavior, and locate the access behavior through the access instruction;
an analyzing unit 303, configured to analyze the access instruction to obtain an analysis result;
and a replacing unit 304, configured to replace the access instruction to complete a corresponding action according to the analysis result.
The monitoring unit 301 may monitor the memory accessed abnormally by configuring a related register set (e.g., a WATCH register set or a JTAG register set), and when an instruction accesses the related memory, an access behavior occurs, and at this time, the system may change some bits in the related register (e.g., a case register) to capture the access behavior.
The obtaining unit 302 is further configured to:
when monitoring the memory by configuring a WATCH register group, querying an EPC register to obtain the access instruction; or,
when monitoring the memory by configuring the JTAG register set, the DEPC register is queried to obtain the access instruction.
When an access action occurs, the program jumps to the exception handling code, and the fetch unit 302 may fetch the address of the access instruction by querying an EPC register or a DEPC register in which the address of the access instruction that caused the access action is stored.
The memory abnormal access positioning device 30 further includes:
a counting unit 305, configured to obtain access times of the access instruction, and view the access instruction according to an order of the access times from a few to a large number, so that memory abnormal access can be located faster.
Because the monitored memory is accessed not only by abnormal accesses but also by normal accesses, and the normal accesses are often the most. In order to quickly locate the access instruction generating the abnormal access, the access times of each instruction can be counted by the counting unit 305, and the access times are checked according to the sequence from a few to a large number, so that the probability that the abnormal instruction is checked first is higher, and the abnormal access of the memory is favorably and quickly located.
The analyzing unit 303 is further configured to:
analyzing the characteristics of the access instruction that may affect the register and/or the memory when the access instruction is executed, and at least the following units may be further included:
a type analysis unit for determining a type of the access instruction; or,
a bit width analysis unit, configured to analyze a bit width operated by the access instruction; or,
an offset analyzing unit for analyzing whether a register-based offset is used; or
And the delay slot analysis unit is used for checking whether the access instruction is in the delay slot.
The replacement unit 304 is further configured to:
modifying registers and/or memory associated with performing the access instruction action so that the corresponding action can be performed in place of the access instruction.
In order to avoid the problem of system reset caused by the fact that the program processes the exception return, the access instruction causing the exception needs to be replaced to complete corresponding actions, so that the program can be continuously executed, and the access instruction is continuously checked in the execution process, so that the instruction causing the memory exception access is effectively positioned.
According to the embodiment of the invention, the access instruction is continuously checked and analyzed, so that abnormal access of the memory can be effectively and timely positioned; and the corresponding action is completed instead of the access instruction, so that the condition that the system needs to be reset is avoided, the program can be continuously executed, and the abnormal access of the memory can be continuously positioned. Meanwhile, the access instructions are checked from the order of few access times to many access times, and abnormal access of the memory can be positioned more quickly.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above-mentioned preferred embodiments, further illustrating the objects, technical solutions and advantages of the present invention, should be understood that the above-mentioned are only preferred embodiments of the present invention and should not be construed as limiting the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A memory abnormal access positioning method is characterized by comprising the following steps:
monitoring the memory with abnormal access, and capturing access behavior;
obtaining an access instruction according to the access behavior, and positioning the access behavior through the access instruction;
analyzing the access instruction to obtain an analysis result; the step of analyzing the access instruction comprises:
analyzing characteristics of the access instruction that may affect the register and/or the memory when the access instruction is executed, wherein the analyzing at least comprises:
determining a type of the access instruction; or,
analyzing the bit width operated by the access instruction; or,
analyzing whether a register-based offset is used; or,
checking whether the access instruction is in a delay slot;
and according to the analysis result, replacing the access instruction to complete corresponding action.
2. The method according to claim 1, wherein the step of obtaining the access instruction according to the access behavior comprises:
when monitoring the memory by configuring a WATCH register group, querying an EPC register to obtain the access instruction; or,
when monitoring the memory by configuring the JTAG register set, the DEPC register is queried to obtain the access instruction.
3. The memory abnormal access location method of claim 1, further comprising:
and acquiring the access times of the access instructions, and viewing the access instructions according to the order of the access times from few to many.
4. The method according to claim 1, wherein the step of performing the corresponding action instead of the access command according to the analysis result comprises:
modifying registers and/or memory associated with performing the access instruction action so that the corresponding action can be performed in place of the access instruction.
5. A memory exception access locating apparatus, comprising:
the monitoring unit is used for monitoring the memory with abnormal access and capturing access behaviors;
the acquisition unit is used for acquiring an access instruction according to the access behavior and positioning the access behavior through the access instruction;
the analysis unit is used for analyzing the access instruction to obtain an analysis result; the analysis unit is further configured to analyze, when the access instruction is executed, characteristics of a register and/or a memory that are affected by the access instruction, and at least one of the following units is further included;
a type analysis unit for determining a type of the access instruction;
a bit width analysis unit, configured to analyze a bit width operated by the access instruction;
an offset analyzing unit for analyzing whether a register-based offset is used;
a delay slot analyzing unit for checking whether the access instruction is in the delay slot;
and the replacing unit is used for replacing the corresponding action of completing the access instruction according to the analysis result.
6. The memory access location device of claim 5, wherein the fetch unit is further configured to:
when monitoring the memory by configuring a WATCH register group, querying an EPC register to obtain the access instruction; or,
when monitoring the memory by configuring the JTAG register set, the DEPC register is queried to obtain the access instruction.
7. The memory abnormal access locating device of claim 5, further comprising:
and the counting unit is used for acquiring the access times of the access instruction and checking the access instruction according to the order of the access times from less to more so as to position the abnormal access of the memory more quickly.
8. The memory access location device of claim 5, wherein the replacement unit is further to:
modifying registers and/or memory associated with performing the access instruction action so that the corresponding action can be performed in place of the access instruction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910058902XA CN101533370B (en) | 2009-04-09 | 2009-04-09 | Memory abnormal access positioning method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910058902XA CN101533370B (en) | 2009-04-09 | 2009-04-09 | Memory abnormal access positioning method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101533370A CN101533370A (en) | 2009-09-16 |
| CN101533370B true CN101533370B (en) | 2011-10-26 |
Family
ID=41103986
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910058902XA Expired - Fee Related CN101533370B (en) | 2009-04-09 | 2009-04-09 | Memory abnormal access positioning method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101533370B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102866951B (en) * | 2012-09-21 | 2015-07-15 | 武汉烽火网络有限责任公司 | Rapid positioning method of internal storage boundary crossing errors of embedded system |
| CN105988905A (en) * | 2015-02-12 | 2016-10-05 | 中兴通讯股份有限公司 | Exception processing method and apparatus |
| CN105893166A (en) * | 2016-04-29 | 2016-08-24 | 浪潮电子信息产业股份有限公司 | Method and device for processing memory errors |
| CN107220181B (en) * | 2017-06-16 | 2020-01-14 | 瑞斯康达科技发展股份有限公司 | Abnormal process positioning method, device and system |
| TWI648620B (en) * | 2017-08-07 | 2019-01-21 | 慧榮科技股份有限公司 | Memory device and operation instruction error processing method |
| CN109788352A (en) * | 2018-12-25 | 2019-05-21 | 深圳市纽格力科技有限公司 | A kind of set-top box exception confirmation method and system based on MIPS framework |
-
2009
- 2009-04-09 CN CN200910058902XA patent/CN101533370B/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN101533370A (en) | 2009-09-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7788535B2 (en) | Means and method for debugging | |
| US8769504B2 (en) | Method and apparatus for dynamically instrumenting a program | |
| JP4617405B2 (en) | Electronic device for detecting defective memory, defective memory detecting method, and program therefor | |
| US8930657B2 (en) | Method and apparatus for realtime detection of heap memory corruption by buffer overruns | |
| US8250543B2 (en) | Software tracing | |
| CN101533370B (en) | Memory abnormal access positioning method and device | |
| US8533681B2 (en) | Atomicity violation detection using access interleaving invariants | |
| CN107315961B (en) | Program vulnerability detection method and device, computing equipment and storage medium | |
| US9639451B2 (en) | Debugger system, method and computer program product for utilizing hardware breakpoints for debugging instructions | |
| CN104281805A (en) | Secure protection method and processor | |
| CN111338864B (en) | Memory problem detection method, device, computer equipment and storage medium | |
| US20070226471A1 (en) | Data processing apparatus | |
| CN112965845A (en) | Delay analysis method, electronic device, and storage medium | |
| CN111666102A (en) | File format conversion method, chip verification method, related device and network chip | |
| CN114253825B (en) | Memory leak detection method, device, computer equipment and storage medium | |
| US20130124925A1 (en) | Method and apparatus for checking a main memory of a processor | |
| JP7049275B2 (en) | Diagnostic data capture | |
| JP2001306334A (en) | Emulation device | |
| CN113220334B (en) | Program fault positioning method, terminal equipment and computer readable storage medium | |
| CN117891509B (en) | Data access method, device, computer equipment and storage medium | |
| CN113157513B (en) | Heap memory damage detection method and device, electronic equipment and storage medium | |
| US11989572B2 (en) | Computer system enabled with runtime software module tracking | |
| US20240248734A1 (en) | Computer system enabled with runtime software module tracking | |
| CN109885402B (en) | Method for testing function output data overflow, terminal equipment and storage medium | |
| CN117573207A (en) | Bit reversal detection method, device, electronic equipment and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: HUAWEI DIGITAL TECHNOLOGY (CHENGDU) CO., LTD. Free format text: FORMER NAME: CHENGDU HUAWEI SYMANTEC TECHNOLOGIES CO., LTD. |
|
| CP01 | Change in the name or title of a patent holder |
Address after: 611731 Chengdu high tech Zone, Sichuan, West Park, Qingshui River Patentee after: Huawei Symantec Technologies Co., Ltd. Address before: 611731 Chengdu high tech Zone, Sichuan, West Park, Qingshui River Patentee before: Chengdu Huawei Symantec Technologies Co., Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20111026 Termination date: 20170409 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |