CN101521825B - Image processor and method thereof - Google Patents
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- CN101521825B CN101521825B CN2008100823060A CN200810082306A CN101521825B CN 101521825 B CN101521825 B CN 101521825B CN 2008100823060 A CN2008100823060 A CN 2008100823060A CN 200810082306 A CN200810082306 A CN 200810082306A CN 101521825 B CN101521825 B CN 101521825B
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Abstract
The invention provides an image processor which comprises an input unit and a direct-current input-simulating front-end circuit. The invention does not arrange capacitors in the input unit and positioners in the direct-current input-simulating front-end circuit. By selecting appropriate comparative voltage and adding a voltage converter or a compensating circuit, the invention can still achieve the purpose of generating correct digital signals.
Description
Technical field
The present invention is relevant for display system, especially relevant for a kind of image processing apparatus and method thereof.
Background technology
The analog front circuit of conventional display system is divided into two big classes, the first kind is the used analog front circuit of LCD controller (liquid crystal display controller) that does not need decoder (decoder), in order to receive from the redness (R) of display card (VGA card) output of computer, green (G), blue (B) three image analoging signals.Second class is the used analog front circuit of video (video) decoder that needs decoder, in order to receive the signal that is transmitted from harmony device (tuner) or digital video video disc player video data origin systems such as (DVD player).And the above-mentioned signal that is transmitted from the video data origin system is divided into following three kinds of video formats: first kind is the AV terminal signal, only comprises a CVBS holding wire; Second kind is the S terminal signals, comprises Y (brightness), C (color) two signal line; The third is the aberration terminal signals, comprises Y, Pr, Pb three signal line.
Analog front circuit all can use the mechanism of AC coupled (AC coupling) and clamped (clamping) traditionally, R, G, B image analoging signal with the feed-in of display card institute are example, the DC level of those signals (DC level) is because can't be by the ac coupling capacitor in the input unit, so analog front circuit must utilize embedded device to come the DC level of reconstructed image analog signal.Generally speaking, AC coupled and clamped mechanism are the DC level for the reconstructed image analog signal, its shortcoming is that the reconstruction of DC level needs a period of time could stablize (settle down) usually, variation that can't immediate response image analoging signal DC level.
According to the type of the image analoging signal that analog front circuit received, the structure of embedded device can be divided into following two kinds:
First kind is the voltage-type embedded device, generally be applicable to handle R, G, B image analoging signal, or Y, Pr, Pb aberration terminal signals.The voltage-type embedded device is by a switch SW connection reconstruction voltage V
ResForm, and the conducting of switch SW is controlled by clamped signal with closing.When the switch SW conducting, restore voltage V
ResCan charge to V to ac coupling capacitor
ResCurrent potential.
Second kind is to be the current mode embedded device, generally is applicable to handle Y, Pr, Pb aberration terminal signals, AV terminal signal and S terminal signals.The current mode embedded device is connected to current source I_up respectively by switch SW 1, the SW2 of two serial connections and current source I_dn is formed, and the conducting of switch SW 1 is controlled with closing by clamped signal clamp_up, the conducting of switch SW 2 and close by clamped signal clamp_dn and controlled.Circuit designers can be set up a direct voltage by the pulse bandwidth of adjusting clamped signal clamp_up, clamp_dn at two tie points that are connected in series switch with the ON time point, and the voltage of this tie point charges to a preset potential to ac coupling capacitor again.
In fact, no matter any kenel embedded device is set, so long as combine the image processing apparatus of AC coupled mechanism, will exist can't the immediate response image analoging signal the problem that changes of DC level.Even, when image analoging signal is included as synchronously at green (synchronization on green, SOG) during signal, many branches of meeting in the circuit, this branch comprise ac coupling capacitor with synchronously at green circuit, and synchronously after green circuit receives image analoging signal SOG, utilize built-in automatic embedded device (auto-clamper) to rebuild after the DC level of SOG image analoging signal, acquisition and output synchronizing signal wherein, this synchronizing signal that captures is the mixed signal HS+VS of horizontal-drive signal HS and vertical synchronization VS signal.So in fact SOG branch has also used AC coupled and clamped mechanism, therefore have equally can't immediate response image analoging signal SOG the problem that changes of DC level.
Traditionally in the analog front circuit except using above-mentioned AC coupled and clamped mechanism, usually the input buffer of also can arranging in pairs or groups uses, with a data buffering, and prevent that the DC level that image analoging signal has been rebuild from being pulled away as the image analoging signal of rebuilding DC level.And this input buffer is finished by analog circuit, and the characteristic of input buffer is input impedance (impedance) infinity, output has very strong actuating force, yet in analog front circuit input buffer is set and the problem that produces is: the circuit with input buffer of high input impedance is difficult for design.
In order to solve in the clamped mechanism operation, the reconstruction of DC level needs a period of time to stablize, the variation of DC level that can't the immediate response image analoging signal is also for the problem of the difficult design that solves the high input impedance input buffer, so propose the present invention.
Summary of the invention
Because the problems referred to above, purpose of the present invention needs a period of time to stablize for a kind of image processing apparatus is provided with the reconstruction that solves the signal DC level, and the high input impedance input buffer is difficult for the problem of design.
For reaching above-mentioned purpose, image processing apparatus of the present invention is in order to receiving at least one image analoging signal, and produces at least one digital signal, and this image processing apparatus comprises input unit and direct current input analog front circuit.Input unit is in order to receive this image analoging signal, and wherein, this input unit does not comprise capacitor.Direct current input analog front circuit is to be electrically connected (Coupled To) this input unit, wherein this direct current input analog front circuit comprises at least one change-over circuit, an energy gap reference circuits and a clock generator, each change-over circuit comprises an analog-to-digital converter at least, and each change-over circuit does not all comprise embedded device.Wherein, this analog-to-digital converter comprises two inputs, in order to receiving this image analoging signal and comparative voltage from this input unit respectively, and converts the voltage difference of this two input to this digital signal according to clock signal.Wherein, this energy gap reference circuits produces reference voltage, to offer this analog-to-digital converter, in order to adjust full width voltage or bias current.Wherein, this clock generator is in order to produce the usefulness of this clock signal as sampling.And wherein, this reference voltage that this energy gap reference circuits produces is in order to the size of dynamic adjustment comparative voltage.
For reaching above-mentioned purpose, the present invention also provides a kind of image processing method, includes: receive at least one image analoging signal; Adjust the DC level of aforementioned image analoging signal; According to clock signal, convert the voltage difference of this image analoging signal and comparative voltage to digital signal; This digital signal is carried out clamped computing, to produce compensated digital signal; And dynamically adjust this comparative voltage.
In the first embodiment of the present invention, each change-over circuit comprises electric pressure converter (level shifter) and analog-to-digital converter, and electric pressure converter is in order to adjust the DC level of aforementioned image analoging signal.In the of the present invention second and the 3rd embodiment, each change-over circuit comprises analog-to-digital converter and compensating circuit.Compensating circuit among second embodiment is according to aforementioned clock signal and clamped signal, and digital signal is carried out clamped computing to produce compensating signal.In the 3rd embodiment, when direct current input analog front circuit receives SOG or SOY image analoging signal, after analog-to-digital converter is converted into SOG or SOY digital signal earlier, compensating circuit carries out synchronizing signal acquisition work according to SOG that is received or SOY digital signal earlier, mix synchronizing signal to produce, afterwards, according to aforementioned clock signal and clamped signal, after again SOG or SOY digital signal being carried out clamped computing, to produce compensated digital signal.
The present invention is characterised in that any capacitor is not set in the input unit, simultaneously, in direct current input analog front circuit any embedded device is not set yet.So, just there are not AC coupled and clamped mechanism the time to need a period of time to stablize in running, and the problem of the variation of DC level that can't the immediate response image analoging signal.The present invention is by the suitable comparative voltage of selection, and adding electric pressure converter or compensating circuit, still can reach the purpose that produces correct digital signal.Therefore, the present invention makes that the design of input buffer is more flexible because any capacitor and embedded device are not set, even can be deleted, not only save the component number on the printed circuit board (PCB), more reduce the power consumption and the area of analog circuit, also obtain preferable image quality simultaneously.
Description of drawings
Fig. 1 is the configuration diagram of image processing apparatus of the present invention.
Fig. 2 A is the configuration diagram of the first embodiment of the present invention.
Fig. 2 B is the circuit diagram of electric pressure converter.
Fig. 3 is the configuration diagram of the second embodiment of the present invention.
Fig. 4 is the configuration diagram of the third embodiment of the present invention.
Fig. 5 is the sequential chart of image analoging signal R, SOG, B, mixing synchronizing signal HS+VS and clamped signal clamp.
The figure number explanation:
100,200,300,400 image processing apparatus
111,121,131 embedded devices
112,122,132 input buffers
113,123,133,413,423,433 analog-to-digital converters
140 energy gap reference circuits
150 clock generators
170 display cards
180 input units
190,290,390,490 direct currents input analog front circuit
450 Synchronous Processing and clock generator
11,12,13,21,22,23,31,32,33 change-over circuits
41,42,43 change-over circuits
211,221,231 electric pressure converters
314,324,334,434 compensating circuits
Embodiment
Fig. 1 is the basic framework figure of image processing apparatus of the present invention.Image processing apparatus 100 of the present invention comprises input unit 180 and direct current input analog front circuit 190.This image processing apparatus 100 is used for handling at least one image analoging signal R, G or the B from display card 170 feed-ins, and produces at least one digital signal D1, D2 or D3.Wherein, input unit 180 is arranged on the printed circuit board (PCB), and direct current input analog front circuit 190 is to be arranged among the foregoing liquid crystal display controller.
For reaching the purpose of direct current input, in the input unit 180 of the present invention any capacitor is not set, in the analog front circuit 190 of direct current input simultaneously any embedded device also is not set, input unit 180 transmits (bypass) immediately to direct current input analog front circuit 190 after image analoging signal R, the G or B that receive by display card 170 feed-ins.
For the image analoging signal that imports input unit 180 into, its video signal format, except above-mentioned image analoging signal R from display card 170 feed-ins, G, or outside the B, also comprise the signal (figure does not show) that is transmitted by video data origin system (digital/analog converter wherein), as the CVBS signal, the YC signal, YPrPb signal etc., at this moment, image processing apparatus 100 is the parts that belong to television system or other video display system, and direct current input analog front circuit 190 is arranged among the Video Decoder (figure does not show), and 180 of input units are arranged on the printed circuit board (PCB).But application of the present invention is as limit, and existing or other video signal format of developing out in the future is also applicable to notion of the present invention.Explain for convenient that below image analoging signal R, G, the B that will receive display card 170 feed-ins with input unit 180 are that example explains.
The image analoging signal of being exported by display card 170 (R, G, B), be to utilize constant current source (Iv1, Iv2, Iv3) equivalence, image analoging signal (R, G, BPb) is transferred into direct current input analog front circuit 190 to carry out the analog digital conversion work via input unit 180.As shown in Figure 1, input unit 180 is provided with a terminal (termination) resistance (R12, R22, R32) (about 75 Ω) respectively to avoid signal reflex on each signal transmission path.
Direct current input analog front circuit 190 comprises three analog-to-digital converters 113,123,133, energy gap reference circuits 140, clock generator 150.Three analog-to-digital converters 113,123,133 receive respectively by simulating to digital translation after image analoging signal R, the G of input unit 180 feed-ins, the B, to produce corresponding digital signal D1, D2, D3.Each analog-to-digital converter comprises positive and negative two inputs, and anode receives image analoging signal (for example R), and negative terminal receives comparative voltage (V for example
Cmp1), each analog-to-digital converter is according to periodic clock signal clk, (with analog-to-digital converter 113 is example, the voltage difference of input=(R-V with the voltage difference of two inputs
Cmp1), then the rest may be inferred for the voltage difference of all the other analog-digital converter inputs) convert digital signal (for example D1) to.In addition, clock generator 150 provides periodic clock signal clk to the usefulness of analog-digital converter (113,123,133) as sampling, and 140 of energy gap reference circuits produce reference voltage V
Ref, be used for adjusting full width (full scale) voltage or bias voltage (bias) electric current so that analog-to-digital converter (113,123,133) to be provided.
The reference voltage V that circuit developer utilizable energy crack reference circuits 140 produces
Ref, or other hardware circuit even dynamically adjust comparative voltage V in the mode of software or firmware
Cmp1, V
Cmp2, V
Cmp3Size, when analog-to-digital converter 113,123,133 conversion black level signals, the digital value that the voltage difference that can adjust two inputs of analog-to-digital converter 113,123,133 makes analog-to-digital converter separate to read also equals 0 (below be referred to as to transfer black correction program).After the black correction program of above-mentioned accent, the digital signal value that the output of analog-to-digital converter 113,123,133 is separated out all can drop within 0～255 the scope (hypothetical simulation to digital quantizer is 8), does not have the phenomenon generation of skew.Wherein, the phenomenon of skew is meant and should be 0～255 Read Range originally that this Read Range has but become 6～255 after being offset.
In known technology, because use AC coupled and clamped mechanism, thus the input buffer of essential collocation high input impedance and high output drive strength, to prevent that the DC level that image analoging signal has been rebuild from being pulled away.But, because image processing apparatus of the present invention has been deleted AC coupled and clamped mechanism, and any capacitor and embedded device are not set, therefore the necessity of input buffer is not set yet, input buffer is wasted in the known image processing unit space and cost be can save, and the power consumption and the area of circuit reduced.The present invention has given up old AC coupled and clamped mechanism, and directly with image analoging signal R, G, B feed-in direct current input analog front circuit 190, again circuit 190 is set for whenever, just carried out and once transfer black correction program, dynamically adjust comparative voltage V through one section Preset Time
Cmp1, V
Cmp2, V
Cmp3Size, to guarantee the correctness of digital signal D1, D2, D3.
Fig. 2 A is the configuration diagram of the first embodiment of the present invention.Fig. 2 B is the circuit diagram of electric pressure converter.In this first embodiment, image processing apparatus 200 comprises input unit 180 and direct current input analog front circuit 290.Direct current input analog front circuit 290 comprises three identical change-over circuits 21,22,23, energy gap reference circuits 140, clock generator 150.Each change-over circuit (21,22,23) comprises electric pressure converter (211,221,231), input buffer (112,122,132), analog-to-digital converter (113,123,133).Image processing apparatus 200 among Fig. 2 A has been more than each change-over circuit an electric pressure converter and an input buffer with the difference of Fig. 1 image processing apparatus 100.In this setting that note that this input buffer only is an embodiment, and scope of the present invention is not limited thereto, and also this input buffer can be set.Because via image analoging signal R, G, the B signal magnitude of cable feed-in to a certain degree decay (degrade) must be arranged from display card 170, the present invention utilizes electric pressure converter 211,221,231 to adjust the DC level of image analoging signal R, G, B, after respectively the direct voltage of image analoging signal R, G, B up being drawn and lifted, produce and draw and lift signal F1, F2, F3.Then, draw and lift signal F1, F2, F3 and comparative voltage V
Cmp1, V
Cmp2, V
Cmp3Be sent to input buffer 112,122,132 more respectively and make buffered.Secondly, input buffer 112 will draw and lift signal F1 and comparative voltage V simultaneously
Cmp1Be sent to analog-to-digital converter 113, input buffer 122 and will draw and lift signal F2 and comparative voltage V simultaneously
Cmp2Be sent to analog-to-digital converter 123, input buffer 132 and will draw and lift signal F3 and comparative voltage V simultaneously
Cmp3Be sent to analog-to-digital converter 133.At last, analog-to-digital converter 113 is with the voltage difference (F1-V of two inputs
Cmp1) converting digital signal D1 to, analog-to-digital converter 123 is with the voltage difference (F2-V of two inputs
Cmp2) convert digital signal D2, analog-to-digital converter 133 voltage difference (F3-V to two inputs
Cmp3) convert digital signal D3 to.Wherein,, it must be raised to positive voltage, then can utilize a constant current source I if input signal is a negative voltage
MConnect P channel transistor M and be used as electric pressure converter (shown in Fig. 2 B).
Compared to direct current input analog front circuit 190, the first embodiment of the present invention has increased the setting of electric pressure converter, make analog-to-digital converter (113,123,133) when the voltage difference of two inputs adjusting, not only can adjust comparative voltage, also can adjust the DC level of image analoging signal, increase the elasticity of adjusting greatly.The first embodiment of the present invention is by suitably selecting electric pressure converter 211,221,231 DC level that drawn and lifted and adjusting comparative voltage V
Cmp1, V
Cmp2, V
Cmp3Size, at analog-to-digital converter 113,123, during 133 conversions (or correction) black level signal, can adjust analog-to-digital converter 113,123, the voltage difference of two inputs of 133 makes the digital value that analog-to-digital converter solved equal 0, therefore, after the black correction program of above-mentioned accent, analog-to-digital converter 113,123,133 reception successive image analog signals are also simulated to digital operation, under the correct situation of gain ranging (Gain Range), the digital value that is produced (D1, D2, D3) will drop in 0～255 the scope (hypothetical simulation to digital quantizer is 8).
Fig. 3 is the configuration diagram of the second embodiment of the present invention.According to the present invention, the image processing apparatus 300 of second embodiment comprises input unit 180 and direct current input analog front circuit 390.Direct current input analog front circuit 390 comprises three identical change-over circuits 31,32,33, energy gap reference circuits 140 (not shown), clock generator 150.Each change-over circuit comprises analog-to-digital converter (113,123,133) and compensating circuit (314,324,334).Wherein, the comparative voltage V of input analog-to-digital converter 113
Cmp1Be to utilize variable current source I
P1The circuit that connects resistance R 13 produces, the comparative voltage V of input analog-to-digital converter 123
Cmp2Be to utilize variable current source I
P2The circuit that connects resistance R 23 produces, the comparative voltage V of input analog-to-digital converter 133
Cmp3Be to utilize variable current source I
P3The circuit that connects resistance R 33 produces.
Suppose that the worst situation appears in circuit, just analog-to-digital converter 113,123,133 can't be by adjusting comparative voltage V behind the black correction program of above-mentioned accent
Cmp1, V
Cmp2, V
Cmp3Make that the digital value that analog-to-digital converter solved is 0, second embodiment provides the compensating circuit 314,324,334 of numeral in addition, be according to clock signal clk and clamped signal clamp, respectively digital signal D1, D2, D3 are carried out clamped computing, to guarantee to produce correct compensated digital signal D1 ', D2 ', D3 '.For example: digital signal value D1, the D2 that hypothetical simulation is separated out to the output of digital quantizer 113,123,133, D3 are 10～255 scope (hypothetical simulation to digital quantizer is 8), are V and cause such result's reason
Cmp1, V
Cmp2, V
Cmp3Set correctly, or analog-to-digital converter itself has non-ideal characteristic.At this moment, the practice of insuring is most utilized compensating circuit (314,324,334) exactly, catch the sequential (timing) of digital signal D1, D2, D3 output on the one hand according to clock signal clk, also utilize the pulse of clamped signal clamp to come corrective black level on the other hand, make digital signal D1, D2, D3 after passing through compensating circuit 314,324,334 respectively, guarantee to produce correct compensated digital signal D1 ', D2 ', D3 ', the above practice can be referred to as the direct current of numeric field (digital domain) and rebuild.According to the present invention, first and second embodiment is applicable to that all reception does not comprise the image analoging signal of SOG or SOY, just primary image signal (R, G, B).The 3rd following embodiment then is applicable to and receives the image analoging signal that comprises SOG or SOY, for example image analoging signal R, SOG, B, perhaps image analoging signal SOY, Pr, Pb, or CVBS signal or (Y, C) signal.
Fig. 4 is the configuration diagram of the third embodiment of the present invention.Fig. 5 is the sequential chart of image analoging signal R, SOG, B, mixing synchronizing signal HS+VS and clamped signal clamp.
Because characteristic of the present invention is not to be provided with in the input unit any capacitor, simultaneously, in direct current input analog front circuit, any embedded device is not set, and image analoging signal is directly imported in the direct current input analog front circuit, so, when the third embodiment of the present invention captures mixing synchronizing signal HS+VS at reception image analoging signal SOG (or SOY), the AC coupled of traditional SOG (or SOY) branch (comprise ac coupling capacitor with synchronously at green circuit) and clamped mode have also been abandoned simultaneously, and also include the work of original SOG (or SOY) branch in compensating circuit 434, make compensating circuit 434 implement the work that acquisition mixes synchronizing signal HS+VS in the lump.With next with image processing apparatus 400 receive image analoging signal R, B, SOG are the function mode that example illustrates the 3rd embodiment.
Image processing apparatus 400 with reference to figure 4, the three embodiment comprises input unit 180 and direct current input analog front circuit 490.Direct current input analog front circuit 490 comprises three change-over circuits 41,42,43 and Synchronous Processing and clock generator 450.Each change-over circuit (41,42,43) comprises an analog-to-digital converter (413,423,433) and a compensating circuit (314,324,434).Difference between analog-to-digital converter in the present embodiment (413,423,433) and other analog-to-digital converter (113,123,133) is that it is big that the voltage range of the input of analog-to-digital converter (413,423,433) becomes.In the known technology, the voltage range of image analoging signal R, the B of process AC coupled and embedded device is about 0～750mV (as shown in Figure 5), and the voltage range of image analoging signal SOG is increased to-300mV～750mV, therefore the decoding figure place of analog-to-digital converter (413,423,433) (or resolving the position) must increase, for example increase to 10, variation otherwise the quality of image or resolution are bound to from original 8.Running as for input unit 180, change-over circuit 41,42 is identical with Fig. 3, no longer repeat specification.
The analog-to-digital converter 433 of change-over circuit 43 receives after the image analoging signal SOG, carries out the analog digital conversion to produce digital signal D3.The circuit function mode is, behind the compensating circuit 434 receiving digital signals D3, must capture out and be sent to Synchronous Processing and clock generator 450 mixing synchronizing signal HS+VS earlier, and Synchronous Processing and clock generator 450 are after receiving mixing synchronizing signal HS+VS, at first produce synchronizing signal HS, synchronizing signal VS and clamped signal clamp, produce periodic clock signal clk to offer compensating circuit (314,324,434) according to two synchronizing signal HS, VS again.Then, compensating circuit 434 according to clock signal clk and clamped signal clamp, is carried out clamped computing to digital signal D3 again, to produce compensated digital signal D3 '.
According to the present invention, compensating circuit 434 is divided into two parts, comprise synchronizing signal acquisition unit and clamped unit (not shown), the synchronizing signal signal that the synchronizing signal acquisition unit operates mainly among the acquisition digital signal D3 mixes synchronizing signal HS+VS to produce, clock signal clk and clamped signal clamp that clamped unit is then produced according to Synchronous Processing and clock generator 450 carry out clamped computing to digital signal D3 again.Hypothetical simulation to digital quantizer 413,423,433 is 10, voltage range-300mV～0 of " groove " among digital value 0～250 representative image analog signal SOG of output signal D3, the voltage range 0～750mV of " view data " among digital value 250～1023 representative image analog signal SOG of output signal D3.During the circuit initialization, the acquisition synchronizing signal acquisition unit of compensating circuit 434 is set a comparison value (for example 125) (substituting the function of comparator in original SOG circuit) earlier, so that capture out mixing synchronizing signal HS+VS, in one section Preset Time, if the received signal value of synchronizing signal acquisition unit all is lower than 125, expression " groove " arrives, the voltage of the mixing synchronizing signal HS+VS of electronegative potential is made as 1 to the synchronizing signal acquisition unit with being about to originally, finish up to " groove ", the voltage that will mix synchronizing signal HS+VS establishes back 0 again, simultaneously, mix synchronizing signal HS+VS and also be sent to Synchronous Processing and clock generator 450 to produce clamped signal clamp and periodic clock signal clk.
Suppose digital signal D1, D2, digital value 250～1023 representative image analog signal R of D3, B, voltage range 0～the 750mV of " view data " among the SOG, compensating circuit 314,324 and the clamped unit of compensating circuit 434 catch digital signal D1 according to clock signal clk again, D2, the sequential of D3 output, and utilize the pulse of clamped signal clamp to come corrective black level, make digital signal D1, D2, D3 is passing through compensating circuit 314,324, after 434, produce correct compensated digital signal D1 ', D2 ', D3 ' (for example its digital value is consistent adjusts back to 0～255).
Though more than with embodiment the present invention is described, therefore do not limit scope of the present invention, only otherwise break away from main idea of the present invention, those skilled in the art can carry out various distortion or change.
Claims (9)
1. image processing apparatus in order to receiving at least one image analoging signal, and produces at least one digital signal, and this image processing apparatus comprises:
Input unit, in order to receive this image analoging signal, wherein this input unit does not comprise capacitor; And
Direct current input analog front circuit, be to be electrically connected this input unit, wherein this direct current input analog front circuit comprises at least one change-over circuit, an energy gap reference circuits and a clock generator, each change-over circuit comprises an analog-to-digital converter at least, and each change-over circuit does not all comprise embedded device
Wherein, this analog-to-digital converter comprises two inputs, in order to receiving this image analoging signal and comparative voltage from this input unit respectively, and converts the voltage difference of this two input to this digital signal according to clock signal,
Wherein, this energy gap reference circuits produces reference voltage, to offer this analog-to-digital converter, and in order to adjustment full width voltage or bias current,
Wherein, this clock generator is in order to producing the usefulness of this clock signal as sampling, and
Wherein, this reference voltage of this energy gap reference circuits generation is in order to the size of dynamic adjustment comparative voltage.
2. image processing apparatus according to claim 1, wherein each change-over circuit also comprises electric pressure converter, in order to adjust the DC level of aforementioned image analoging signal.
3. image processing apparatus according to claim 2, wherein the aforesaid voltage transducer comprises:
Constant current source; And
Transistor, grid receive aforementioned image analoging signal, and source electrode is connected to this current source and aforementioned analog-to-digital converter, grounded drain.
4. image processing apparatus according to claim 1, wherein aforementioned each change-over circuit also comprises compensating circuit, is the back level that is arranged at this analog-to-digital converter, and according to this clock signal and clamped signal, aforementioned digital signal is carried out clamped computing, to produce compensated digital signal.
5. image processing apparatus according to claim 4, wherein, this clock generator is Synchronous Processing and clock generator, receives to mix synchronizing signal, to produce this clock signal and this clamped signal.
6. image processing apparatus according to claim 1, wherein each change-over circuit also comprises:
Variable current source; And
Resistance is connected to this variable current source, and the tie point of this resistance and this variable current source produces this comparative voltage.
7. image processing method includes:
Receive at least one image analoging signal;
Adjust the DC level of aforementioned image analoging signal;
According to clock signal, convert the voltage difference of this image analoging signal and comparative voltage to digital signal;
This digital signal is carried out clamped computing, to produce compensated digital signal; And
Dynamically adjust this comparative voltage.
8. image processing method according to claim 7 also comprises:
Produce reference voltage; And
Utilize this reference voltage to adjust this comparative voltage.
9. image processing method according to claim 7 also comprises:
Receive this digital signal and go forward side by side line synchronizing signal acquisition processing to produce the mixing synchronizing signal; And
According to this clock signal and clamped signal, this digital signal is carried out this clamped computing, to produce this compensated digital signal.
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| CN1482804A (en) * | 2002-08-13 | 2004-03-17 | 三星电子株式会社 | Apparatus and method for a/d conversion in a digital video system |
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| CN101521825A (en) | 2009-09-02 |
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