CN101510349B - Data buffering type multichannel monitoring apparatus - Google Patents
Data buffering type multichannel monitoring apparatus Download PDFInfo
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- CN101510349B CN101510349B CN200910071674XA CN200910071674A CN101510349B CN 101510349 B CN101510349 B CN 101510349B CN 200910071674X A CN200910071674X A CN 200910071674XA CN 200910071674 A CN200910071674 A CN 200910071674A CN 101510349 B CN101510349 B CN 101510349B
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Abstract
The invention provides a data buffer multi-channel monitoring device. A digital signal processor (U1) is connected with a programmable logic device (U2), a field programmable gate array (U3), a multi-circuit selection switch (U5), a communication interface (U6), a fault alarm interface (U11) and an external memory (U12); the programmable logic device (U2) is connected with the field programmable gate array (U3), a video decoder (U10) and the external memory (U12); the field programmable gate array (U3) is connected with a liquid crystal display screen (U4); the multi-circuit selection switch (U5) is connected with a wind speed-like sensor, a water flow sensor and a temperature sensor; the communication interface (U6) is connected with a GPS signal plate (U7) and a PC (U8); and a CCD photoelectric converter (U9) is connected with the video decoder (U10). The data buffer multi-channel monitoring device has the advantages and effects that a high-reliability, comprehensive and practical monitoring system is finally provided by processing the data of every module through the multi-channel data buffer technology.
Description
(1) technical field
What the present invention relates to is a kind of supervisory system, specifically a kind of data buffering type supervisory system.
(2) background technology
The supervisory system of generally using mainly contains following several now:
1, utilizes the situation of LED display demonstration as devices such as boats and ships.Shortcoming is the display message dullness, can not display video information.
2, utilize can display video information video monitor show the situation of devices such as boats and ships main rudder, wing rudder.But this monitor mode is displays image information merely, can not carry out profound level to image information and handle, and a cover display system can only show one road image, does not possess the function that split screen shows the multi-channel video image.
3, utilization is based on the monitoring and display system of PC platform.This system can show the ruuning situation of devices such as main rudder, wing rudder in real time, and can carry out profound level analysis to image, can show multiway images simultaneously.But this system needs special video frequency collection card, and Installation and Debugging need higher know-how, and the cost height, and are bulky, promotes difficulty on the device of space requirement strictness.
(3) summary of the invention
The object of the present invention is to provide a kind of reliability height, data buffering type multichannel monitoring apparatus that applicability is good.
The object of the present invention is achieved like this:
It comprises digital signal processor U1, programmable logic device (CPLD) U2, on-site programmable gate array FPGA U3, LCDs U4, multidiameter option switch U5, communication interface RS232CAN U6, gps signal plate U7, PC U8, CCD photoelectric commutator U9, Video Decoder U10, fault alarm interface U11, external memory storage U12, digital signal processor U1 connects programmable logic device (CPLD) U2, on-site programmable gate array FPGA U3, multidiameter option switch U5, communication interface RS232CAN U6, fault alarm interface U11, external memory storage U12, programmable logic device (CPLD) U2 connects on-site programmable gate array FPGA U3, Video Decoder U10, external memory storage U12, on-site programmable gate array FPGA U3 connects LCDs U4, multidiameter option switch U5 connects as air velocity transducer, water flow sensing unit, temperature sensor etc., communication interface RS232 CAN U6 connects gps signal plate U7, PC U8, CCD photoelectric commutator U9 connects Video Decoder U10.
The present invention can also comprise some architectural features like this:
1, digital signal processor U1 adopts digital signal processor TMS320C6713 chip, comprise ADC, MCBSP, EMIF and eCAN part, ADC partly connects multidiameter option switch U5, MCBSP partly connects on-site programmable gate array FPGA U3, EMIF partly connects Video Decoder U10, fault alarm interface U11, external memory storage U12, and eCAN connects communication interface RS232 CAN U6.
2, programmable logic device (CPLD) U2 adopts the CPLDXC9536XL chip, external devices is played the logic control effect, and inside is provided with system protection circuit.
3, communication interface RS232 CAN U6 is the CAN mouth.
4, external memory storage U12 is the SRAM storer.
Control signal is by the given signal of communication interface U6 by PC among the present invention.
The signal of gps signal plate U7 output is input to digital signal processor U1 through communication interface RS232CAN U6, and deposits in the data-carrier store of DSP by the multi-functional buffered serial port (MCBSP) of DSP.
Be input to A/D converter spare by information via multidiameter option switch U5, and deposit in the data-carrier store of DSP by the multi-functional buffered serial port (MCBSP) of DSP as sensor acquisition such as wind speed, current, temperature.
CCD photoelectric commutator U9 changes into analog video data with vision signal, converts digital video signal to by Video Decoder U10 again through the analog video data of changing, and digital video signal cushions through FIFO, in the data-carrier store of last collected DSP.
Whether adopt image process method to carry out algorithm process to video data, can discern as devices such as main rudder, wing rudders and break down, if break down, failure message is input to fault alarm interface U11 through digital signal processor U1, gives the alarm.
PC U8 simulation produces data as device device for monitoring running state such as ship flap rudders, data comprise main rudder parameter, wing rudder parameter, sea condition, loading parameters etc., data are handled the back through on-site programmable gate array FPGA U3 then and are shown by LCDs U4 through the multi-functional buffered serial port (MCBSP) that communication interface RS232 CAN U6 is input to digital signal processor U1.
Advantage of the present invention and effect are the data of each module of system are handled by the multi-channel data buffer technology, and a cover high reliability, comprehensive practical supervisory system finally are provided:
(1) be core processor with cost performance height, TMS320C6713 chip low in energy consumption, by extender district and data field, but the FLASH chip of the SRAM of use fast access and rewritable, power down protection, the reliability of assurance system.Utilize himself A/D modular converter to realize collection as data such as wind speed, current, temperature; Utilize himself multi-functional buffered serial port (MCBSP) to realize the storage of data such as gps signal, wind speed, current, temperature.
(2) adopt programmable logic device (PLD) (CPLD) to replace discreet logic device and analog device, by the circuit level height that the programming to CPLD realizes, antijamming capability is strong; CPLD also finishes the virtual protection function to DSP output pulse in addition, and the status signal of system feedback is handled, and realizes failure response, protection system; In addition, extensive programable logic device and small scale in circuitry logical device ratio have increased integrated level, have reduced wiring density, improve system reliability.
(4) description of drawings
Fig. 1 is a system principle structural drawing of the present invention;
Fig. 2 is a system program process flow diagram of the present invention;
Fig. 3 is the circuit theory diagrams of programmable logic device (PLD) of the present invention;
Fig. 4 is a system failure warning circuit schematic diagram of the present invention;
Fig. 5 is on-site programmable gate array FPGA circuit theory diagrams of the present invention.
(5) embodiment
For example the present invention is done description in more detail below in conjunction with accompanying drawing:
In conjunction with Fig. 1, the present invention includes digital signal processor U1, programmable logic device (CPLD) U2, on-site programmable gate array FPGA U3, LCDs U4, multidiameter option switch U5, communication interface RS232CAN U6, gps signal plate U7, PC U8, CCD photoelectric commutator U9, Video Decoder U10, fault alarm interface U11, external memory storage U12, digital signal processor U1 connects programmable logic device (CPLD) U2, on-site programmable gate array FPGA U3, multidiameter option switch U5, communication interface RS232CAN U6, fault alarm interface U11, external memory storage U12, programmable logic device (CPLD) U2 connects on-site programmable gate array FPGA U3, Video Decoder U10, external memory storage U12, on-site programmable gate array FPGA U3 connects LCDs U4, multidiameter option switch U5 connects air velocity transducer, water flow sensing unit, temperature sensor, communication interface RS232 CAN U6 connects gps signal plate U7, PC U8, CCD photoelectric commutator U9 connects Video Decoder U10.Digital signal processor U1 adopts digital signal processor TMS320C6713 chip, comprise ADC, MCBSP, EMIF and eCAN, ADC partly connects multidiameter option switch U5, MCBSP partly connects on-site programmable gate array FPGA U3, EMIF partly connects Video Decoder U10, fault alarm interface U11, external memory storage U12, and eCAN connects communication interface RS232CAN U6.Programmable logic device (CPLD) U2 adopts the CPLDXC9536XL chip, external devices is played the logic control effect, and inside is provided with system protection circuit.Communication interface RS232CANU6 is the CAN mouth.
In conjunction with Fig. 2, workflow of the present invention is: during system start-up, at first from the FLASH loading application programs, program then brings into operation, carry out system initialization, comprise DSP clock, serial ports, DMA passage, timer and sampling module and display controller are carried out initialization, system begins operate as normal.When the video data field interrupts taking place, start the video data interrupt service subroutine, video data is gathered and stored; When serial ports 1 interrupts taking place, start GPS and gather service subprogram, gps data is gathered and stored; When serial ports 2 interrupts taking place, start as sea situation state acquisition interrupt service subroutine, the sea situation status data is gathered and stored.Take three frame buffer zone methods for video data on software design, one of them frame buffer zone is used for handling in real time and showing, two frame buffer zones are used for gathering storage in addition, and three frame buffer zones circulate between two states.To the signal of gathering, adopt data anastomosing algorithm that data message is carried out overall treatment, start display routine after the data processing, display shows in real time; Adopt image process method to carry out algorithm process to video data simultaneously, can discern devices such as main rudder, wing rudder and whether break down,, start alert program, give the alarm if break down.
Fig. 3 is the circuit theory diagrams of programmable logic device (PLD) of the present invention, as shown in Figure 3, programmable logic device (PLD) U2 adopts the XC9536XL chip of CPLD, the 2-8 pin of CPLD chip is PWM6-PWM1 output, connecting resistance R 37-R42 respectively arrives+the 3.3V power supply, 7 pin are the T1 pin of PWM, 35 pin are the T2 pin of PWM, 9 pin are the DRIVE pin, 10,23,31 pin meet DGND, 15 pin are the TDI_CPLD input, 30 pin are TDO_CPLD output, 16 pin are the TMS_CPLD pin, 17 pin are the TCK_CPLD pin, 20 pin are the HV_S pin, 22 pin are the LV_S pin, and 24 pin connect switch S 1, capacitor C 48 to DGND, connect resistance R 103 and arrive+the 3.3 V power supply 21,32,41 pin connection+3.3V power supplys, 25-29,33 pin are PWM6O, PWM4O, PWM2O, PWM5O, PWM3O and PWM1O pin, 38 pin are the IPMF_S pin, and 39 pin are the BREAK pin, and the TCK1 pin of the JTAG-CPLD chip of programmable logic device (PLD) is the TCK_CPLD pin, the GND2 pin meets DGND, the TDI3 pin is the TDI_CPLD pin, and the VCC4 pin connects+the 5V power supply, and the TMS5 pin is the TMS_CPLD pin, the TDO9 pin is the TDO_CPLD pin, and capacitor C 54-C56 connection+3.3V is to DGND.
Fig. 4 is on-site programmable gate array FPGA circuit theory diagrams of the present invention, as shown in Figure 4, on-site programmable gate array FPGA adopts the XC2S200-5PQ208C chip, 12,26,39,53,65,92,105,117,130,144,150,170,184,198,208 pin of fpga chip are the VCC pin, 3 pin are the FPGA_RST pin, 77 pin are the IFCLK pin, 80 pin are the FPGA_CLK pin, 2 pin are the TMS pin, 157 pin are the TDO pin, 207 pin are the TCK pin, and 106 pin are the PROG pin.Capacitor C 46-C57 connection+2.5V is to DGND, and capacitor C 58-C73 connection+3.3V is to DGND.
Fig. 5 is system failure warning circuit figure of the present invention, as shown in Figure 5, input signal busbar voltage IPMP connects resistance R 81, R82 is to amplifier U8A and amplifier U8B, connect resistance R 83, capacitor C 35 to P_GND, amplifier U8A connects resistance R 74, capacitor C 11 to P_GND, resistance R 32 to VCC+15V, the output of amplifier U8A connects resistance R 32 to VCC+15V, resistance R 71 is to triode Q5 base electrode, triode Q5 cascode level is to P_GND, collector output connects resistance R 53 to the O1 unit, the O1 unit connects resistance R 14 to VCC+5V, output connects HV_S over voltage alarm signal, amplifier U8B connects resistance R 55, capacitor C 12 to P_GND, resistance R 90 to VCC+15V, the output of amplifier U8B connects resistance R 75 to VCC+15V, resistance R 72 is to triode Q6 base electrode, triode Q6 cascode level is to P_GND, collector output connects resistance R 54 to the O2 unit, and the O2 unit connects resistance R 16 to VCC+5V, output connects LV_S undervoltage warning signal.
Fig. 5 median generatrix voltage IPMP obtains voltage actual detected voltage U d by the dividing potential drop of resistance R 81, R82 and R83, and Ud connects 5 pin of amplifier LM339.The reference voltage of alarm for high voltage is obtained by R32 and R74 dividing potential drop by+15V voltage, and the high pressure reference voltage connects 4 pin of LM339.When detection voltage U d is higher than the high pressure reference voltage, the comparer upset, the 2 pin output high pressure of LM339 makes the Q5 conducting, by electric current, makes HV_S over voltage alarm signal put height, output alarm signal among the O1.Low pressure detects 6 pin that Ud meets LM339.Low pressure reference voltage+15V voltage is obtained by R90 and R55 dividing potential drop, and low pressure detects 7 pin that meet LM339.When detection voltage U d was lower than the low pressure reference voltage, 1 jiao of output high pressure of LM39 made the Q6 conducting.O2 alives and makes LV_S undervoltage warning signal put height, output alarm signal.
Claims (3)
1. data buffering type multichannel monitoring apparatus, it comprises digital signal processor (U1), programmable logic device (PLD) (U2), field programmable gate array (U3), LCDs (U4), multidiameter option switch (U5), communication interface (U6), gps signal plate (U7), PC (U8), CCD photoelectric commutator (U9), Video Decoder (U10), fault alarm interface (U11) and external memory storage (U12), it is characterized in that: digital signal processor (U1) connects programmable logic device (PLD) (U2), field programmable gate array (U3), multidiameter option switch (U5), communication interface (U6), fault alarm interface (U11), external memory storage (U12), programmable logic device (PLD) (U2) connects field programmable gate array (U3), Video Decoder (U10), external memory storage (U12), field programmable gate array (U3) connects LCDs (U4), multidiameter option switch (U5) connects air velocity transducer, water flow sensing unit, temperature sensor, communication interface (U6) connects gps signal plate (U7), PC (U8), CCD photoelectric commutator (U9) connects Video Decoder (U10); Described programmable logic device (PLD) (U2) adopts the XC9536XL chip of CPLD, the 2-6 of CPLD chip, 8 pin are PWM6-PWM1 output, connecting the 37-42 resistance (R37-R42) respectively arrives+the 3.3V power supply, 7 pin are the T1 pin of PWM, 35 pin are the T2 pin of PWM, 9 pin are the DRIVE pin, 10,23,31 pin meet DGND, 15 pin are the TDI_CPLD input, 30 pin are TDO_CPLD output, 16 pin are the TMS_CPLD pin, 17 pin are the TCK_CPLD pin, 20 pin are the HV_S pin, 22 pin are the LV_S pin, switch S 1 and the 36 electric capacity (C36) are connected in parallel, one end connects 24 pin and is connected to+the 3.3V power supply through the 103 resistance (R103), the other end is connected to DGND, 21,32,41 pin connection+3.3V power supplys, 25-29,33 pin are PWM6O, PWM4O, PWM2O, PWM5O, PWM3O and PWM1O pin, 38 pin are the IPMF_S pin, 39 pin are the BREAK pin, the TCK1 pin of the JTAG-CPLD chip of programmable logic device (PLD) is the TCK_CPLD pin, the GND2 pin meets DGND, the TDI3 pin is the TDI_CPLD pin, the VCC4 pin connects+the 5V power supply, the TMS5 pin is the TMS_CPLD pin, the TDO6 pin is the TDO_CPLD pin, the 54-56 electric capacity (C54-C56) parallel connection, connection+3.3V is to DGND respectively.
2. data buffering type multichannel monitoring apparatus according to claim 1, it is characterized in that: described field programmable gate array adopts the XC2S200-5PQ208C chip, 12,26,39,53,65,92,105,117,130,144,156,170,184,197,208 pin of field programmable gate array chip are the VCC pin, 3 pin are the FPGA_RST pin, 77 pin are the IFCLK pin, 80 pin are the FPGA_CLK pin, 2 pin are the TMS pin, 157 pin are the TDO pin, 207 pin are the TCK pin, and 106 pin are the PROG pin; The the 46-57 electric capacity (C46-C57) connection+2.5V is to DGND, and the 58-73 electric capacity (C58-C73) connection+3.3V is to DGND.
3. data buffering type multichannel monitoring apparatus according to claim 1 and 2, it is characterized in that: the failure alarm circuit figure that connects on the fault alarm interface is, input signal busbar voltage IPMP connects the 81 resistance (R81) of series connection and an end of the 82 resistance (R82), the 81 resistance (R81) of series connection and the other end of the 82 resistance (R82) are connected to the 8th A amplifier (U8A) and the 8th B amplifier (U8B), the 83 resistance (R83) is in parallel with the 35 electric capacity (C35), one end is connected between the 82 resistance (R82) and the 8th A amplifier (U8A), the other end connects P_GND, the 74 resistance (R74) is in parallel with the 11 electric capacity (C11), one termination the 8th A amplifier (U8A) and the 32 resistance (R32), another termination P_GND, the 32 resistance (R32) meets VCC+15V, the output of the 8th A amplifier (U8A) connects the 73 resistance (R73) to VCC+15V, connect the 71 resistance (R71) to the 5th triode (Q5) base electrode, the 5th triode (Q5) common emitter connects P_GND, collector output connects the 53 resistance (R53) to the O1 unit, the O1 unit connects the 41 resistance (R14) to VCC+5V, output connects HV_S over voltage alarm signal, the 55 resistance (R55) is in parallel with the 12 electric capacity (C12), one end connects the 8th B amplifier (U8B) and the 90 resistance (R90), another termination P_GND, the 90 resistance (R90) meets VCC+15V, the output of the 8th B amplifier (U8B) connects the 75 resistance (R75) to VCC+15V, connect the 72 resistance (R72) to the 6th triode (Q6) base electrode, the 6th triode (Q6) common emitter connects P_GND, collector output connects the 54 resistance (R54) to the O2 unit, and the O2 unit connects the 16 resistance (R16) to VCC+5V, output connects LV_S undervoltage warning signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910071674XA CN101510349B (en) | 2009-03-31 | 2009-03-31 | Data buffering type multichannel monitoring apparatus |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910071674XA CN101510349B (en) | 2009-03-31 | 2009-03-31 | Data buffering type multichannel monitoring apparatus |
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| CN101510349A CN101510349A (en) | 2009-08-19 |
| CN101510349B true CN101510349B (en) | 2011-01-26 |
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| CN200910071674XA Expired - Fee Related CN101510349B (en) | 2009-03-31 | 2009-03-31 | Data buffering type multichannel monitoring apparatus |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101873439B (en) * | 2010-01-20 | 2012-04-04 | 杭州海康威视数字技术股份有限公司 | Method, system and decoder for switching monitoring channel |
| CN103091527A (en) * | 2011-11-04 | 2013-05-08 | 上海科沁机电有限公司 | Video universal meter |
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