CN101507117B - Return-to-hold switching scheme for DAC output stage - Google Patents
Return-to-hold switching scheme for DAC output stage Download PDFInfo
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- CN101507117B CN101507117B CN2007800307022A CN200780030702A CN101507117B CN 101507117 B CN101507117 B CN 101507117B CN 2007800307022 A CN2007800307022 A CN 2007800307022A CN 200780030702 A CN200780030702 A CN 200780030702A CN 101507117 B CN101507117 B CN 101507117B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
- H03M1/0863—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of switching transients, e.g. glitches
- H03M1/0872—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of switching transients, e.g. glitches by disabling changes in the output during the transitions, e.g. by holding or latching
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
- H03M1/0678—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components
- H03M1/068—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS
- H03M1/0682—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS using a differential network structure, i.e. symmetrical with respect to ground
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/742—Simultaneous conversion using current sources as quantisation value generators
- H03M1/747—Simultaneous conversion using current sources as quantisation value generators with equal currents which are switched by unary decoded digital signals
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Abstract
A novel clock control circuit completely removes the inter-symbol interference (ISI) in the DAC output waveform without any significant increase in power consumption and silicon area of the DAC. The novel circuit does not increase the requirement for slew rate and bandwidth of the amplifier.
Description
Priority information
The novel patent application serial numbers of U.S. utility that the application's request was submitted on June 28th, 2006 is No.11/476, and 476 priority is incorporated its full content into this paper by reference.
Technical field
The present invention relates to the mixed signal transducer of current steering type, and be specifically related in output stage, adopt the ∑-Δ digital to analog converter of the current-to-voltage converting circuit of continuous time.
Background technology
The current steering topology is to realize the common method of digital to analog converter in industry.Because the simplicity and the flexibility of this method, all having adopted in a large amount of high speeds that make up or high-resolution applications should topology.Fig. 1 illustrates the exemplary embodiments of the current steering type DAC 100 of 16 grades of thermometer-codes.This DAC comprises one group of current steering unit 102,104,106 and 108, amplifier 110, and a pair of feedback resistance 112 and 114, and also comprise a pair of capacitor C1 116 and C2 118 in some cases.Capacitor 116 and 118 effectively slows down the step output waveform to help to reduce the requirement of amplifier switching rate.The simplest form of control bit and supplementary form thereof is the Q and the QB output of d type flip flop array.The input of these d type flip flops is digital DAC sign indicating numbers.The operation of this circuit is quite simple, because how many unit digital code control has to be directed into the suitable summing junction of amplifier.The clock that limits the DAC transfer ratio is used for coming all outputs of Synchronization Control position to change via d type flip flop.
∑-Δ digital to analog converter (DAC) provides to compare relative low one-tenth with traditional Nyquist transducer and realized the device of high-resolution and low distortion originally.In the past, many these unusual realization results of high-resolution DAC that use current steering type topology in its output stage have been arranged.Can the title of Douglas Mercer in the paper of " A Low Power Current Steering Digitalto Analog Converter in 0.18Micron CMOS " and people's such as Adams title for finding the example of this enforcement in the paper of " A 113-dB SNR Oversampling DAC with SegmentedNoise-Shaped Scrambling ".
The paper teaches of above-mentioned Douglas Mercer solve the DC of low-power current steering type dac design and the multiple circuit engineering of AC distorted characteristic.It is 10 times high power DAC that the technology of AC distortion Mercer of resulting from can be tackled energy dissipation.
People's such as Adams above-mentioned paper teaches ∑-Δ digital to analog converter, it is implemented with 0.6 micrometre CMOS and the scrambling design of using the noise of 6 modulators and segmentation to form comes together to realize 113dB weighting dynamic range on the 20kHz bandwidth.The output stage of Adams is used the dual homed zero circuit, this circuit for eliminating the error that causes by intersymbol interference (ISI).
Fig. 2 illustrates the calcspar of the prior art audio band multidigit ∑-Δ DAC 200 that adopts current steering type output stage.This transducer comprises usually with 128 times of up-samplers 202 that the numeral input are upsampled to the design work frequency of system to input sample speed Fs (Fs=48kHz).The output of up-sampler 202 is imported in the digital filter 204, and this digital filter carries out filtering to the image that obtains from the up-sampling process.It is wide that sigma-delta modulator 206 reduces the output word of digital filter then, is reduced to more manageable size from 24 usually, is generally 4 to 6.This modulation substantially is the wide out-of-band noise that removes of small character more by truncated error being shifted onto in the higher untapped frequency field.Then use binary system thermometer encoder 208 that the binary weighting digital coding is become the thermometer-code data.The output of binary system thermometer encoder 208 is 2
NThe set of individual element (element), N is that the design word of modulator output is wide here.So each element that should gather will drive a current unit in this group current unit.In order to ensure the linearity of this group current unit, (also be called blender, shuffler or scrambler scrambler) 210 select 2 according to the digital code from thermometer encoder output then to use data selection logic
NThe subclass of individual element.Convert voltage by the summation that makes selected current unit to via current/voltage (I-V) transducer and produce output voltage.The output of element blender 210 is fed among the thermometer-code DAC 212.For the filtering out-of-band noise, use back analog filter (not shown) usually.
Disturb between the problem is-symbol of a fine understanding relevant (ISI) with current steering type DAC.This ISI problem is the result who is passed to unequal rise time and fall time in the current pulse shape of output by each current unit.Thereby the currency of DAC output depends on that it formerly is worth.Net effect is the main degradation (degradation) of total harmonic distortion (THD) and the noiseproof feature aspect of DAC.
Be used to minimize the influence of ISI such as the prior art of (RTZ) technology that makes zero.The principle of RTZ is shown in Figure 3.RTZ forces each current unit to turn-off a period of time, is generally half of clock cycle.Therefore, the output of DAC is always started from scratch at each clock cycle section start.ISI is removed thus fully.The major defect of this technology comprises high conversion rate, bandwidth requirement and the high power consumption in the amplifier; Introduce other high-frequency content as the result who belongs to nought state.In addition, the follow-up filtering stage of DAC must be very linear (the challenging task of a kind of oneself) so that avoid can be by from the dynamically distortion that causes of output of this height of DAC.
Fig. 4 illustrates two RTZ technology, and it is to the output summation of two RTZ waveforms postponing half clock cycle each other.People's such as Adams above-mentioned paper and title is that the United States Patent (USP) 6,061,010 of " Dualreturn-to-zero pulse encoding in a DAC output stage " has been instructed this pair of RTZ technology.By the principle of superposition theory, two no ISI waveform sums must produce a no ISI output.The major defect of this technology is the second group of electric current that increases the RTZ waveform be used to produce delay.This increase makes silicon area double, consume the quantity of power of twice and makes clock scheme and data sync between the digital and analog interface of DAC complicated.
When control bit carries out from 1 to 0 and from 0 to 1 transformation, always see identical symmetrical disturbance by guaranteeing current unit in its drain electrode, the low ISI gate drive circuit of prior art helps to reduce the influence of ISI.Known this class circuit can not be eliminated ISI fully.In addition, when logic changed, it drew big current spike signal from power supply, made this class circuit be unsuitable for the enforcement of low power consumption.
Regardless of accurate value, the feature and advantage of above-mentioned list of references of quoting and technology, neither one can obtain or realize purpose of the present invention in them.
Summary of the invention
The invention provides and remove the ISI in the DAC output waveform fully and do not have the power consumption of DAC and the clock control circuit and the method for any remarkable increase of silicon area aspect.In addition, the present invention does not increase as the switching rate of the pair amplifier seen usually in the prior art and the requirement of bandwidth.
The invention provides the method for the intersymbol interference error of the I-V output stage of eliminating current steering type DAC with a plurality of current units, wherein this output stage comprises I-V amplifier, feedback resistance R1 and the R2 with summing junction SJP and SJN at least, and feedback condenser C1 and C2.In this embodiment, the method includes the steps of: (a) in output stage the summing junction SJP of feedback resistance R1 and R2 and current unit and amplifier and SJN are disconnected; (b) feedback resistance R1 and R2 are linked together to stride across the output formation resistance string of output stage, and when the I-V amplifier did not link to each other with the current unit of current steering type DAC, feedback condenser C1 and C2 produced hold period to keep the output voltage of I-V amplifier; (c) link to each other with the mid point of resistance string by output, use the I-V amplifier, keep common mode electrical level with drain electrode during hold period at current unit as buffer with current unit; And when being in the maintenance pattern, the output of current unit changes the DAC sign indicating number, and (d) after the DAC sign indicating number is changed, the output of current unit is disconnected each other, and the suitable output of feedback resistance and current unit is reconnected back the summing junction of I-V transducer.
The present invention also provides the equipment of the intersymbol interference error of the I-V output stage of eliminating the current steering type DAC with a plurality of current units, wherein this output stage comprises I-V amplifier, feedback resistance R1 and the R2 with summing junction SJP and SJN at least, and feedback condenser C1 and C2.In this embodiment, this equipment comprises: (a) be used in output stage the summing junction SJP of feedback resistance R1 and R2 and current unit and amplifier and the device of SJN disconnection; (b) be used for feedback resistance R1 and R2 are linked together to stride across the output formation resistance string of output stage, and when the I-V amplifier did not link to each other with the current unit of current steering type DAC, feedback condenser C1 and C2 produced the device of hold period with the output voltage of maintenance I-V amplifier; (c) link to each other with the mid point of resistance string by output, be used to use the I-V amplifier, keep common mode electrical level with drain electrode during hold period at current unit as buffer with current unit; And be used for when the output of current unit is in the maintenance pattern, changing the device of DAC sign indicating number, and (d) after the DAC sign indicating number is changed, the output of current unit is disconnected each other, and the suitable output of feedback resistance and current unit is reconnected back the device of the summing junction of I-V transducer.
The present invention also provides the circuit of the intersymbol interference error of the I-V output stage of eliminating the current steering type DAC with a plurality of current units, and wherein this circuit comprises: the I-V amplifier that (a) has summing junction SJP and SJN; (b) the first feedback resistance R1; (c) the second feedback resistance R2; (d) the first feedback condenser C1; (e) the second feedback condenser C2; (f) be used for first switch S 1 that R1 and summing junction SJP are connected/disconnect and the second switch S2 that is used for R2 and summing junction SJN are connected/disconnect; (g) be used for the 3rd switch S 3 that feedback resistance R1 and R2 are linked together/disconnect, and when connecting, the output that R1 and R2 stride across output stage forms resistance string, and when the I-V amplifier did not link to each other with the current unit of current steering type DAC, feedback condenser C1 and C2 produced hold period to keep the output voltage of I-V amplifier; And wherein link to each other with the mid point of resistance string by output with current unit, this I-V amplifier is as buffer, keep common mode electrical level with drain electrode during hold period at current unit, and after the DAC sign indicating number is changed, the output of current unit disconnects each other, and the suitable output of feedback resistance and current unit is reconnected back the summing junction of I-V transducer.
The present invention also is provided for eliminating the circuit of intersymbol interference error of the I-V output stage of the current steering type DAC with a plurality of current units, and wherein this circuit comprises: (a) be used for first switch S 1 that the feedback resistance R1 and the summing junction SJP of I-V amplifier are connected/disconnect; (b) be used for second switch S2 that the feedback resistance R2 and the summing junction SJN of I-V amplifier are connected/disconnect; (c) be used for the 3rd switch S 3 that feedback resistance R1 and R2 are linked together/disconnect, and when connecting, the output that R1 and R2 stride across output stage forms resistance string, and when the I-V amplifier did not link to each other with the current unit of current steering type DAC, feedback condenser C1 and C2 produced hold period to keep the output voltage of I-V amplifier; And wherein link to each other with the mid point of resistance string by output with current unit, this I-V amplifier is as buffer, keep common mode electrical level with drain electrode during hold period at current unit, and after the DAC sign indicating number is changed, the output of current unit disconnects each other, and the suitable output of feedback resistance and current unit is reconnected back the summing junction of I-V amplifier.
Description of drawings
Fig. 1 illustrates the exemplary embodiments of 16 grades of thermometer-code current steering type DAC;
Fig. 2 illustrates the calcspar of the multidigit ∑ Δ DAC that adopts current steering type output stage;
Fig. 3 illustrates the waveform that makes zero;
Fig. 4 illustrates dual homed zero waveform;
Fig. 5 illustrates the calcspar that belongs to maintenance (return-to-hold) scheme;
Fig. 6 illustrates the sequential chart that belongs to maintenance;
Fig. 7 illustrates the schematic diagram of the control logic that is used to belong to inhibit signal.
Embodiment
Though illustrate and described the present invention in a preferred embodiment, can produce the present invention with many different structures.The preferred embodiments of the present invention are shown in the drawings and will describe in detail in this article, be appreciated that the example that present disclosure is counted as principle of the present invention and its structure related functionality is illustrated, and be not intended to the present invention is limited to shown embodiment.Those skilled in the art can imagine many other possible variations within the scope of the present invention.
Fig. 5 illustrates the calcspar that belongs to the maintenance scheme of the present invention, and wherein the increase of current steering type DAC output stage has switch S 1 502, S2 504 and S3 506.Switch S 1 502 and S2 504 are subjected to the control of HOLD_B signal, and switch S 3 506 is subjected to the control of HOLD signal.The sequential chart of clock, current unit control bit and control signal are shown in Figure 6.
The operation of circuit is as described below.When the rising edge of clock 602 arrived, HOLD_B 604 became low and by stopcock S1 502 and S2 504 and with the summing junction disconnection of feedback resistance R1 508 and R2510 and I-V transducer.Simultaneously, HOLD 606 becomes height and via switch S 3 506 left-hand side of resistance R 1 508 with R2 510 is linked to each other.The output of current unit also is shorted to together via switch S 3 506.During cycle, the I-V transducer is in " maintenance " pattern in this " maintenance ", and its output voltage remains identical value by capacitor C1 512 with C2 514.Therefore, this handover scheme is named as and belongs to maintenance.Because resistance R 1 508 links to each other with the positive and negative output that R2 510 strides across the I-V transducer, therefore the mid point (terminals of switch S 3 506) with this resistance string is set on output common mode (CM) voltage of amplifier A1.Because the output current unit links to each other with this point, so amplifier A1 is used as the CM buffer and the drain electrode of current unit remained on the CM level, eliminated the needs to extra CM buffer.
In " maintenance " cycle, DAC sign indicating number 612 is changed, but simulation output 610 does not change, and this is still to disconnect with summing junction SJP and SJN because of square feedback resistance R1 508 and R2 510.When " maintenance " end cycle, S3 506 turn-offs, and S1 502 and S2 504 connect.Resistance R 1 508 is connected back SJP and SJN with R2 510, allows the DAC electric current to be converted into output voltage.Because DAC sign indicating number 612 is at " maintenance " cyclomorphosis, therefore output is not about the rise time of each current unit that switches separately and information or the storage of fall time.So output voltage does not have intersymbol interference.
In Fig. 7, demonstrate the circuit that produces HOLD, HOLD_B and clock 608 into d type flip flop.The rest-set flip-flop that the RESET signal is used for illustrating places reset mode, and HOLD_B is low for height HOLD here.This d type flip flop DFF1 is also by identical RESET signal zero clearing.
Gate AN1 702 and I1 704 produce pulse when the rising edge of DAC_CLK 706 arrives, DAC_CLK 706 is master clocks of transducer here.The duration of the pulse that produces is by determining by the delay of reverser I1 704.Usually, 1ns to 2ns pulse duration is enough to be provided with the rest-set flip-flop that arrives seen in the current silicon technology.When this pulse appears at the input of NO1 708, HOLD_B 710 is set to low, and HOLD 712 is set to height.At this moment, I-V is in " maintenance " stage, remains unchanged at its voltage of this stage.The trailing edge of this pulse provides clock for trigger DFF1 714 and produces high at output Q place then.After the delay of being determined by B1 716, then the output of B1 716 reaches high and HOLD_B710 is provided with back high, and is provided with back HOLD 712 low; I-V also begins to change the electric current that is produced by new DAC sign indicating number.
The DFF1 714 so trailing edge of DAC_CLK generation pulse, this pulse reset successively.The circuit of Fig. 7 is that each rising edge of DAC_CLK repeats identical operations.
An advantage of this circuit is that gate is configured to HOLD 712 easily and HOLD_B 710 produces best crosspoint.This best crosspoint produces minimal disturbances for the summing junction of amplifier, and this is necessary to high-speed cruising.
In addition, because the enough bandwidth in the amplifier, this handover scheme is all insensitive to any variation in the HOLD_B pulse duration.This means that this circuit is insensitive to the shake of being introduced by gate among Fig. 7.This also is another advantage of the present invention.
Because the trailing edge of TRIG is used for providing clock to the d type flip flop array of storage DAC sign indicating number, so when the I-V transducer is in " maintenance " pattern, sign indicating number will takes place change.When passing through the delay approximately equal of reverser I1 and buffer B1, the DAC sign indicating number guarantees and can change in the middle of " maintenance " cycle.
In fact, voltage will appear in the terminals that stride across switch S 3 506 in " maintenance " during the cycle, and this is owing to the non-zero conducting resistance (on-resistance) of the MOS device of realizing S3 506 and flows through resistance R 1 508 and the cause of the magnitude of current of R2 510.The drain voltage of this voltage modulated current unit also can cause distortion.But, the design of being careful minimizes the conducting resistance of S3 506, and if necessary, makes the cloudy altogether grid altogether of current unit, can overcome this problem easily.
Conclusion
Illustrated in the above-described embodiments the DAC output stage has effectively been implemented to belong to the system and method that keeps handover scheme.Though illustrated and described different preferred embodiments, be appreciated that and be not intended to limit the present invention, and be intended to cover all modifications that falls into as in the spirit and scope of the present invention defined in the claims by present disclosure.For example, the present invention should not be subjected to the restriction of specific hardware etc.
Claims (20)
1. the method for the intersymbol interference error of the I-V output stage of a current steering type DAC who is used to eliminate have a plurality of current units, described output stage comprises I-V amplifier, feedback resistance R1 and the R2 with summing junction SJP and SJN at least, and feedback condenser C1 and C2, described method comprises following steps:
Described summing junction SJP and SJN with described feedback resistance R1 and R2 and described current unit and described amplifier in described output stage disconnect;
Described feedback resistance R1 and R2 are linked together to stride across the output formation resistance string of described output stage, and when described I-V amplifier did not link to each other with the described current unit of described current steering type DAC, described feedback condenser C1 and C2 produced hold period to keep the output voltage of described I-V amplifier;
Link to each other with the mid point of described resistance string by output, use the I-V amplifier, keep common mode electrical level with drain electrode during described hold period at described current unit as buffer with described current unit; And when being in described maintenance pattern, the output of described current unit changes the DAC sign indicating number, and
After the DAC sign indicating number is changed, the output of described current unit is disconnected each other, and the suitable output of described feedback resistance and described current unit is reconnected back the summing junction of described I-V transducer.
2. the method for claim 1 is wherein finished the step of described feedback resistance R1 and R2 and described current unit and described summing junction SJP and SJN disconnection via first and second switches.
3. method as claimed in claim 2, wherein said method further comprises the output of the 3rd switch described current unit of short circuit during described hold period, described the 3rd switch links together the end of described feedback resistance R1 and R2, and the other end of described resistance links to each other with the output of described I-V amplifier.
4. method as claimed in claim 3, described the 3rd switch is driven by second inhibit signal wherein said first and second switches by the driving of first inhibit signal, rising edge at the clock that drives described DAC, described first inhibit signal becomes low, described summing junction to pass through to turn-off described first and second switches with described feedback resistance R1 and R2 and I-V amplifier disconnects, and described second inhibit signal becomes height and links to each other via the left-hand side of described the 3rd switch with resistance R 1 and R2 simultaneously.
5. method as claimed in claim 3, wherein gate is designed to produce best crosspoint, and this crosspoint produces minimal disturbances to the described summing junction of described I-V amplifier.
6. method as claimed in claim 3, wherein said I-V amplifier has enough bandwidth, and insensitive to the variation in the pulse duration relevant with described first inhibit signal.
7. the equipment of the intersymbol interference error of the I-V output stage of a current steering type DAC who is used to eliminate have a plurality of current units, described output stage comprises I-V amplifier, feedback resistance R1 and the R2 with summing junction SJP and SJN at least, and feedback condenser C1 and C2, described equipment comprises:
In described output stage, be used for the described summing junction SJP of described feedback resistance R1 and R2 and described current unit and described amplifier and the device of SJN disconnection;
Be used for described feedback resistance R1 and R2 are linked together to stride across the output formation resistance string of described output stage, and when described I-V amplifier did not link to each other with the described current unit of described current steering type DAC, described feedback condenser C1 and C2 produced the device of hold period with the output voltage that keeps described I-V amplifier;
Link to each other with the mid point of described resistance string by output, be used to use the I-V amplifier, during described hold period, common mode electrical level is kept in the drain electrode of described current unit as buffer with described current unit; And be used for changing when output at described current unit is in described maintenance pattern the device of DAC sign indicating number, and
After the DAC sign indicating number is changed, is used for the output of described current unit is disconnected each other, and is used for the suitable output of described feedback resistance and described current unit is reconnected back the device of the summing junction of described I-V transducer.
8. equipment as claimed in claim 7 is wherein finished the described device of described feedback resistance R1 and R2 and described current unit and described summing junction SJP and SJN disconnection via first and second switches.
9. equipment as claimed in claim 8, wherein said equipment is included in the 3rd switch that is used for the output of the described current unit of short circuit during the described hold period, described the 3rd switch links together the end of described feedback resistance R1 and R2, and the other end of described resistance links to each other with the output of described I-V amplifier.
10. equipment as claimed in claim 9, wherein said first and second switches are driven by first inhibit signal, and described the 3rd switch is driven by second inhibit signal, rising edge at the clock that drives described DAC, described first inhibit signal becomes low, described summing junction to pass through to turn-off described first and second switches with described feedback resistance R1 and R2 and I-V amplifier disconnects, and described second inhibit signal becomes height and links to each other via the left-hand side of described the 3rd switch with resistance R 1 and R2 simultaneously.
11. equipment as claimed in claim 9, wherein gate is designed to produce best crosspoint, and this crosspoint produces minimal disturbances to the described summing junction of described I-V amplifier.
12. equipment as claimed in claim 9, wherein said I-V amplifier has enough bandwidth, and insensitive to the variation in the pulse duration relevant with described first inhibit signal.
13. the circuit of the intersymbol interference error of the I-V output stage of a current steering type DAC who is used to eliminate have a plurality of current units, described circuit comprises:
I-V amplifier with summing junction SJP and SJN;
The first feedback resistance R1;
The second feedback resistance R2;
The first feedback condenser C1;
The second feedback condenser C2;
Be used for first switch S 1 that R1 and described summing junction SJP are connected/disconnect and the second switch S2 that is used for R2 and described summing junction SJN are connected/disconnect;
Be used for the 3rd switch S 3 that described feedback resistance R1 and R2 are linked together/disconnect, and when connecting, the output that R1 and R2 stride across described output stage forms resistance string, and when described I-V amplifier did not link to each other with the described current unit of described current steering type DAC, described feedback condenser C1 and C2 produced hold period to keep the output voltage of described I-V amplifier; And
Wherein link to each other with the mid point of described resistance string by output with described current unit, described I-V amplifier is as buffer, keep common mode electrical level with drain electrode during described hold period at described current unit, and after the DAC sign indicating number is changed, the output of described current unit disconnects each other, and the suitable output of described feedback resistance and described current unit is reconnected back the summing junction of described I-V transducer.
14. circuit as claimed in claim 13, wherein said first switch S 1 and second switch S2 are driven by first inhibit signal, and described the 3rd switch is driven by second inhibit signal, rising edge at the clock that drives described DAC, described first inhibit signal becomes low, described summing junction to pass through described first switch S 1 of shutoff and second switch S2 with described feedback resistance R1 and R2 and I-V amplifier disconnects, and described second inhibit signal becomes height and links to each other via the left-hand side of described the 3rd switch S 3 with resistance R 1 and R2 simultaneously.
15. circuit as claimed in claim 13, wherein said gate is designed to produce best crosspoint, and this crosspoint produces minimal disturbances to the described summing junction of described I-V amplifier.
16. circuit as claimed in claim 13, wherein said I-V amplifier has enough bandwidth, and insensitive to the variation in the pulse duration relevant with described first inhibit signal.
17. the circuit of the intersymbol interference error of the I-V output stage of a current steering type DAC who is used to eliminate have a plurality of current units, described circuit comprises:
Be used for first switch S 1 that the feedback resistance R1 and the summing junction SJP of I-V amplifier are connected/disconnect;
Be used for second switch S2 that the feedback resistance R2 and the described summing junction SJN of described I-V amplifier are connected/disconnect;
Be used for the 3rd switch S 3 that described feedback resistance R1 and R2 are linked together/disconnect, and when connecting, the output that R1 and R2 stride across described output stage forms resistance string, and when described I-V amplifier did not link to each other with the described current unit of described current steering type DAC, described feedback condenser C1 and C2 produced hold period to keep the output voltage of described I-V amplifier; And
Wherein link to each other with the mid point of described resistance string by output with described current unit, described I-V amplifier is as buffer, keep common mode electrical level with drain electrode during described hold period at described current unit, and after the DAC sign indicating number is changed, the output of described current unit disconnects each other, and the suitable output of described feedback resistance and described current unit is reconnected back the summing junction of described I-V amplifier.
18. circuit as claimed in claim 17, wherein said first switch S 1 and second switch S2 are driven by first inhibit signal, and described the 3rd switch is driven by second inhibit signal, rising edge at the clock that drives described DAC, described first inhibit signal becomes low, described summing junction to pass through described first switch S 1 of shutoff and second switch S2 with described feedback resistance R1 and R2 and I-V amplifier disconnects, and described second inhibit signal becomes height and links to each other via the left-hand side of described the 3rd switch S 3 with resistance R 1 and R2 simultaneously.
19. circuit as claimed in claim 17, wherein gate is designed to produce best crosspoint, and this crosspoint produces minimal disturbances to the described summing junction of described I-V amplifier.
20. circuit as claimed in claim 17, wherein said I-V amplifier has enough bandwidth, and insensitive to the variation in the pulse duration relevant with described first inhibit signal.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/476,476 | 2006-06-28 | ||
| US11/476,476 US7307568B1 (en) | 2004-11-19 | 2006-06-28 | Return-to-hold switching scheme for DAC output stage |
| PCT/US2007/071990 WO2008002858A2 (en) | 2006-06-28 | 2007-06-25 | Return-to-hold switching scheme for dac output stage |
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| Publication Number | Publication Date |
|---|---|
| CN101507117A CN101507117A (en) | 2009-08-12 |
| CN101507117B true CN101507117B (en) | 2011-10-26 |
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| CN2007800307022A Active CN101507117B (en) | 2006-06-28 | 2007-06-25 | Return-to-hold switching scheme for DAC output stage |
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| CN (1) | CN101507117B (en) |
| GB (1) | GB2453298B (en) |
| WO (1) | WO2008002858A2 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9065477B2 (en) * | 2013-09-03 | 2015-06-23 | Analog Devices Global | Linear and DC-accurate frontend DAC and input structure |
| US9065463B2 (en) * | 2013-10-11 | 2015-06-23 | Analog Devices Global | Method and apparatus for reducing capacitor induced ISI in DACS |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1625840A (en) * | 2002-05-27 | 2005-06-08 | 诺基亚公司 | Method for calibrating digital-to-analog converter and digital-to-analog conwerter |
| CN1650524A (en) * | 2002-04-26 | 2005-08-03 | 艾利森电话股份有限公司 | Digital-to-analog converter having error correction |
| CN1742435A (en) * | 2003-01-24 | 2006-03-01 | 模拟设备公司 | Current DAC code independent switching |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6417793B1 (en) * | 2000-02-04 | 2002-07-09 | Rockwell Technologies, Llc | Track/attenuate circuit and method for switched current source DAC |
| US7002499B2 (en) * | 2004-01-21 | 2006-02-21 | Hrl Laboratories, Llc | Clocked D/A converter |
-
2007
- 2007-06-25 CN CN2007800307022A patent/CN101507117B/en active Active
- 2007-06-25 GB GB0900998A patent/GB2453298B/en not_active Expired - Fee Related
- 2007-06-25 WO PCT/US2007/071990 patent/WO2008002858A2/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1650524A (en) * | 2002-04-26 | 2005-08-03 | 艾利森电话股份有限公司 | Digital-to-analog converter having error correction |
| CN1625840A (en) * | 2002-05-27 | 2005-06-08 | 诺基亚公司 | Method for calibrating digital-to-analog converter and digital-to-analog conwerter |
| CN1742435A (en) * | 2003-01-24 | 2006-03-01 | 模拟设备公司 | Current DAC code independent switching |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2008002858A3 (en) | 2008-03-13 |
| WO2008002858A2 (en) | 2008-01-03 |
| GB2453298B (en) | 2011-04-06 |
| CN101507117A (en) | 2009-08-12 |
| GB2453298A (en) | 2009-04-01 |
| GB0900998D0 (en) | 2009-03-04 |
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