CN101499799A - Circuit and method for time clock signal synchronization - Google Patents
Circuit and method for time clock signal synchronization Download PDFInfo
- Publication number
- CN101499799A CN101499799A CNA200810148002XA CN200810148002A CN101499799A CN 101499799 A CN101499799 A CN 101499799A CN A200810148002X A CNA200810148002X A CN A200810148002XA CN 200810148002 A CN200810148002 A CN 200810148002A CN 101499799 A CN101499799 A CN 101499799A
- Authority
- CN
- China
- Prior art keywords
- input
- signal
- clock signal
- frequency
- feedback
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses a frequency/phase discriminator, which is connected with a charge pump and a resistor-capacitor oscillator in sequence. The input end of the frequency/phase discriminator is connected with an input impulse signal and a feedback clock signal; FPD carries out comparison of the frequency and the phase to the input impulse signal and the feedback clock signal; when the frequency and the phase is same, the FPD generates a digital level signal so as to lead the output voltage of a CP connected with the FPD to keep a certain voltage value; when the frequency and the phase is different, the FPD generates a digital level signal so as to control the change of the output voltage of the CP; the invention is a sampling clock which uses data impulse width to restore the data, the principle can save a crystal oscillator, reduce the product cost and simultaneously realize that the circuit structure is very simple.
Description
Technical field
The present invention relates to integrated circuit fields, circuit and method that particularly a kind of clock signal is synchronous.
Background technology
Obtain the clock with data sync, traditional method is by plug-in low frequency crystal oscillator, produces the clock signal of certain frequency, obtains the clock of required frequency then by frequency multiplication.But crystal oscillator price height, the design cycle is long, and this must increase the cost of product.
Summary of the invention
The object of the invention provides synchronous circuit of a kind of clock signal and method, utilizes the data pulse width to recover the sampling clock of these data, can save crystal oscillator, reduces product cost.
Technical scheme of the present invention is as follows:
The circuit that a kind of clock signal is synchronous, it is characterized in that: comprise a frequency discrimination/phase discriminator (FPD), charge pump (CP) and RC oscillator (RC oscillator), the pulse signal of the input termination input of described frequency discrimination/phase discriminator and the clock signal of feedback, the output of frequency discrimination/phase discriminator connects the input of charge pump, the electric charge delivery side of pump connects the input of RC oscillator, and the output of RC oscillator connects the input of frequency discrimination/phase discriminator.
The clock signal of described feedback is exported by the RC oscillator.
The method that a kind of clock signal is synchronous, it is characterized in that: FPD carries out the comparison of frequency and phase place to the pulse signal of input and the clock signal of feedback, when frequency is identical with phase place, FPD produces digital signal level makes the output voltage of CP keep certain magnitude of voltage, when frequency and phase place not simultaneously, FPD produces digital signal level changes CP as the input control signal of CP output voltage, the clock signal that makes the pulse signal of input and feedback by the CP output voltage after changing is identical on frequency and phase place, and this moment, the output voltage of CP kept constant.
The digital signal level that described FPD produces is ＂ 1 " or ＂ 0 ", corresponding high level of difference and low level.This digital signal level is the control signal of CP, the change of the output voltage of control CP, and the output voltage of CP is as the input reference voltage of RC oscillator.
The output voltage of described CP is used to provide the input reference voltage of RC oscillator.
When described clock signal when pulse signal of importing and feedback was identical, it is constant that the input reference voltage of RC oscillator keeps; When the pulse signal of input and the clock signal of feedback not simultaneously, the input reference voltage of RC oscillator changes, the clock signal that the change of this input reference voltage always makes the pulse signal of input and feedback is tending towards identical gradually on frequency and phase place, this moment, the output clock frequency of RC oscillator equaled the clock sampling frequency of input signal.
The RC oscillator produces the clock signal of fixed frequency under described input reference voltage, this clock signal is as clock signal, simultaneously also as the feedback clock signal of FPD input.
The present invention utilizes FPD that the pulse signal of input and the RC oscillator clock frequency and the phase place of feedback are compared, and the output of FPD is adjusted the output of CP, the i.e. reference voltage of RC oscillator as the control signal of CP.The RC oscillator is according to the variation generation and the corresponding clock signal of reference voltage of reference voltage.
When FPD compares the pulse signal of input and the clock signal of feedback, if the high level pulsewidth is greater than the cycle of feedback clock signal in the pulse signal of input, then the sampling clock frequency of Shu Ru pulse signal is less than the frequency of feedback clock signal, if the high level pulsewidth is less than the cycle of feedback clock signal in the pulse signal of input, then the sampling clock frequency of Shu Ru pulse signal is greater than the frequency of feedback clock signal.
Perhaps, when FPD compares the pulse signal of input and the clock signal of feedback, if low-level pulse width is greater than the cycle of feedback clock signal in the pulse signal of input, then the sampling clock frequency of Shu Ru pulse signal is less than the frequency of feedback clock signal, if low-level pulse width is less than the cycle of feedback clock signal in the pulse signal of input, then the sampling clock frequency of Shu Ru pulse signal is greater than the frequency of feedback clock signal.
When pwm input signal during greater than cycle of feedback clock signal, the digital signal level of FPD output changes the reference voltage (trend of variation can be decided according to the design of circuit) of RC oscillator by CP.The change of reference voltage forces the RC concussion cycle close to pwm input signal gradually, and both are equated, promptly reaches RC concussion frequency and input pulse signals sampling frequency and equates.
In like manner, when pwm input signal during less than cycle of feedback clock signal, the digital signal level of FPD output changes the reference voltage (trend of variation can be decided according to the design of circuit) of RC oscillator by CP.The change of reference voltage forces the RC concussion cycle close to pwm input signal gradually, and both are equated.
When the cycle of pwm input signal and feedback clock signal is identical, the digital signal level of FPD output remains unchanged the output voltage of CP, the reference voltage that is the RC oscillator is constant, RC oscillator output frequency remains unchanged, and it is identical with the pulse duration of input pulse signal promptly to reach the RC concussion cycle.
Because the pulsewidth of input pulse signal equals the sampling period of its sampled signal, so when the cycle of the output oscillator signal of RC oscillator equaled the pulse duration of input pulse signal, the clock frequency of RC oscillator output equaled input pulse signals sampling clock frequency.
Beneficial effect of the present invention is as follows:
The present invention utilizes the data pulse width to recover the sampling clock of these data, and such principle can have been saved crystal oscillator, reduces product cost, and the circuit structure of Shi Xianing is very simple simultaneously.
Description of drawings
Fig. 1 is circuit theory diagrams of the present invention
Fig. 2 is data in the embodiment of the invention ' 010 ' and ' 101 ' sequential chart
Fig. 3 is the application schematic diagram of example of the present invention
Embodiment
As shown in Figure 1, the circuit that a kind of clock signal is synchronous, comprise a frequency discrimination/phase discriminator (FPD), charge pump (CP) and RC oscillator (RC oscillator), the pulse signal of the input termination input of described frequency discrimination/phase discriminator and the clock signal of feedback, the output of frequency discrimination/phase discriminator connects the input of charge pump, and the electric charge delivery side of pump connects the input of RC oscillator, and the output of RC oscillator connects the input of frequency discrimination/phase discriminator.
The clock signal of described feedback is exported by the RC oscillator.
The method that a kind of clock signal is synchronous, FPD carries out the comparison of frequency and phase place to the pulse signal of input and the clock signal of feedback, when frequency is identical with phase place, FPD produces digital signal level makes the output voltage of CP keep certain magnitude of voltage, when frequency and phase place not simultaneously, FPD produces digital signal level changes CP as the input control signal of CP output voltage, the clock signal that makes the pulse signal of input and feedback by the CP output voltage after changing is identical on frequency and phase place, and this moment, the output voltage of CP kept constant.
The digital signal level that described FPD produces is ＂ 1 " or ＂ 0 ", corresponding high level of difference and low level.This digital signal level is the control signal of CP, the change of the output voltage of control CP, and the output voltage of CP is as the input reference voltage of RC oscillator.
The output voltage of described CP is used to provide the input reference voltage of RC oscillator.
When described clock signal when pulse signal of importing and feedback was identical, it is constant that the input reference voltage of RC oscillator keeps; When the pulse signal of input and the clock signal of feedback not simultaneously, the input reference voltage of RC oscillator changes, the clock signal that the change of this input reference voltage always makes the pulse signal of input and feedback is tending towards identical gradually on frequency and phase place, this moment, the output clock frequency of RC oscillator equaled the clock sampling frequency of input signal.
The RC oscillator produces the clock signal of fixed frequency under described input reference voltage, this clock signal is as clock signal, simultaneously also as the feedback clock signal of FPD input.
The present invention utilizes FPD that the pulse signal of input and the RC oscillator clock frequency of feedback are compared, and the output of FPD is adjusted the output of CP, the i.e. reference voltage of RC oscillator as the control signal of CP.The RC oscillator is according to the variation generation and the reference voltage corresponding clock signals of reference voltage.
When FPD compares the pulse signal of input and the clock signal of feedback, if the high level pulsewidth is greater than the cycle of feedback clock signal in the pulse signal of input, then the sampling clock frequency of Shu Ru pulse signal is less than the frequency of feedback clock signal, if the high level pulsewidth is less than the cycle of feedback clock signal in the pulse signal of input, then the sampling clock frequency of Shu Ru pulse signal is greater than the frequency of feedback clock signal.
Perhaps, when FPD compares the pulse signal of input and the clock signal of feedback, if low-level pulse width is greater than the cycle of feedback clock signal in the pulse signal of input, then the sampling clock frequency of Shu Ru pulse signal is less than the frequency of feedback clock signal, if low-level pulse width is less than the cycle of feedback clock signal in the pulse signal of input, then the sampling clock frequency of Shu Ru pulse signal is greater than the frequency of feedback clock signal.
As shown in Figure 2, when FPD detected the input pulse signal and ＂ 010 ＂ or ＂ 101 ＂ sequential occur, FPD compared input pulse signal and the clock signal that feeds back to.＂ 010 when input signal " when the high level pulsewidth is greater than cycle of feedback clock signal in the sequential; the frequency of the sampling clock frequency of input signal less than feedback clock signal being described; opposite; as input signal ＂ 101 " sequential high level pulsewidth is during less than cycle of feedback clock signal, and the sampling clock frequency of input signal is just greater than the frequency of feedback clock signal.If input signal ＂ 010 " cycle of sequential high level pulsewidth and feedback clock signal equates that the sampling clock frequency of explanation input signal equals the frequency of feedback clock signal.In like manner, when input signal occurs " 101 " control methods of sequential is identical, just gets ＂ 101 this moment " low-level pulse width and feedback clock signal cycle of sequential make comparisons.
If medium-term and long-term constant high level or the constant low level of keeping of signal thinks that then FPD does not make comparisons to the clock signal of input pulse signal and feedback, FPD lost efficacy.This moment, the output voltage of CP was constant, constant reference voltage was provided for the RC oscillator, and the output of RC oscillator is constant.Notice that the present invention is the effect of kind signal Synchronization when not reaching in this case, so input signal should be avoided keeping constant high level or constant low level for a long time, this point has certain requirement on communication protocol.
When pwm input signal (be input pulse signal when ＂ 010 ＂ or ＂ 101 ＂ occurring high level or low level pulsewidth) during greater than cycle of feedback clock signal, the digital signal level of FPD output is by the reference voltage (trend of variation can be decided according to the design of circuit) of CP output voltage change RC oscillator.The change of reference voltage forces the RC concussion cycle close to pwm input signal gradually, and both are equated, promptly reaches RC concussion frequency and input pulse signals sampling frequency and equates.
In like manner, when pwm input signal during less than cycle of feedback clock signal, the digital signal level of FPD output is by the reference voltage (trend of variation can be decided according to the design of circuit) of CP output voltage change RC oscillator.The change of reference voltage forces the RC concussion cycle close to pwm input signal gradually, and both are equated.
When the cycle of pwm input signal and feedback clock signal is identical, the digital signal level of FPD output stops the change of CP output voltage, the reference voltage that is the RC oscillator is constant, and RC oscillator output frequency remains unchanged, and it is identical with the pulse duration of input pulse signal promptly to reach the RC concussion cycle.
Because the pulsewidth of input pulse signal equals the sampling period of its sampled signal, so when the cycle of the output oscillator signal of RC oscillator equaled the pulse duration of input pulse signal, the clock frequency of RC oscillator output equaled input pulse signals sampling clock frequency.
As shown in Figure 3, the present invention sends out application concrete, its operation principle is: when two low speed/full speed USB (USB) transceiver swap datas, can reach two transceiver clock signals synchronous transmission by the sampling clock of the data restore data on the data/address bus.
Be transmitted in both directions among Fig. 3, but only provided slave unit 1 for convenience of description to equipment 2 one-way transmission schematic diagrams.The dateout D+ of transceiver is as input signal of the present invention in the equipment 1, and by the present invention, the sampling clock of input signal is extracted, and the clock of extraction is as the input clock of equipment 2 transceivers.
Claims (8)
1, the synchronous circuit of a kind of clock signal, it is characterized in that: comprise a frequency discrimination/phase discriminator FPD, charge pump CP and RC oscillator, the pulse signal of the input termination input of described frequency discrimination/phase discriminator and the clock signal of feedback, the output of frequency discrimination/phase discriminator connects the input of charge pump, the electric charge delivery side of pump connects the input of RC oscillator, and the output of RC oscillator connects the input of frequency discrimination/phase discriminator.
2, according to the synchronous circuit of the described a kind of clock signal of claim 1, it is characterized in that: the clock signal of described feedback is exported by the RC oscillator.
3, the synchronous method of a kind of clock signal, it is characterized in that: FPD carries out the comparison of frequency and phase place to the pulse signal of input and the clock signal of feedback, when frequency is identical with phase place, FPD produces digital signal level makes the output voltage of CP keep certain magnitude of voltage, when frequency and phase place not simultaneously, FPD produces digital signal level changes CP as the input control signal of CP output voltage, the clock signal that makes the pulse signal of input and feedback by the CP output voltage after changing is identical on frequency and phase place, and this moment, the output voltage of CP kept constant.
4, according to claim 1 or the synchronous method of 3 described a kind of clock signals, it is characterized in that: it is ＂ 1 that FPD sends digital signal level to the pulse signal of input and the clock signal of feedback after relatively " or ＂ 0 ", corresponding high level and low level respectively.
5, according to the synchronous method of the described a kind of clock signal of claim 3, it is characterized in that: when the pulse signal of input was identical with the clock signal of feedback, it is constant that the input reference voltage of RC oscillator keeps; When the pulse signal of input and the clock signal of feedback not simultaneously, the input reference voltage of RC oscillator changes, the clock signal that the change of this input reference voltage always makes the pulse signal of input and feedback is tending towards identical gradually on frequency and phase place, this moment, the output clock frequency of RC oscillator equaled the clock sampling frequency of input signal.
6, according to the synchronous method of the described a kind of clock signal of claim 5, it is characterized in that: described RC oscillator produces the clock signal of fixed frequency under input reference voltage, this clock signal is as clock signal, simultaneously also as the feedback clock signal of FPD input.
7, according to the synchronous method of the described a kind of clock signal of claim 3, it is characterized in that: when FPD compares the pulse signal of input and the clock signal of feedback, if the high level pulsewidth is greater than the cycle of feedback clock signal in the pulse signal of input, then the sampling clock frequency of Shu Ru pulse signal is less than the frequency of feedback clock signal, if the high level pulsewidth is less than the cycle of feedback clock signal in the pulse signal of input, then the sampling clock frequency of Shu Ru pulse signal is greater than the frequency of feedback clock signal; Perhaps, when FPD compares the pulse signal of input and the clock signal of feedback, if low-level pulse width is greater than the cycle of feedback clock signal in the pulse signal of input, then the sampling clock frequency of Shu Ru pulse signal is less than the frequency of feedback clock signal, if low-level pulse width is less than the cycle of feedback clock signal in the pulse signal of input, then the sampling clock frequency of Shu Ru pulse signal is greater than the frequency of feedback clock signal.
8, according to the synchronous method of the described a kind of clock signal of claim 3, it is characterized in that: when pwm input signal during greater than cycle of feedback clock signal, the digital signal level of FPD output is by the discharge and recharge reference voltage that change RC oscillator of CP to electric capacity; When pwm input signal during less than cycle of feedback clock signal, the digital signal level of FPD output is by the discharge and recharge reference voltage that change RC oscillator of CP to electric capacity; When the cycle of pwm input signal and feedback clock signal is identical, the digital signal level of FPD output stops CP constant with the maintenance capacitance voltage to capacitor charge and discharge, the reference voltage that is the RC oscillator is constant, RC oscillator output frequency remains unchanged, and RC is identical with the pulse duration of input pulse signal cycle of oscillation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA200810148002XA CN101499799A (en) | 2008-12-25 | 2008-12-25 | Circuit and method for time clock signal synchronization |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA200810148002XA CN101499799A (en) | 2008-12-25 | 2008-12-25 | Circuit and method for time clock signal synchronization |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101499799A true CN101499799A (en) | 2009-08-05 |
Family
ID=40946702
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA200810148002XA Pending CN101499799A (en) | 2008-12-25 | 2008-12-25 | Circuit and method for time clock signal synchronization |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101499799A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106911322A (en) * | 2015-12-23 | 2017-06-30 | 意法半导体股份有限公司 | Generate the circuit and method of the adjustable clock signal of dutycycle |
| CN111027108A (en) * | 2019-08-13 | 2020-04-17 | 哈尔滨安天科技集团股份有限公司 | Sequential logic safety detection method and device of low-speed synchronous serial bus |
-
2008
- 2008-12-25 CN CNA200810148002XA patent/CN101499799A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106911322A (en) * | 2015-12-23 | 2017-06-30 | 意法半导体股份有限公司 | Generate the circuit and method of the adjustable clock signal of dutycycle |
| CN106911322B (en) * | 2015-12-23 | 2020-10-27 | 意法半导体股份有限公司 | Circuit and method for generating clock signal with adjustable duty ratio |
| CN111027108A (en) * | 2019-08-13 | 2020-04-17 | 哈尔滨安天科技集团股份有限公司 | Sequential logic safety detection method and device of low-speed synchronous serial bus |
| CN111027108B (en) * | 2019-08-13 | 2024-02-13 | 安天科技集团股份有限公司 | Sequential logic safety detection method and device for low-speed synchronous serial bus |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10185683B2 (en) | Bus interface system | |
| US10528502B2 (en) | Power management system for a bus interface system | |
| CN103887985A (en) | Control device and control method for wireless induction type power supply | |
| CN103812333A (en) | Control circuit of charge pump and charge pump circuit | |
| CN114201440B (en) | Clock detection method, circuit, serial port communication system, medium and equipment | |
| CN103684943A (en) | Bus system with power supply transmission and data communication functions | |
| CN103248223A (en) | Clock circuit and boost regulator | |
| CN101499799A (en) | Circuit and method for time clock signal synchronization | |
| CN101604182A (en) | Automatically adjust the method and the clock frequency regulating circuit of clock frequency | |
| CN103780849A (en) | Focal plane time schedule controller for synchronous electric charge transfer of TDICCD | |
| CN101765244B (en) | Method and system for realizing isolating low-frequency clock signal transmission among split modules | |
| CN102170345B (en) | High definition camera self-adaption digitization external synchronization method | |
| CN101051069B (en) | Detection method and system for AC coupling differential circuit receiver connection state | |
| CN102854916B (en) | Method for achieving accurate clock synchronization of USB (universal serial bus) device | |
| CN101719767B (en) | Phase-locked loop with quick response | |
| CN204334523U (en) | Power-up time delay circuit, switch | |
| CN104283569A (en) | Signal decoding circuit | |
| CN102568598A (en) | Shift-register-based anti-interference method | |
| CN105576966A (en) | Charge pump circuit for generating positive and negative voltage sources | |
| CN203775182U (en) | RS232 and infrared communication interface switching circuit capable of automatically taking power | |
| CN203310898U (en) | Optical communication data acquisition module | |
| CN105450221B (en) | Multichannel time sequence recovery device | |
| CN102355241B (en) | Synchronous circuit of pulse width modulation circuit | |
| CN202364116U (en) | Slope compensation circuit of full bridge transformation controller | |
| CN109817151A (en) | Display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Open date: 20090805 |