CN101494084B - Non-volatile dynamic random access memory - Google Patents
Non-volatile dynamic random access memory Download PDFInfo
- Publication number
- CN101494084B CN101494084B CN2009101281143A CN200910128114A CN101494084B CN 101494084 B CN101494084 B CN 101494084B CN 2009101281143 A CN2009101281143 A CN 2009101281143A CN 200910128114 A CN200910128114 A CN 200910128114A CN 101494084 B CN101494084 B CN 101494084B
- Authority
- CN
- China
- Prior art keywords
- voltage
- data
- unit
- circuit
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Read Only Memory (AREA)
Abstract
The invention provides a method for driving a non-volatile dynamic random access memory, wherein the memory comprises a circuit with a plurality of storage unit modules for a plurality of unit cells; an internal voltage generator for receiving an external voltage and generating a plurality of internal voltages with different levels; a switching device for supplying one of the plurality of internal voltages to a word line, a bit line and a capacitor plate line; and a mode controller for controlling the switching device. The mode controller controls the switching device. The non-volatile dynamic random access memory is normally operated through regulating the threshold voltages of floating gates in the unit cells.
Description
The application is that application number is the dividing an application of one Chinese patent application of 200410058544X.
Technical field
The present invention relates to a kind of semiconductor memory apparatus, relate in particular to a kind of apparatus and method of driving non-volatile dram (NVDRAM) and method of operating thereof.
Background technology
Generally speaking, semiconductor memory apparatus can be divided into RAS (hereinafter to be referred as RAM) and ROM (read-only memory) (hereinafter to be referred as ROM).RAM is a volatibility, and ROM then is non-volatile.In other words, even remove power supply, ROM can also keep the data of storing, and still, if remove power supply, then RAM just can not keep the data of storing.
The many RAM that developed adopt the advantage of the stored charge ability of field-effect transistor, and are used as storage unit.This element can be dynamic or static in essence.As everyone knows, dynamic cell can only adopt a field-effect transistor, and static cell then can positive and negative configuration be arranged.Because when the power supply supply voltage that is fed to storer loses or closes, the information that is stored in these unit will lose, so these several kinds of unit are called volatile cells.Under the essential volatilized situation that keeps storing, must alternate source power like battery system, be connected to storer, under the situation of primary source failure, to use.
Figure 1A is the circuit diagram of the dynamic cell in traditional volatibility dynamic ram device.
As shown in the figure, use capacitor Cap storage data, that is, and the high or low data of logic " 1 " or " 0 ".When MOS transistor MOS passes through word line voltage Vg conducting, capacitor Cap response bit-line voltage Vb1 charge or discharge.Bit-line voltage Vb1 is when logic high, and then capacitor Cap is recharged, i.e. storage ' 1 ".Otherwise, capacitor Cap discharge, i.e. storage " 0 ".At this, the printed line of capacitor Cap is supplied by plate line voltage Vcp.Generally speaking, plate line voltage Vcp is the half the of 0V or supply voltage.
Simultaneously; For just can maintenance information without alternate source power; The device of convention can provide variable threshold voltage, as has the field effect crystal of metal-nitride-oxide-silicon (MNOS) and have the field-effect transistor of floating grid, and can be for a long time with non-volatile mode canned data.Through incorporating non-volatile device into storage unit, when primary power generation power interruption or inefficacy, need not back up or alternate source power, with reservation information, the volatile cells of normal running just can be provided.
Use the non-volatile memory cells of non-volatile MNOS transistor or related device to be stored in the one period reasonable time cycle of information in the unit with can keeping volatibility.But these devices need high-voltage pulse, are used to write and erasure information.
Below, will specify the conventional non-volatile dynamic cell with reference to United States Patent (USP).
For example; Deliver on October 28th, 1975 by J.J.Chang and R.A.Kenyon for one piece; Denomination of invention is No. the 3rd, 916,390, the United States Patent (USP) that often is cited of " DYNAMIC MEMORY WITH NON-VOLATILE BACK-UP MODE "; It has disclosed the use of using the silicon dioxide and the double insulator of silicon nitride formation, so that non-volatile ground canned data during power-fail.Another can store the example of the dynamic cell of non-volatile information through using the NMOS structure; Comprise that one piece is delivered on October 25th, 1977 by people such as K.U.Stein; Its denomination of invention is No. the 4th, 055,837, the United States Patent (USP) of " DYNAMIC SINGLE-TRANSISTOR MEMORY ELEMENT FOR RELATIVELY PERMANENT MEMORIES "; Deliver on November 20th, 1979 by W.Spence with one piece; Denomination of invention is No. the 4th, 175,291, the United States Patent (USP) of " NON-VOLATILE RANDOM ACCESS MEMORY CELL ".These dynamic cells with non-volatile ability can have gratifying operation.But they need bigger cellar area usually, and higher voltage is used for volatility operator scheme or archive memory.
Delivered in 1984 by DiMaria and Donelli J. at one piece; Its denomination of invention is the United States Patent (USP) the 4th of " NON-VOLATILE RAM EDVICE "; 471; In No. 471, a kind of non-volatile DRAM (NVDRAM) with a plurality of field-effect transistor DRAM floating grids is provided, it has the characteristic of nonvolatile memory.NVDRAM uses floating grid, is used for non-volatile ground canned data when power-fail, and utilizes the bielectron on the transmission gate to inject body stack architecture (DEIS), and being used for can restore data after power up.The main shortcoming in this kind unit is: because the DEIS stack architecture is positioned at the bit line side top of unit, so the data in all unit all cannot be transferred to floating grid from the capacitor parallel connection.These data will be earlier through the conducting transmission transistor, and then the voltage of sensing supply on bit line reads.
In order to overcome above-mentioned shortcoming; People such as Acovic deliver the United States Patent (USP) the 5th of a piece " NON-VOLATILE DRAM CELL " by name on July 19th, 1994; 331, No. 188, wherein disclose a kind of single-transistor closely non-volatile DRAM unit and manufacturing approach thereof.In this patent by people such as Acovic, channel oxide or bielectron that the DRAM unit has between memory node and floating grid inject body structure, when being used for the power interruption when single-transistor structure closely, can keep Nonvolatile data.
But in above-mentioned DRAM unit, the plate line voltage of capacitor is connected to ground voltage.The electric field of capacitor only produces through the voltage that is fed to word line and bit line.Therefore, floating grid should comprise two-layer, and the size of DRAM unit should increase.In addition, the manufacturing approach of this DRAM unit and technology can be more complicated.Compare with the adjustable DRAM of plate line voltage unit, because word line and bit line should be supplied quite high voltage, so NVDRAM can consume bigger power.
Summary of the invention
Therefore, the purpose of this invention is to provide the device and method of a kind of driving non-volatile DRAM (NVDRAM), wherein NVDRAM has the adjustable DRAM of plate line voltage unit.
According to an aspect of the present invention, a kind of unit cell that is included in the non-volatile DRAM (NVDRAM) is provided, it comprises: the control grid layer that is connected to word line; Be used to store the capacitor of data; Be used for the storage data transmission of the capacitor floating transistor to bit line, the grid of this floating transistor is an individual layer and as interim dot data memory; And first insulation course between the grid of control grid layer and floating transistor, the voltage that wherein is fed to the body of floating transistor is controllable.
According to a further aspect in the invention, a kind of unit cell that is included in the non-volatile DRAM (NVDRAM) is provided, it comprises: the control grid layer that is made of metal and is connected to word line; Be used to store the capacitor of data; And be used for the storage data transmission of the capacitor floating transistor to bit line, the grid of this floating transistor is a nitride individual layer and as interim dot data memory, the voltage that wherein is fed to the body of floating transistor is controllable.
According to a further aspect in the invention; Provide a kind of being used for to drive the circuit that non-volatile DRAM (NVDRAM) comprises a plurality of storage unit modules of a plurality of unit cells, it comprises: be used to receive external voltage and the internal voltage generator that produces a plurality of builtin voltages with variant level; One of them that is used for a plurality of builtin voltages is fed to the switchgear of word line, bit line and capacitor printed line; And be used for the mode controller of CS device, wherein, mode controller CS device operates under the normalization pattern through the threshold voltage of adjusting floating grid in the said unit cell.
According to a further aspect in the invention; Providing a kind of is used for operation and has a plurality of storage unit; And each unit all has a capacitor and the method with transistorized non-volatile DRAM (NYDRAM) of floating grid, and it comprises the following steps: that (A) fills the logic high data to the capacitor of all storage unit; And (B) to having the capacitor discharge in the transistorized storage unit that its floating grid stores the logic high data.
This method also comprises the step (C) that refreshes a plurality of capacitors.
In the method: through using some word lines and bit line, a plurality of storage unit are arranged in matrix, step (C) is carried out line by line.
In the method, step (A) comprises the following steps: that (A-1) is to being connected to a certain word line supply first threshold voltage of a plurality of storage unit, with the floating transistor in all storage unit of conducting; (A-2) the logic high data are write in the capacitor of the storage unit that is connected to word line; And (A-3) repeating step (A-1) and (A-2), all be charged to the voltage level of logic high data up to all capacitors in a plurality of storage unit.
According to a further aspect in the invention; Providing a kind of is used for operation and has a plurality of storage unit; And each unit all has a capacitor and the method with transistorized non-volatile DRAM (NVDRAM) of floating grid, its comprise the following steps: (A) to the word line supply by the defined voltage of following equation: V
W1=V
B1p+ (V
Th-H+ V
Th-L)/2, wherein V
B1pBe bit-line pre-charge voltage, V
Th-HBe first target threshold voltage, and V
Th-LIt is second target threshold voltage; Reaching (B), whether response lag voltage is V
Th-HOr V
Th-L, logic high data or low-level data are write capacitor.
This method also comprises: (C) through each word line supply being higher than the voltage level of logic high data, refresh a plurality of storage unit.
In the method: step (A) also comprises except being supplied with V
W1Word line beyond the step (A-1) of other word line supply predetermined negative voltage.
According to a further aspect in the invention; Providing a kind of is used for operation and has a plurality of storage unit; And each unit all has a capacitor and the method with transistorized non-volatile DRAM (NVDRAM) of floating grid; It comprises the following steps: that (A) transistorized all grids in all storage unit supply first predetermined voltage, so that electronics is inserted floating grid; (B) to capacitor chargings all in all storage unit; (C) transistorized threshold voltage is reduced to first threshold voltage.
This method also comprises: (E) before in step (A), and the data of collecting in the backup capacitor; And, (F) in step (C) afterwards, backed up data is stored in the capacitor again.
In the method, step (B) comprises the following steps: (B-1) voltage to the side supply 0V of capacitor; Reach (B-2) level voltage of pairs of bit line supply logic high data.
In the method, step (C) comprises the following steps: that (C-1) removes the electronics in the grid of the floating transistor in the storage unit; (C-2) through supplying second threshold voltage, capacitor is discharged to the grid of the floating transistor in the storage unit; Reaching (C-3), repeating step (C-1) all discharges up to all capacitors to step (C-2).
In the method: step (C-1) comprises the following steps: (C-1-a) grid supply negative voltage to the floating transistor in all storage unit; (C-1-b) to the voltage level of the sheet metal of capacitor in storage unit supply logic high data; Reach the capacitor that (C-1-c) electronics in the grid of floating transistor is moved on to the stored logic high level data.
In the method: step (C-2) comprises the following steps: that (C-2-a) supplies second threshold voltage to the grid of floating transistor; And (C-2-b) will have capacitor discharge in some storage unit of the floating transistor through the second threshold voltage conducting.
In the method: step (C) comprises the step (C-4) that refreshes all storage unit.
In the method, through using some word lines and bit line a plurality of storage unit are arranged in matrix, step (C) is carried out line by line.
In the method, capacitor is a coupling condenser.
According to a further aspect in the invention; Providing a kind of is used for operation and has a plurality of storage unit; And each unit all has a capacitor and the method with transistorized non-volatile DRAM (NVDRAM) of floating grid, and it comprises the following steps: that (A) removes the electronics in the floating grid of the storage unit that stores the logic high data; (B) supply second threshold voltage through the transistorized grid in all storage unit, make the capacitor discharge; Reaching (C), repeating step (A) all discharges up to all capacitors to step (B).
In the method: step (A) comprises the following steps: (A-1) grid supply negative voltage to the floating transistor in all storage unit; (A-2) to the voltage level of the sheet metal of capacitor in storage unit supply logic high data; Reach the capacitor that (A-3) optionally the electronics in the grid of floating transistor is moved on to the stored logic high level data.
In the method: step (B) comprises the following steps: that (B-1) supplies second threshold voltage to the grid of floating transistor; Reach (B-2) will have and discharge through the capacitor in transistorized some storage unit of the second threshold voltage conducting.
In the method: step (B) comprises the step (B-3) of refresh of memory cells.
In the method: through using some word lines and bit line a plurality of storage unit are arranged in matrix, step (B) is carried out line by line.
In the method: said capacitor is a coupling condenser.
Description of drawings
Through following preferred embodiment description taken together with the accompanying drawings, above-mentioned and other purpose of the present invention and characteristic will become more apparent, wherein:
Fig. 1 is the cross-sectional view of the unit cell of the non-volatile DRAM (NVDRAM) according to known techniques;
Fig. 2 A is the cross-sectional view according to the unit cell of the NVDRAM of the embodiment of the invention;
Fig. 2 B is the circuit diagram of the unit cell of the NVDRAM shown in Fig. 2 A;
Fig. 3 A is the cross-sectional view of the unit cell of NVDRAM according to another embodiment of the present invention;
Fig. 3 B is the circuit diagram of the unit cell of the NVDRAM shown in Fig. 3 A;
Fig. 4 is the block diagram of the memory bank (bank) of NVDRAM according to another embodiment of the present invention;
Fig. 5 is for have the block diagram of the NVDRAM of backup of memory matrix according to another embodiment of the present invention;
Fig. 6 is the cross-sectional view of the normalization pattern of the NVDRAM device shown in Fig. 3 A;
Fig. 7 is the threshold voltage figure of the floating grid of the NVDRAM device shown in Fig. 3 A when the normalization pattern;
Fig. 8 is the cross-sectional view of the unit cell bias condition of the NVDRAM device shown in Fig. 3 A when the normalization pattern;
Fig. 9 is the cross-sectional view of the unit bias condition of the NVDRAM device shown in Fig. 3 A when the normalization pattern;
Figure 10 is the normalization pattern list diagrammatic sketch of the NVDRAM device shown in Fig. 3 A; And
Figure 11 is the threshold voltage figure of the NVDRAM device shown in Fig. 3 A when program schema.
Embodiment
Below, will specify non-volatile DRAM (NVDRAM) with reference to accompanying drawing.
Fig. 2 A is the cross-sectional view according to the unit cell of the NVDRAM of the embodiment of the invention.Fig. 2 B is the circuit diagram of the unit cell of the NVDRAM shown in Fig. 2 A.
Shown in Fig. 2 A, the DRAM unit generally includes floating transistor and capacitor 207.But the unit cell of NVDRAM also is included in the control grid 201 of grid 202 tops of floating transistor.Below, the grid of floating transistor abbreviates floating grid as.
In the present invention, floating grid 202 is an individual layer.In addition, the printed line of capacitor 207 is supplied with plate line voltage V
Cp, but not ground voltage.As a result, the size of unit cell can reduce.In addition, the manufacturing approach of unit cell and technology also can be simplified.Moreover, because capacitor 207 is supplied with controllable plate line voltage, so NVDRAM can be through operating at the word line that is connected to unit cell and quite low voltage of bit line input.In other words, NVDRAM of the present invention can reduce power consumption.
At this, with reference to figure 2A, control grid 201 and floating grid 202 are processed by polysilicon; And insulation course is between control grid 201 and floating grid 202.
Fig. 3 A is the cross-sectional view of the unit cell of NVDRAM according to another embodiment of the present invention.Fig. 3 B is the circuit diagram of the unit cell of the NVDRAM shown in Fig. 3 A.
With reference to figure 3A, floating grid 303 is processed by nitride layer.In other words, unit cell has silicon-oxide-nitride--oxide-silicon (SONOS) structure 301 to 305.But,, then do not need first oxide insulating layer 302 if control grid 301 is made of metal.Therefore, unit cell can have metal-nitride-oxide-silicon (MNOS) structure.
Fig. 4 is the block diagram of the memory bank of NVDRAM according to another embodiment of the present invention.
Wherein a part comprises mode controller 401, internal voltage generator 402, bit-line pre-charge voltage switch module 403, word-line decoder 404, plate line voltage switch module 405, unit module 406, word line voltage switch module 407, bit line decoder 408, sensing amplifier 409 and data input/output (i/o) buffer 410.
At this, omit general module, the i.e. detailed description of the operational module in general DRAM.For example, bit line decoder 404 and the word-line decoder 408 in general DRAM, used always.Therefore, omit the explanation of bit line decoder 404, data input/output (i/o) buffer 410, sensing amplifier 409, unit module 406 and word-line decoder 408.But the constituent parts unit in unit module 406 all is a non-volatile memory cells, as is shown in the unit cell of Fig. 2 A or Fig. 3 A.
In memory bank; Be used for driving the circuit that non-volatile DRAM (NVDRAM) comprises a plurality of storage unit modules of a plurality of unit cells, comprise: be used to receive external voltage and produce a plurality of internal voltage generators 402 with builtin voltage of variant level; One of them that is used for a plurality of builtin voltages is fed to the switch module of word line, bit line and capacitor printed line; And be used for the mode controller 401 of CS module.Wherein, switch module comprises: one of them that is used for a plurality of builtin voltages is fed to the word line voltage switch module 407 of word line; One of them that is used for a plurality of builtin voltages is fed to the bit-line pre-charge voltage switch module 403 of bit line; And be used for a plurality of builtin voltages one of them be fed to the plate line voltage switch module 405 of capacitor printed line.
Below, specify the operation of the NVDRAM that comprises a plurality of unit cells with floating grid of processing by polysilicon.When NVDRAM comprised a plurality of unit with SONOS or MNOR structure, the present invention did not exist together description operation.
If external voltage is isolated, then NVDRAM remains on data in each unit; Otherwise if the supply external voltage is arranged, then NVDRAM operates as volatibility DRAM.Therefore, in NVDRAM of the present invention, operator scheme comprises 4 kinds of patterns: callback mode, normalization pattern, DRAM pattern and program schema.
In callback mode, as supply during external voltage,, check whether the threshold voltage that each storage unit is used for turn-on transistor is first threshold voltage V for the data that will be stored in the floating grid 303 are sent to capacitor Cap
HthOr the second threshold voltage V
LthWherein, first threshold voltage V
HthThe expression floating grid has electronics, i.e. the stored logic low-level data; And the second threshold voltage V
LthThe expression floating grid has no electronics, i.e. the stored logic high level data.In other words, first threshold voltage V
Hth,, be higher than the second threshold voltage V like 1V
Lth, like 0V.
Especially, shown in Fig. 4 A, to each transistorized grid supply higher voltage in all storage unit, like 4V, with turn-on transistor.Then, all supply supply voltage V to all bit lines
DD, the result, the logic high data are written among all storage unit.In other words, the logic high data are stored among the capacitor Cap of all storage unit.
Afterwards, supply the second threshold voltage V to each transistorized grid
LthThen, have through the second threshold voltage V at some
LthIn the transistorized storage unit of conducting, capacitor Cap is discharged.But, in other storage unit, promptly have not through the second threshold voltage V
LthIn transistorized each storage unit of conducting, capacitor Cap is discharge not.
That is, if the transistorized threshold voltage in the storage unit is higher than the second threshold voltage V
Lth, the capacitor Cap stored logic high level data in same memory cell then.Otherwise, capacitor Cap stored logic low-level data.
As stated, after carrying out callback mode, the oppisite phase data of capacitor Cap storage raw data.Therefore, the oppisite phase data that is stored among the capacitor Cap should revert to raw data.In the present invention, the normalization pattern comprises the step that oppisite phase data is reverted to raw data.
On the other hand, in another example of callback mode, data just can be stored among the capacitor Cap without data-switching.
At first, the word line voltage of selecting a word line that its supply is derived by following equation 1.
V
W1=V
B1p+ (V
Hth+ V
Lth)/2 [equation 1]
Wherein, " V
B1p" be the bit-line pre-charge voltage of NVDRAM device when operating as volatibility DRAM." V
Hth" when operating in program schema, have the first threshold voltage of the storage unit of logic-low data for NVDRAM, and " V
Lth" be the NVDRAM device operation when program schema, have second target threshold voltage of the unit of logic-low data.In addition, the negative voltage predetermined to other word line supply except selecteed word line is with the drain voltage between protective condenser Cap and the bit line.
Afterwards, in all word lines of unit module, carry out above-mentioned process in regular turn.As a result, through the first and second threshold voltage V
HthAnd V
LthBetween electric potential difference, each capacitor Cap can stored logic high level data or logic-low data.The data that are stored among the capacitor Cap are defined as following equation 2.
V
W1=V
B1p± (V
Hth-V
Lth)/2 [equation 2]
Wherein, above-mentioned symbolic representation is same as equation 1.
Secondly, through supply is higher than the voltage of logic high data voltage to word line, refresh all storage unit.Then, with normal data, the data of promptly not changing are stored among the capacitor Cap.
Fig. 6 is the cross-sectional view of the normalization pattern of the NVDRAM device shown in Fig. 3 A.
After accomplishing callback mode, because data storage is among floating grid 303, so the transistorized threshold voltage in each storage unit is all inequality.This is based on data because of transistorized threshold voltage,, is stored in logic high data or logic-low data in the floating grid of storage unit that is.Wherein, the normalization pattern is used for the transistorized threshold voltage of all storage unit is made as first threshold voltage V
Hth
In first step, elder generation is the data of back-up storage in each capacitor Cap of all storage unit respectively.
In second step, as shown in Figure 6, to all word lines, that is, the transistorized grid in all storage unit is all supplied the voltage of about 5V; The voltage of all supplying pact-3V to the bit line and the body of all storage unit.The electronics that then, will be positioned at second insulation course, 304 belows moves on to floating grid 303.Therefore, each storage unit all has the first threshold of being higher than voltage V
Hth, be used for the threshold voltage (being shown in Fig. 7) of turn-on transistor.
Fig. 7 is the threshold voltage figure of the floating grid of the NVDRAM device shown in Fig. 3 A when the normalization pattern.Particularly, Fig. 7 is the 3rd threshold voltage figure of the floating grid in the storage unit.Shown in Fig. 7 (a), it is illustrated in supplies any electric charge threshold voltage before to floating grid.In addition, shown in the 7th (b) figure, it is illustrated in supplies any electric charge threshold voltage afterwards to floating grid.Scheme with reference to the 7th (a) figure and the 7th (b), each storage unit has and is higher than the first target threshold voltage V
Th-HThreshold voltage.
In third step, when to the voltage of the about 5V of transistorized grid supply, be connected to the logic high data in all bit lines of all storage unit through supply, the capacitor Cap of all storage unit is charged.Capacitor Cap is charged by the logic high data then.
On the other hand, at bit line supply voltage V
B1Be increased to after the logic high data voltage, capacitor can charge among the logic high data are write on all storage unit.
Fig. 8 and Fig. 9 are the cross-sectional view of the unit bias condition of the NVDRAM device shown in Fig. 3 A when the normalization pattern.
In the 4th step, the threshold voltage of each storage unit reduces to first threshold voltage V
Hth, i.e. 1V.Particularly, the 4th step comprises the following steps: that (a) removes the electronics in the floating grid of storage unit; (b) through supplying first threshold voltage V to the transistorized grid in the storage unit
Hth, capacitor Cap is discharged; Repeating step (a) and (b) is all discharged up to all capacitor Caps.
For example, with reference to figure 5C, to word line voltage supply first threshold voltage V
Hth, like 1.0V, and the voltage of the about 0V of pairs of bit line supply.Then, if the threshold voltage of storage unit is lower than first threshold voltage V
Hth, the capacitor Cap discharge of the then transistor turns of storage unit, and storage unit.But, if threshold voltage is higher than first threshold voltage V
Hth, capacitor Cap just can not discharge.
In the step (a) of the 5th step, with reference to figure 5D, to word line supply negative voltage, as-3V; The voltage of pairs of bit line supply 0V; Voltage to body (bulk) supply-3V; And the printed line of capacitor Cap is fed to about 2.5V from 0V approximately gradually.Wherein, capacitor Cap is a coupling condenser, that is, if capacitor does not have the voltage gap between discharge and capacitor both sides to keep fixing, then the voltage level in its a certain side is the voltage level of response opposite side.Then, the storage node voltage level of the storage unit of stored logic high level data is increased to about 5V, and the storage node voltage of the storage unit of stored logic low-level data keeps about 2.5V.Wherein, memory node Vn is between the capacitor Cap and transistor of storage unit.As a result, the electric potential difference between memory node and the control grid is about 8V.This electric potential difference is enough to be transmitted electronically to capacitor Cap with being stored in the floating grid 303.Then, threshold voltage reduces gradually, equals the first target threshold voltage V up to threshold voltage
Hth(being shown in Fig. 5 D).
Afterwards, to transistorized grid supply first threshold voltage V
Hth, i.e. 0V.If threshold voltage reduces to first threshold voltage V
Hth, then capacitor Cap discharge; Otherwise capacitor Cap just can not discharge.If capacitor Cap is discharge not, then transistorized grid will be supplied negative voltage, as-3V.Then, the electronics that is stored in the floating grid 303 moves on to capacitor Cap.In all storage unit, repeat above-mentioned process, discharge up to capacitor.
In addition, before transistorized grid supply negative voltage, because transistorized grid supply first threshold voltage V
HthSo all storage unit can be refreshed, to purify the storage data.
On the other hand, because the capacitance of capacitor Cap is not enough to be received from the electric charge of floating grid output, so will repeat this process.Wherein, in the present invention, repeat this process one-period be defined as oppress-refresh-check (SRC) process.
Figure 10 is the normalization pattern list diagrammatic sketch of the NVDRAM shown in Fig. 3 A.
In the SRC process, be stored in storage unit three threshold voltage of the 4th step, because electric charge is not removed in the 5th step, so can be in order to avoid be lower than target threshold voltage from the logic-low data of logic high data-switching.This operation is defined as the threshold voltage clamp.
At last, (not shown) in the 8th step recovers to get into original unit with Backup Data.Wherein, through the callback mode data converted, when data have back up or restore, can be through using the phase inverter reduction.
On the other hand, in having the NVDRAM device of SONOS structure, electric charge is not in whole nitride layer 303, to collect, but is collecting near the nitride layer 303 of source electrode 308 and drain electrode 307 these two sides.Wherein, should be able to discharge at the electric charge of collecting near the nitride layer 303 of source electrode 308 these sides.Therefore, second and third step between, the voltage of word line supply pact-3V, bit line is then supplied the voltage of about 5V.
In normal DRAM pattern, the NVDRAM device is operated as volatibility DRAM.Therefore, omit the operation instructions of normal DRAM pattern.
Figure 11 is the threshold voltage figure of the NVDRAM device shown in Fig. 3 A when program schema.
If external voltage is unsettled or isolates, then carry out the program schema that is used for the data that are stored in capacitor Cap are sent to floating grid.
In first step, refresh a plurality of storage unit, be used for purifying the storage data.
In second step, in the storage unit of stored logic high level data, threshold voltage is clamped at the second threshold voltage V
LthBased on this step, supply the second threshold voltage V to word line
Lth, 0V according to appointment, and pairs of bit line is supplied the voltage of about 0V at the fixed time.
Afterwards, in third step, response is stored in the data in a plurality of storage unit, through the electric charge of selectivity discharge in each floating grid of a plurality of storage unit, reduces threshold voltage.As shown in Figure 9, to the voltage of word line supply pact-3V, and the printed line of capacitor is increased to about 2.5V from about 0V.As a result, the storage node voltage of the storage unit of stored logic high level is about 5V; And the storage node voltage of the low level storage unit of stored logic is about 2.5V.Then, with reference to Figure 11, in a storage unit of stored logic high level data, the electric charge of in floating grid, collecting is discharged into capacitor Cap, and therefore, threshold voltage reduces.
At last, repeat second and third step in regular turn, up to all storage unit stored logic low-level data all.The SRC of this step and normalization pattern is similar.Shown in figure 11, after program schema, the threshold voltage of some storage unit of stored logic high level data is changed into the second threshold voltage V at the NVDRAM device operation
Lth, the threshold voltage of other storage unit of stored logic low-level data does not then change.
Therefore, according to above-mentioned most preferred embodiment,, can control the NVDRAM device through supplying various voltage to the printed line of the word line in the storage unit, bit line and capacitor.Especially,, the printed line of capacitor supplies various voltage, so the NVDRAM device can be through a quite low builtin voltage operation because can responding the operator scheme of NVDRAM device.As a result, the NVDRAM device can reduce power consumption significantly.
Though invention has been described in conjunction with preferred embodiment, it is obvious that, and those skilled in the art can make variations and modifications under the situation that does not break away from the defined spirit and scope of the invention of following claim.
Claims (11)
1. one kind is used for driving the circuit that non-volatile DRAM (NVDRAM) comprises a plurality of storage unit modules of a plurality of unit cells, comprising:
Be used to receive external voltage and the internal voltage generator that produces a plurality of builtin voltages with variant level;
One of them that is used for a plurality of builtin voltages is fed to the switchgear of word line, bit line and capacitor printed line; And
The mode controller that is used for the CS device,
Wherein, said mode controller is controlled said switchgear, operates under the normalization pattern through the threshold voltage of adjusting floating grid in the said unit cell.
2. circuit as claimed in claim 1, it is characterized in that: switchgear comprises:
One of them that is used for a plurality of builtin voltages is fed to the word line voltage switch module of word line;
One of them that is used for a plurality of builtin voltages is fed to the bit-line pre-charge voltage switch module of bit line; And
One of them that is used for a plurality of builtin voltages is fed to the plate line voltage switch module of capacitor printed line.
3. circuit as claimed in claim 1 is characterized in that: the scope of a plurality of builtin voltages from pact-3V to pact+5V.
4. circuit as claimed in claim 1; It is characterized in that: mode controller CS device; When supply during external voltage, operate under the callback mode, the data that promptly are stored in the floating grid of unit cell are stored in the capacitor of same units unit again.
5. circuit as claimed in claim 4; It is characterized in that: mode controller CS device after isolating exterior voltage, exhausts before the external voltage; Operate under the program schema, the data that promptly are stored in the capacitor of unit cell are loaded in the floating grid of same units unit.
6. circuit as claimed in claim 1 also comprises:
Be used for the redundant memory cell module of back-up storage in the data of constituent parts unit.
7. circuit as claimed in claim 6 is characterized in that: the size of Backup Data is based on the size of redundant memory cell module.
8. circuit as claimed in claim 7 is characterized in that: the size of redundant memory cell module and each storage unit module big or small identical.
9. circuit as claimed in claim 1 is characterized in that: said unit cell has floating grid, when isolating exterior voltage, is used to store data.
10. circuit as claimed in claim 1 is characterized in that: said unit cell has silicon-oxide-nitride--oxide-silicon (SONOS) structure.
11. circuit as claimed in claim 1 is characterized in that: said unit cell has metal-nitride-oxide-silicon (MNOS) structure.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR20030058300 | 2003-08-22 | ||
| KR10-2003-0058300 | 2003-08-22 | ||
| KR1020030058300 | 2003-08-22 | ||
| KR1020030064354A KR100543938B1 (en) | 2003-08-22 | 2003-09-17 | Driving circuit for non volatile dynamic random access menory and its method |
| KR1020030064354 | 2003-09-17 | ||
| KR10-2003-0064354 | 2003-09-17 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB200410058544XA Division CN100481260C (en) | 2003-08-22 | 2004-08-18 | Method for driving non-volatile DRAM, and unit cell therein |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101494084A CN101494084A (en) | 2009-07-29 |
| CN101494084B true CN101494084B (en) | 2012-10-31 |
Family
ID=37229445
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009101281143A Expired - Fee Related CN101494084B (en) | 2003-08-22 | 2004-08-18 | Non-volatile dynamic random access memory |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP5102812B2 (en) |
| KR (1) | KR100543938B1 (en) |
| CN (1) | CN101494084B (en) |
| TW (1) | TWI296153B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100988812B1 (en) * | 2008-04-10 | 2010-10-20 | 주식회사 하이닉스반도체 | Semiconductor Device Equipped With Comprising Solid Transistor In Peri Area |
| CN102201411B (en) * | 2010-03-25 | 2013-04-03 | 上海丽恒光微电子科技有限公司 | Moire nonvolatile flash storage unit, storage device and manufacturing method thereof |
| US8441850B2 (en) * | 2010-10-08 | 2013-05-14 | Qualcomm Incorporated | Magnetic random access memory (MRAM) layout with uniform pattern |
| KR101987934B1 (en) * | 2012-12-07 | 2019-06-13 | 에스케이하이닉스 주식회사 | Semiconductor device including current compensator |
| KR102002942B1 (en) * | 2013-04-18 | 2019-07-24 | 에스케이하이닉스 주식회사 | Nonvolatile memory device and method of fabricating the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1169204A (en) * | 1994-10-19 | 1997-12-31 | 英特尔公司 | Voltage supplies for flash memory |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5331188A (en) * | 1992-02-25 | 1994-07-19 | International Business Machines Corporation | Non-volatile DRAM cell |
| JP3299900B2 (en) * | 1996-12-27 | 2002-07-08 | シャープ株式会社 | Nonvolatile memory and method of operating the same |
-
2003
- 2003-09-17 KR KR1020030064354A patent/KR100543938B1/en not_active IP Right Cessation
- 2003-12-29 TW TW092137307A patent/TWI296153B/en not_active IP Right Cessation
-
2004
- 2004-08-18 CN CN2009101281143A patent/CN101494084B/en not_active Expired - Fee Related
-
2009
- 2009-06-30 JP JP2009155007A patent/JP5102812B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1169204A (en) * | 1994-10-19 | 1997-12-31 | 英特尔公司 | Voltage supplies for flash memory |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI296153B (en) | 2008-04-21 |
| KR100543938B1 (en) | 2006-01-23 |
| JP2009217932A (en) | 2009-09-24 |
| KR20050020546A (en) | 2005-03-04 |
| CN101494084A (en) | 2009-07-29 |
| JP5102812B2 (en) | 2012-12-19 |
| TW200509375A (en) | 2005-03-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100481260C (en) | Method for driving non-volatile DRAM, and unit cell therein | |
| US7339847B2 (en) | BLEQ driving circuit in semiconductor memory device | |
| US7042276B2 (en) | Charge pump with improved regulation | |
| EP0938096B1 (en) | Ferroelectric memory device | |
| US9214465B2 (en) | Structures and operational methods of non-volatile dynamic random access memory devices | |
| US20070247891A1 (en) | Over-driven access method and device for ferroelectric memory | |
| JPH08221980A (en) | Bias voltage generation circuit | |
| US5886942A (en) | Word line driver and semiconductor device | |
| US6845051B2 (en) | Semiconductor memory device and data access method for semiconductor memory device | |
| CN100524520C (en) | Non-volatile dynamic random access memory and operation method thereof | |
| US7359271B2 (en) | Gate induced drain leakage current reduction by voltage regulation of master wordline | |
| US7054201B2 (en) | Driving circuit for non-volatile DRAM | |
| US6888767B1 (en) | Dual power sensing scheme for a memory device | |
| CN101494084B (en) | Non-volatile dynamic random access memory | |
| US6738292B2 (en) | Nonvolatile semiconductor storage device | |
| KR950014256B1 (en) | Semiconductor memory device using low source voltage | |
| KR20080080562A (en) | Memory system for reducing current consumption and method thereof | |
| US7251153B2 (en) | Memory | |
| US6469952B1 (en) | Semiconductor memory device capable of reducing power supply voltage in a DRAM's word driver | |
| JPH08279285A (en) | Device and method for extending data holding time of semiconductor storage circuit | |
| JPH08249885A (en) | Dynamic semiconductor storage | |
| US20060077729A1 (en) | Low current consumption at low power DRAM operation | |
| JPS6129072B2 (en) | ||
| JP2006134401A (en) | Low power consumption storage apparatus | |
| JPS6129073B2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20121031 Termination date: 20140818 |
|
| EXPY | Termination of patent right or utility model |