CN101488478B

CN101488478B - Integrated method for protecting polycrystalline and substrate surface

Info

Publication number: CN101488478B
Application number: CN2008100327535A
Authority: CN
Inventors: 居建华; 魏莹璐; 何学缅
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2008-01-17
Filing date: 2008-01-17
Publication date: 2012-06-06
Anticipated expiration: 2028-01-17
Also published as: CN101488478A

Abstract

The invention provides an integration method for protecting polycrystal and substrate surfaces, comprising the following steps in sequence: 1. deposition of compensation spacer SIN; 2. etching of compensation spacer; 3. N/P MOS IO lightly doped drain; 4. NMOS core lightly doped drain; 5. PMOS core lightly doped drain (LDD); 6. deposition of oxide/nitride of the spacer; 7. etching of the spacer; 8. injection of N+ source electrode/drain electrode; 9. stripping of oxide and 10. injection of P+ source electrode/drain electrode. The integration method of the invention can protect the surface of polycrystalline membrane from LDD harm and lower probability of puncturing the polycrystalline membrane.

Description

Be used to protect the integrated approach of polycrystalline and substrate surface

Technical field

The present invention relates to a kind of semiconductor fabrication process, relate in particular to a kind of LDD (lightly doped drain, lightly doped drain) integrated approach that is used to protect polycrystalline and substrate surface.

Background technology

In field of semiconductor manufacture, along with the size of Primary Component is more and more littler, the polycrystalline grid in polycrystalline film deposition back through ion implantation doping (being also referred to as preparatory doping) is necessary for realization high speed MOS performance.But can run into a problem like this, promptly through ion implantation doping behind the polycrystalline grid polycrystalline film be easy to have weakness, as shown in Figure 1.In subsequent process, promptly comprise that IMP, PR ashing, wet method are peeled off, gate electrode film and substrate always directly contact with plasma by force in the LDD of the additional heat-treatment circulation.Along with the yardstick of polycrystalline thickness is tending towards diminishing, there is risk in strong plasma collapse meeting, and it may pass the grain boundary and puncture polycrystalline film and cause transistor leakage.

Summary of the invention

The object of the present invention is to provide a kind of integrated technique of protecting surface of polycrystalline membrane to avoid the probability of LDD infringement and reduction puncture polycrystalline film.

For this reason, the invention provides a kind of integrated approach that is used to protect polycrystalline and substrate surface, this integrated approach may further comprise the steps successively:

Step 1: deposition of compensation spacer SIN;

Step 2: compensation spacer etching;

Step 3: the slight doped-drain of N/P MOS IO;

Step 4: the slight doped-drain of NMOS core (LDD);

Step 5: the slight doped-drain of PMOS core (LDD);

Step 6: the oxide/nitride deposition of sept;

Step 7: spacer-etch;

Step 8: the N+ source/drain injects;

Step 9: oxide is peeled off; And

Step 10: the P+ source/drain injects.

According to an aspect of the present invention, in the step 9 of the above-mentioned integrated approach that is used for protecting polycrystalline and substrate surface, oxide is peeled off through the HF wet method and is removed.

According to a further aspect in the invention, at the above-mentioned integrated approach that is used for protecting polycrystalline and substrate surface, can also comprise the step of a compensation etching post cleaning between step 2 and the step 3.The step that can also comprise in addition, spacer-etch post cleaning between step 7 and the step 8.

According to another aspect of the invention, at the above-mentioned integrated approach that is used for protecting polycrystalline and substrate surface, before the slight doped-drain of the N/P of above-mentioned steps three MOS IO, do not carry out the step that oxide is peeled off.

The invention has the advantages that:

1. this method can be avoided the polycrystalline film damage significantly and reduce owing to the ion that injects passes the high Ioff distributed points that polycrystalline film causes, and is as shown in Figure 1;

2. need not remove extra oxidation film, this method only changes original oxide immersion plating order;

3. this method is easy to control;

4. scalable NMOS energy and consumption, and to the not influence of performance of PMOS device.

Should be appreciated that the above generality of the present invention is described and following detailed description all is exemplary and illustrative, and be intended to further explanation is provided for as claimed in claim the present invention.

Description of drawings

Comprise that accompanying drawing is for providing the present invention further to be understood, they are included and are constituted the application's a part, and accompanying drawing shows embodiments of the invention, and play the effect of explaining the principle of the invention with this specification.

In the accompanying drawing:

Fig. 1 is the curve chart of the Ioff of sept film deposition to IDSAT;

Fig. 2 shows the processing step of prior art;

Fig. 3 shows the step according to technology of the present invention.

Embodiment

Now with embodiments of the present invention will be described by referring to the drawings in detail.

Below the contrast prior art is described processing step of the present invention in detail.

Fig. 2 shows the concrete steps of current technology.Wherein may further comprise the steps successively:

Step 201: deposition of compensation spacer SIN;

Step 202: compensation spacer etching;

Step 203: compensation etching post cleaning;

Step 204: oxide is peeled off;

The slight doped-drain of step 205:N/P MOS IO (LDD);

The slight doped-drain of step 206:NMOS core (LDD);

The slight doped-drain of step 207:PMOS core (LDD);

Step 208: the oxide/nitride deposition of sept;

Step 209: spacer-etch;

Step 210: spacer-etch post cleaning;

Step 211: oxide is peeled off; And

Step 212:N/P MOS source/drain injects.

With it accordingly, Fig. 3 shows the concrete steps according to technology of the present invention, wherein comprises successively:

Step 301: deposition of compensation spacer SIN;

Step 302: compensation spacer etching;

Step 303: compensation etching post cleaning;

The slight doped-drain of step 304:N/P MOS IO (LDD);

The slight doped-drain of step 305:NMOS core (LDD);

The slight doped-drain of step 306:PMOS core (LDD);

Step 307: the oxide/nitride deposition of sept;

Step 308: spacer-etch;

Step 309: spacer-etch post cleaning;

Step 310:N+ source/drain injects;

Step 311: oxide is peeled off; And

Step 312:P+ source/drain injects.

Be to have skipped the step that the oxide (OX) after the compensation spacer etch is peeled off according to above-mentioned steps main feature of the present invention, and kept reoxidizing of polycrystalline on polycrystalline and the substrate.Before PMOS core devices LDD IMP, remaining oxide (OX) is peeled off through the HF wet method and is removed.This polycrystalline of repairing the polycrystalline sidewall reoxidizes film can prevent the direct contact of (for example, PR coating, PR ashing, wet method are peeled off) in follow-up LDD cyclic process of polycrystalline and surface, and can prevent the infiltration of polycrystalline film.This method only changes flow sequence simply and can not accumulate side effect.Through regulating RTO or boiler tube technology controlling and process isolation layer thickness.The energy of needs optimization NMS LDD and consumption are to satisfy the requirement of device performance.The PMOS performance is unaffected.The control of remaining oxide (OX) is the key in the method for the present invention.

Those skilled in the art can be obvious, can carry out various modifications and modification and without departing from the spirit and scope of the present invention to above-mentioned exemplary embodiment of the present invention.Therefore, be intended to that the present invention is covered and drop in appended claims and the come scope thereof to modification of the present invention and modification.

Claims

1. an integrated approach that is used to protect polycrystalline and substrate surface is characterized in that, may further comprise the steps successively:

Step 1: compensation spacer SiN deposition;

Step 2: compensation spacer etching;

Step 3: doped-drain that N/P MOS IO place is slight is implanted;

Step 4: doped-drain that NMOS core place is slight is implanted;

Step 5: doped-drain that PMOS core place is slight is implanted;

Step 6: the oxide/nitride deposition of sept;

Step 7: spacer-etch;

Step 8: the N+ source/drain injects;

Step 9: the device that behind said N+ source/drain implantation step, forms is carried out oxide peel off; And

Step 10: the P+ source/drain injects,

Wherein, this method is not carried out the step that oxide is peeled off after the compensation spacer etching and before the slight doped-drain implantation in N/P MOS IO place,

Wherein, in the said step 9, the oxide that forms in the oxide/nitride deposition step of said sept is peeled off through the HF wet method and is removed.

2. the integrated approach that is used to protect polycrystalline and substrate surface as claimed in claim 1 is characterized in that,

The step that also comprises a compensation etching post cleaning between said step 2 and the step 3.

3. the integrated approach that is used to protect polycrystalline and substrate surface as claimed in claim 1 is characterized in that,

The step that also comprises spacer-etch post cleaning between said step 7 and the step 8.