CN101477978A - Semiconductor apparatus - Google Patents

Semiconductor apparatus Download PDF

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Publication number
CN101477978A
CN101477978A CN200810086241.7A CN200810086241A CN101477978A CN 101477978 A CN101477978 A CN 101477978A CN 200810086241 A CN200810086241 A CN 200810086241A CN 101477978 A CN101477978 A CN 101477978A
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dielectric layer
layer
dielectric
refractive index
semiconductor device
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CN101477978B (en
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蔡方文
王冠程
林耕竹
林志隆
郑双铭
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The invention discloses a semiconductor device, applied to dielectric film layer structure with ULK of the advanced interconnect, comprising an upper ELK dielectric layer and a lower ELK dielectric layer with different index of refraction. The index of refraction of the upper ELK dielectric layer is greater than that of the lower ELK dielectric layer. The invention provides a dielectric film layer with ULK applied to the advanced interconnect. The dielectric film layer with ULK includes bi-film layer with different index of refraction by detecting the wavelength of the same UV, to prevent UV from penetrating into lower film layer while roasting UV, in order to improve the UV roasting efficiency and save UV.

Description

Semiconductor device
Technical field
The present invention relates to a kind of formation of dielectric layer during making integrated circuit on the semiconductor wafer, particularly a kind of formation that is applicable to the ultralow dielectric dielectric film layer of advanced intraconnections.
Background technology
Along with semiconductor device density increases, resistance capacitance time delay (RC delay) is increased gradually for the influence of circuit performance.In order to reduce the RC late effect, and change conventional dielectric into low-k (low-k) dielectric material, its dielectric constant is lower than silicon dioxide (SiO 2) or 4, in case cross-talk (cross-talk) takes place and reduces the device electrical source consumption in stop bit between the metal of different layers position.Low dielectric constant dielectric materials also comprises a kind of ultralow dielectric (ELK) dielectric material, and its dielectric constant is lower than 2.5.One of existing ELK dielectric material is a porousness low-k material, its for inferior micron (sub-micron) technology or or even inner layer metal dielectric (the inter-metal dielectric of 65 nanometers (nm), 45 nanometers or following technology, IMD) (interlayer dielectric, ILD) layer is helpful especially for layer and internal layer dielectric.Porousness low-k dielectric material is by spin coating (spin-on) and chemical vapour deposition (CVD) (chemical vapor deposition, CVD) that form or by the formation of self assembly (self-assembly) technology, need after depositing operation, carry out one baking (curing) technology usually.Porousness low-k dielectric material can carry out ultraviolet light baking (UV curing) to replace heat baking or plasma treatment under short time or lower temperature, boiler tube baking (prior furnace curing) thereby reduce total heat budget before need not to carry out is kept simultaneously or is reduced dielectric constant.Yet during the UV baking, porousness low-k dielectric layer (that is, the SiCO rete of the hole agent (porogen) of having mixed) only absorbs about 40% UV light, and 60% UV light penetrates the below rete.This cause UV baking efficient to reduce and the longer stoving time of needs reach lower per hour wafer quantum of output (wafer per hour, WPH).The problem that UV penetrates also can reduce the tack (that is, the tack between etch stop layer and the copper interconnects) of below rete, and may need that (front-end of the line, FEOL) device carries out extra baking process to ELK dielectric layer and FEOL.
Therefore, be necessary that a kind of manufacturing technology of development is in order to form porousness low-k dielectric layer in ic manufacturing technology, it improves UV baking efficient and gets rid of the problem that UV penetrates.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of ultralow dielectric dielectric film layer that is applied to the inner layer metal dielectric layer of advanced intraconnections.The ultralow dielectric dielectric film layer is included in the two retes that have different refractivity under the identical UV optical wavelength measurement, penetrates into the below rete with UV light during preventing follow-up UV baking, and then the use that improves UV baking efficient and save UV light.
In one embodiment, the invention provides a kind of semiconductor device, comprise: semi-conductive substrate, be formed at one first dielectric layer on this Semiconductor substrate, dielectric constant is not more than 2.5, and being formed at one second dielectric layer between the Semiconductor substrate and first dielectric layer, dielectric constant is not more than 2.5.First dielectric layer has one first refractive index for the ultraviolet light under the set wavelength, and second dielectric layer has one second refractive index for the ultraviolet light under this set wavelength, and first refractive index is greater than second refractive index.
In another embodiment, the invention provides a kind of semiconductor device, comprising: have the semi-conductive substrate of a conduction region in being formed at, be formed at a etch stop layer on the Semiconductor substrate, be formed on the etch stop layer and dielectric constant be not more than 2.5 one the one ELK dielectric layer, be formed between etch stop layer and the ELK dielectric layer and dielectric constant be not more than 2.5 one the 2nd ELK dielectric layer and be formed at an ELK dielectric layer and the 2nd ELK dielectric layer in and be electrically connected to a dual-damascene structure of the interior conduction region of this Semiconductor substrate.The one ELK dielectric layer has one first refractive index for the ultraviolet light under the set wavelength, and the 2nd ELK dielectric layer has one second refractive index for the ultraviolet light under this set wavelength, and first refractive index is greater than second refractive index.
In another embodiment, the invention provides a kind of semiconductor device, comprising: have the semi-conductive substrate of a conduction region in being formed at, be formed at a etch stop layer on the Semiconductor substrate, be formed on the etch stop layer and dielectric constant is not more than an ELK dielectric layer of 2.5, is formed at the air gap between etch stop layer and the ELK dielectric layer and is formed at the ELK dielectric layer and air gap is interior and be electrically connected to a dual-damascene structure of conduction region.The refractive index of ELK dielectric layer is greater than 1.0.
In sum, the invention provides a kind of ultralow dielectric dielectric film layer that is applied to the inner layer metal dielectric layer of advanced intraconnections.The ultralow dielectric dielectric film layer is included in the two retes that have different refractivity under the identical UV optical wavelength measurement, penetrates into the below rete with UV light during preventing follow-up UV baking, and then the use that improves UV baking efficient and save UV light.
Description of drawings
Fig. 1 to Fig. 3 shows the integrated circuit of a kind of multilayer position semiconductor device and makes generalized section; And
Fig. 4 shows a kind of ELK dielectric film layer generalized section that is used for advanced intraconnections of another embodiment.
Wherein, description of reference numerals is as follows:
10～Semiconductor substrate
12～conduction region
14～etch stop layer
The ELK of 16～lower floor dielectric layer
18～upper strata ELK dielectric layer
20～ELK dielectric layer structure
22～reflector
24～dual-damascene structure
26～TEOS oxide layer 26
θ C～critical angle
Embodiment
The preferred embodiment of the invention provides a new ELK dielectric film layer structure, it is applicable to time micron technology (promptly, 65 nanometers, 45 nanometers, and 32 nanometers or following technology) last part technology (back-endof line, BEOL) or employed IMD layer of FEOL (FEOL) intraconnections or ILD layer.In this article, " ELK " means dielectric constant and is about 2.5 or be lower than below 2.5, and it comprises " porousness low-k " material, and it is about 2.0 or be lower than dielectric material below 2.0 for dielectric constant.The ELK dielectric film layer helps and has interconnection porous (interconnecting porous) structure and dielectric constant and be lower than 2.5 silica-based low-k dielectric material and together use.
Following conjunction with figs. explanation embodiments of the invention.Accompanying drawing and the corresponding identical mark of declaratives use.In the accompanying drawings, adopt exaggerative external form and thickness for clear and convenience.This paper explains special formation or device according to the present invention at parts.And the parts that do not illustrate or narrate can be by learning in the known technology.In addition, when a rete be positioned on another rete or be positioned at a substrate " on " time, mean to be located immediately on other rete or the substrate or therebetween and may have other rete.
Fig. 1 to Fig. 3 shows the integrated circuit of the multilayer position semiconductor device of an embodiment and makes generalized section.
Please refer to Fig. 1, in semi-conductive substrate 10, form a conduction region 12 by known microelectronic integrated circuit manufacturing technology.On Semiconductor substrate 10, form an etch stop layer 14 subsequently.Then, deposition one ELK dielectric layer structure 20 on etch stop layer 14, it comprises upper strata ELK dielectric layer 18 and the ELK of the lower floor dielectric layer 16 with different refractivity.The refractive index of one transparent material is a constant.In a material, therefore the refraction results difference under the different wavelength can produce different values for different optical wavelength." different refractivity " means for measure two refractive indexes under the UV of set wavelength light.
Semiconductor substrate 10 is to be used for the substrate that semiconductor integrated circuit is made, and in it and/or top is formed with integrated circuit." Semiconductor substrate " is defined as any structure that comprises semi-conducting material, for example have or do not have epitaxial loayer silicon substrate, contain the substrate that on the insulating barrier of flush type insulating barrier silicon (silicon-on-insulator) substrate is arranged or have germanium-silicon layer." integrated circuit " indication is the electronic circuit with multiple indivedual electronic components herein, for example transistor, diode, resistance, electric capacity, inductance, other active formula (active) or passive type (passive) device.Conduction region 12 is the conducting wiring of a part, has an exposing surface to carry out flatening process, for example cmp (chemical mechanical polishing).The conduction region material that is fit to comprises: copper, aluminium, copper alloy or other electric conducting material, but be not limited to this.The layer position of copper interconnects can be the ground floor of semiconductor device or belongs to any metal interconnecting layer position.The etch stop layer 14 that is used to control the terminating point of subsequent etch technology is deposited on above-mentioned Semiconductor substrate 10.For example, etch stop layer 14 (for example can be silicon nitride, SiN, Si3N4) or carborundum (for example, SiC) also by known CVD, low-pressure chemical vapor deposition (low pressure CVD, LPCVD), plasma enhanced chemical vapor deposition (plasmaenhanced CVD, PECVD) or high density plasma CVD (high densityplasma CVD HDPCVD) forms.
Refractive index (the n of upper strata ELK dielectric layer 18 1) be preferably refractive index (n greater than the ELK of lower floor dielectric layer 16 2).In one embodiment, for wavelength 600 to 700nm, and the ultraviolet light of preferred wavelength under 677nm, n 1Value more than or equal to 1.35.For example, upper strata ELK dielectric layer 18 is for having the silica-based low-k material layer of loose structure, can adopt the SiCO base membrane layer of the hole agent of having mixed, it is by using plasma CVD, PECVD for example, comprise: (remote plasma CVD RPCVD) or thermal chemical vapor deposition (thermal CVD), produces material (playing the hole agent) with the hole hole and is incorporated in the oxide of doping carbon and forms in distant formula chemical vapour deposition (CVD).The deposit thickness of upper strata ELK dielectric layer 18 is preferable at 50 to 2000 dusts
Figure A200810086241D00081
Scope, yet also can be other thickness.Under in the technical field those skilled in the art as can be known this thickness scope for the selection in the design and can along with the device critical size dwindle and the improvement of technology controlling and process reduces.
Refractive index (the n of the ELK of lower floor dielectric layer 16 2) be preferably refractive index (n less than upper strata ELK dielectric layer 18 1).In one embodiment, for wavelength 600 to 700nm, and the ultraviolet light of preferred wavelength under 677nm, n 2Value in 1.0 to 1.35 scope.For example, refractive index (n 2) the ELK of the lower floor dielectric layer 16 of scope 1.0 to 1.35 is for having the silica-based low-k material layer of loose structure, can adopt the SiCO base membrane layer, it is by using plasma CVD, and PECVD for example comprises: RPCVD or thermal chemical vapor deposition and form.The ELK of lower floor dielectric layer 16 can form by original position (in-situ) or displacement (ex-situ) deposition with upper strata ELK dielectric layer 18.In another embodiment, refractive index (n2) is that 1.0 the ELK of lower floor dielectric layer 16 can be an air gap (air gap) and forms by thermal decomposition.For example, deposit a heat decomposable polymer with as an expendable material, and carrying out the UV baking after implementing CMP being embedded in internal connection-wire structure in the ELK dielectric layer structure 20.Therefore, the ELK of lower floor dielectric layer 16 is to form with the displacement deposition with upper strata ELK dielectric layer 18.The preferable deposit thickness of the ELK of lower floor dielectric layer 16 is in the scope of 30 to 2500 dusts, yet also can be other thickness.Under in the technical field those skilled in the art as can be known this thickness scope for the selection in the design and can along with the device critical size dwindle and the improvement of technology controlling and process reduces.
When finishing the ELK dielectric layer structure 20 that comprises upper strata ELK dielectric layer 18 with different refractivity and the ELK of lower floor dielectric layer 16, in a reative cell, implement the UV baking.Please refer to Fig. 2, a reflector 22 is provided in reative cell, make UV light be done suitable reflection, and the adjustable angle of reflector 20 is whole, to obtain uniform irradiation.It is ear law (Snell ' s law) that the direction of passing the UV light reflection of upper strata ELK dielectric layer 18 depends mainly on department.Department is that the ear law is n 1Sin θ 1=n 2Sin θ 2, n wherein 1Be the refractive index of upper strata ELK dielectric layer 18, n 2Be the refractive index of the ELK of lower floor dielectric layer 16, θ 1Be the angle between the normal of UV light in the upper strata ELK dielectric layer 18 and refracting interface, θ 2Be the angle between the normal of UV light in the ELK of the lower floor dielectric layer 16 and refracting interface.If incident angle (that is θ, 1) more than or equal to a critical angle (that is θ, C), then UV light will produce total internal reflection in upper strata ELK dielectric layer 18.The generation of total internal reflection is according to θ C=sin -1(n 2/ n 1), n wherein 1N 2Therefore, in the present embodiment, make θ when adjusting reflector 22 1More than or equal to θ CThe time, UV light will can not enter the ELK of lower floor dielectric layer 16, but do internal reflection in upper strata ELK dielectric layer 18.Compared to single ELK dielectric layer structure traditionally, the double-deck ELK dielectric layer structure with different refractivity according to the present invention can prevent that UV light from passing the rete that is positioned at the below, and to save about 60% UV light, it helps to improve UV baking efficient.
In ELK dielectric layer structure 20, form a dual-damascene structure 24, as shown in Figure 3.(bottom anti-reflectance coating BARC) can be formed at ELK dielectric layer structure 20 tops to one layer or more hard mask/bottom layer anti-reflection layer, and it has a suitable thickness, in follow-up photoengraving pattern metallization processes reverberation is reduced to minimum.Then carry out photoetching and etch process forming a dual damascene opening, it can comprise groove opening on the dielectric layer opening and.One barrier layer is complied with and is deposited on dual damascene opening, and it comprises refractory metal, refractory metal nitride or silication refractory metal nitride layer.For example: tantalum (Ta), titanium (Ti), tungsten (W), tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), nitrogen tantalum silicide (TaSiN), nitrogen titanium silicide (TiSiN), and nitrogen tungsten silicide (WSiN).Implement copper deposition process in order to fill dual damascene opening, for example by depositing a copper seed layer to carry out electrochemical deposition (electro-chemical deposition, ECD), after carrying out the copper electrochemical deposition, implement CMP finishes dual-damascene structure 24 with hard mask/BARC layer of removing unnecessary copper layer, barrier layer and at least a portion making.
Though the present invention with the ELK dielectric layer structure 20 that is positioned at refractive index and is about 2.0 etch stop layer 14 tops as the example explanation, yet be understandable that it is n that ELK dielectric layer structure 20 of the present invention also can be positioned at a refractive index 3Dielectric layer top, n wherein 3Refractive index n greater than the ELK of lower floor dielectric layer 16 2Please refer to Fig. 4, during its integrated circuit that shows another embodiment was made, ELK dielectric layer structure 20 is positioned over a tetraethyl-metasilicate, and (tetraethyl orthosilicate, TEOS) oxide layer 26.The refractive index of TEOS oxide layer 26 is about 1.46.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art in the affiliated technical field; without departing from the spirit and scope of the present invention; when can doing to change and revise, so protection scope of the present invention is as the criterion when looking the scope that appending claims defines.

Claims (14)

1. semiconductor device comprises:
Semi-conductive substrate;
One first dielectric layer be formed on this Semiconductor substrate, and dielectric constant is not more than 2.5; And
One second dielectric layer be formed between this Semiconductor substrate and this first dielectric layer, and dielectric constant is not more than 2.5;
Wherein this first dielectric layer has one first refractive index for the ultraviolet light under the set wavelength, and this second dielectric layer has one second refractive index for the ultraviolet light under this set wavelength, and this first refractive index is greater than this second refractive index.
2. semiconductor device as claimed in claim 1, wherein this first refractive index is more than or equal to 1.35 for the ultraviolet light of wavelength under 600 to 700 nanometers.
3. semiconductor device as claimed in claim 1, wherein this second refractive index is 1.0 to 1.35 scope for the ultraviolet light of wavelength under 600 to 700 nanometers.
4. semiconductor device as claimed in claim 1, wherein this first dielectric layer is a porousness SiCO base dielectric material.
5. semiconductor device as claimed in claim 1, wherein this second dielectric layer is a porousness SiCO base dielectric material.
6. semiconductor device as claimed in claim 1 also comprises an etch stop layer, is arranged between this second dielectric layer and this Semiconductor substrate.
7. semiconductor device as claimed in claim 6 also comprises a tetraethyl-metasilicate oxide layer, is arranged between this second dielectric layer and this etch stop layer.
8. semiconductor device comprises:
Semi-conductive substrate comprises the conduction region in being formed at;
One etch stop layer is formed on this Semiconductor substrate;
One first dielectric layer be formed on this etch stop layer, and dielectric constant is not more than 2.5;
One second dielectric layer be formed between this etch stop layer and this first dielectric layer, and dielectric constant is not more than 2.5; And
One dual-damascene structure is formed in this first dielectric layer and this second dielectric layer, and is electrically connected to this conduction region in this Semiconductor substrate;
Wherein this first dielectric layer has one first refractive index for the ultraviolet light under the set wavelength, and this second dielectric layer has one second refractive index for the ultraviolet light under this set wavelength, and this first refractive index is greater than this second refractive index.
9. semiconductor device as claimed in claim 8, wherein this first dielectric layer is a porousness SiCO base dielectric material, and this first refractive index is more than or equal to 1.35 for the ultraviolet light of wavelength under 600 to 700 nanometers.
10. semiconductor device as claimed in claim 8, wherein this second dielectric layer is a porousness SiCO base dielectric material, and this second refractive index is 1.0 to 1.35 scope for the ultraviolet light of wavelength under 600 to 700 nanometers.
11. semiconductor device as claimed in claim 8 also comprises a tetraethyl-metasilicate oxide layer, is arranged between this second dielectric layer and this etch stop layer.
12. a semiconductor device comprises:
Semi-conductive substrate comprises the conduction region in being formed at;
One etch stop layer is formed on this Semiconductor substrate;
One dielectric layer be formed on this etch stop layer, and dielectric constant is not more than 2.5;
One air gap is formed between this etch stop layer and this dielectric layer; And
One dual-damascene structure is formed in this first dielectric layer and this air gap, and is electrically connected to this conduction region in this Semiconductor substrate;
Wherein the refractive index of this dielectric layer is greater than 1.0.
13. semiconductor device as claimed in claim 12, wherein this dielectric layer is a porousness SiCO base dielectric material, and its refractive index is more than or equal to 1.35 for the ultraviolet light of wavelength under 600 to 700 nanometers.
14. semiconductor device as claimed in claim 12 also comprises a tetraethyl-metasilicate oxide layer, is arranged between this air gap and this etch stop layer.
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