CN101471345B - Semiconductor device and photomask - Google Patents

Abstract

Shared contact holes SC1 and SC2 reach both gate electrode layers GE1 and GE2 and a drain region PIR. In a planar view, a sidewall E2 of gate electrode layers GE1 and GE2 is shifted toward a side of a sidewall E4 from a virtual extended line E1a of the sidewall E1. In a planar view, a center line (C2-C2) of a line width D1 in a portion that shared contact holes SC1 and SC2 of gate electrode layers GE1 and GE2 reach is located while shifted with respect to a center line (C1-C1) of a line width D2 in a portion located on channel formation regions CHN1 and CHN2 of gate electrode layers GE1 and GE2. Therefore, a semiconductor device such as an SRAM or TCAM and a photomask that can suppress an opening defect of the shared contact hole are obtained.

Description

Semiconductor device and photomask

Technical field

The present invention relates to semiconductor device and photomask, particularly have the semiconductor device of the shared contact hole (shared contact hole) that arrives grid electrode layer and this two side of extrinsic region and be used for the photomask of the composition of this grid electrode layer.

Background technology

The device of partly leading with the shared contact hole that arrives grid electrode layer and this two side of extrinsic region is for example openly put down in 9-321152 communique, the open 2004-273642 communique of Japanese patent application, the open 2004-273972 communique of Japanese patent application and the open 2004-327796 communique of Japanese patent application etc. open at Japanese patent application.

Shared contact hole has the cone shape section shape that darker opening diameter becomes more little from the open end position usually.Therefore, to being etched film and carrying out etching and form shared contact hole of insulating barrier etc. the time, carry out along with etched, the etching area that is etched film also diminishes.Because this is etched dwindling of area and causes etched carrying out to be hindered, the result is that shared contact hole can not arrive active layer (extrinsic region), the fault in the conducting of the bad grade of generation opening.

For example when the etching that is used to form shared contact hole, in the etching way, cause etching to be hindered owing to be positioned at the outstanding of sidewall spacer (sidewall spacer) of grid electrode layer sidewall.Therefore; In overlooking; When do not guarantee significantly from sidewall spacer end (etching when forming through shared contact hole does not have the end under the removed state) to the edge location of the long side direction of shared contact hole apart from the time; Liner on the oppose side wall dividing plate (liner) nitride film carries out in the etched operation residue taking place, and it is bad to produce opening.

Summary of the invention

The present invention just is being based on the problems referred to above and is accomplishing, and its purpose is to provide a kind of bad semiconductor device and photomask of opening that can suppress shared contact hole.

The semiconductor device of this execution mode possesses: Semiconductor substrate; Extrinsic region; Insulated-gate type field effect transistor; And insulating barrier.Semiconductor substrate has first type surface.Extrinsic region forms on this first type surface.Insulated-gate type field effect transistor forms on Semiconductor substrate.Insulating barrier forms on extrinsic region and insulated-gate type field effect transistor.Insulated-gate type field effect transistor comprises: a pair of regions and source that on first type surface, forms; And the grid electrode layer that on the channel formation region territory that this a pair of regions and source clips, forms via gate insulation layer.Insulating barrier has the shared contact hole that arrives grid electrode layer and this two side of extrinsic region.In overlooking, grid electrode layer has a side's toward each other sidewall and the opposing party's sidewall.In overlooking, a side's of the part that the shared contact hole of grid electrode layer arrives sidewall is compared with the imaginary extended line of a side's of part on the channel formation region territory that is positioned at grid electrode layer sidewall, is positioned on the position that sidewall one lateral deviation to the opposing party leaves.In overlooking, the center line of the line width of the part that the shared contact hole of grid electrode layer arrives, the center line with respect to the line width of the part on the channel formation region territory that is positioned at grid electrode layer is positioned on the position of departing from.

In this execution mode, be positioned on the position that center line departs from, the center line that refers to both sides is not located along the same line, and is the notion that comprises the parallel situation of both sides' center line and comprise the situation that both sides' center line intersects with inclining towards each other.

Semiconductor device according to this execution mode; In overlooking; One side's of the part that the shared contact hole of grid electrode layer arrives sidewall; Compare with the imaginary extended line of a side's of part on the channel formation region territory that is positioned at grid electrode layer sidewall, be positioned on the position that sidewall one lateral deviation to the opposing party leaves.Distance between one side's of the part that shared contact hole that therefore, can the enlarged gate electrode layer arrives the sidewall and the edge portion of shared contact hole.It is bad during etching in the time of thus, can being suppressed at shared contact hole and forming opening to take place.

Purpose, characteristic, aspect and advantage above-mentioned and that remove in addition of the present invention just can have been known through the detailed explanation of understanding relatively with accompanying drawing about below of the present invention.

Description of drawings

Fig. 1 is the equivalent circuit figure of the memory cell of SRAM.

Fig. 2 is the general view that is illustrated in the plane figure structure of the semiconductor device in the execution mode 1 of the present invention from following ground floor.

Fig. 3 is the general view that is illustrated in the plane figure structure of the semiconductor device in the execution mode 1 of the present invention from the following second layer.

Fig. 4 is illustrated in the plane figure structure of the semiconductor device in the execution mode 1 of the present invention from the 3rd layer following general view.

Fig. 5 is the summary section along the V-V line of Fig. 2～Fig. 4.

Fig. 6 is near the general view of shared contact hole that enlarges the semiconductor device of expression execution mode 1 of the present invention.

Fig. 7～Figure 15 is the skeleton diagram of manufacturing approach of representing the semiconductor device of execution mode 1 of the present invention with process sequence, is the figure that representes with the section corresponding with the section of Fig. 5.

Figure 16 is the plane graph of the structure of the photomask roughly representing to use in the manufacturing approach of semiconductor device of execution mode 1 of the present invention.

Figure 17 is that the part that enlarges the region R of expression Figure 16 enlarges plane graph.

Figure 18 is that expression hypothesis grid electrode layer linearity ground extends the general view of the structure in the absence of breach.

Figure 19 is used to explain the bad summary section of opening takes place when making the structure of Figure 18.

Figure 20 is used to explain the summary section that when making the semiconductor device of execution mode 1 of the present invention, can suppress the bad generation of opening.

Figure 21 is near the general view of shared contact hole that enlarges the semiconductor device of expression execution mode 2 of the present invention.

Figure 22 roughly representes to be used to make the semiconductor device of execution mode 2 of the present invention and the part of the structure of the photomask that uses enlarges plane graph.

Figure 23 is near the general view of shared contact hole that enlarges the semiconductor device of expression execution mode 3 of the present invention.

Figure 24 roughly representes to be used to make the semiconductor device of execution mode 3 of the present invention and the part of the structure of the photomask that uses enlarges plane graph.

Figure 25 is near the general view of shared contact hole that enlarges the semiconductor device of expression execution mode 4 of the present invention.

Figure 26 roughly representes to be used to make the semiconductor device of execution mode 4 of the present invention and the part of the structure of the photomask that uses enlarges plane graph.

Figure 27 is the general view of the structure of the expression MOS transistor during with the configuration of two row two row and shared contact hole with the SRAM memory cell shown in the execution mode 1.

Figure 28 is the general view of the structure of the expression MOS transistor during with the configuration of two row two row and shared contact hole with the SRAM memory cell shown in the execution mode 2.

Figure 29 is the general view of the structure of the expression MOS transistor during with the configuration of two row two row and shared contact hole with the SRAM memory cell shown in the execution mode 3.

Figure 30 is the general view of the structure of the expression MOS transistor during with the configuration of two row two row and shared contact hole with the SRAM memory cell shown in the execution mode 4.

Figure 31 is the circuit diagram of circuit structure of the TCAM unit of the structure of expression storage part with SRAM memory cell.

Figure 32 is the plane graph of plane figure of the TCAM unit of the expression structure of having used execution mode 1.

Figure 33 is the plane graph of representing the plane figure of Figure 32 from lower floor, is the plane graph of expression active region that electric ground has isolated through component isolation structure and the extrinsic region that in this active region, forms.

Figure 34 is a plane graph of representing the plane figure of Figure 32 from lower floor, is to be illustrated in the plane graph that has appended the structure of grid electrode layer in the plane figure of Figure 33.

Figure 35 is a plane graph of representing the plane figure of Figure 32 from lower floor, is the plane graph that is illustrated in the allocation position of the shared contact hole that forms on the interlayer insulating film of cover gate electrode layer etc. and common contact hole.

Figure 36 is a plane graph of representing the plane figure of Figure 32 from lower floor, is the plane graph that is illustrated in the pattern of the conductive layer that forms on the interlayer insulating film of Figure 35.

Figure 37 is the plane graph of plane figure on more upper strata of the plane figure of expression Figure 32, is the plane graph that is illustrated in the allocation position of the through hole that forms on the interlayer insulating film that covers conductive layer.

Figure 38 is the plane graph of plane figure on more upper strata of the plane figure of expression Figure 32, is the plane graph that is illustrated in the pattern of the conductive layer that forms on the interlayer insulating film of Figure 37.

Figure 39 is the plane graph of plane figure of the TCAM unit of the expression structure of having used execution mode 2.

Figure 40 is the plane graph of plane figure of the TCAM unit of the expression structure of having used execution mode 3.

Figure 41 is the plane graph of plane figure of the TCAM unit of the expression structure of having used execution mode 4.

Embodiment

Below, with reference to accompanying drawing execution mode of the present invention is described.

Execution mode 1

With reference to Fig. 1, SRAM is the semiconductor storage of volatibility, and the memory cell of this SRAM for example is the memory cell of whole CMOS (Complementary Metal Oxide Semiconductor) type.

In this SRAM, complementary type data wire (complementary data line) (bit line) BL of matrix (ranks) shape ground configuration ,/dispose memory cell on the cross part of BL and word line WL.This memory cell constitutes with circuits for triggering (flip flop circuit) and two access transistors (access transistor) AT1, the AT2 that a pair of negative circuit (inverter circuit) constitutes.Through these circuits for triggering, constituted cross-linked two memory node N1, N2, constituted the bistable state of (High, LOW) or (Low, High).As long as this memory cell is provided predetermined power voltage, just can continue to keep bistable state.

Each of a pair of access transistor AT1, AT2 for example comprises n channel MOS transistor (below, be called the nMOS transistor).One side of the source/drain of access transistor AT1 is electrically connected with memory node (storage node) N1, and the opposing party of source/drain is electrically connected with bit line/BL.In addition, a side of the source/drain of access transistor AT2 is electrically connected with memory node N2, and the opposing party of source/drain is electrically connected with bit line BL.In addition, each the grid of access transistor AT1, AT2 is electrically connected with word line WL.Through this word line WL control access transistor AT1, the conducting of AT2, nonconducting state.

Negative circuit constitutes with a driver transistor DT1 (or DT2) and a load transistor LT1 (or LT2).

Each of a pair of driver transistor DT1, DT2 for example is made up of the nMOS transistor.The source electrode of each of a pair of driver transistor DT1, DT2 is electrically connected with GND (earthing potential).In addition, the drain electrode of driver transistor DT1 is electrically connected with memory node N1, and the drain electrode of driver transistor DT2 is electrically connected with memory node N2.And then the grid of driver transistor DT1 is electrically connected with memory node N2, and the grid of driver transistor DT2 is electrically connected with memory node N1.

Each of a pair of load transistor LT1, LT2 for example is made up of p channel MOS transistor (below, be called the pMOS transistor).The source electrode of each of a pair of load transistor LT1, LT2 is electrically connected to the Vdd supply voltage.The drain electrode of load transistor LT1 is electrically connected to memory node N1 in addition, and the drain electrode of load transistor LT2 is electrically connected to memory node N2.In addition, the grid of load transistor LT1 is electrically connected with memory node N2, and the grid of load transistor LT2 is electrically connected with memory node N1.

When this memory cell is write data; Word line WL is selected and access transistor AT1, AT2 become conducting state; Through corresponding to desirable logical value to bit line to BL ,/BL applies voltage by the strong hand, thereby be set at circuits for triggering bistable any.In addition, from this memory cell sense data the time, make access transistor AT1, AT2 become conducting state, the current potential of memory node N1, N2 be communicated to bit line BL ,/BL.

In the structure of the semiconductor device of this execution mode; The drain region of the grid electrode layer of load transistor LT1 and load transistor LT2 is electrically connected through shared contact hole each other, and the drain region of the grid electrode layer of load transistor LT2 and load transistor LT1 is electrically connected through shared contact hole each other.Below, its structure is described.

With reference to Fig. 2 and Fig. 5, on the first type surface of Semiconductor substrate SB, for example be formed with the groove isolation construction that comprises STI (shallow Trench Isolation, shallow trench isolation leaves).This groove isolation construction has: the trench isolations in that the first type surface of Semiconductor substrate SB forms is used ditch TR; With the filler TI that constitutes by silica that fills in this ditch TR.

On first type surface, be formed with a plurality of SRAM memory cells through the segregate Semiconductor substrate SB of this groove isolation construction.In the SRAM memory cell area MC zone of dotted line (among the Fig. 2 with), be formed with a pair of driver transistor DT1, DT2, a pair of access transistor AT1, AT2 and a pair of load transistor LT1, LT2.

Each of a pair of driver transistor DT1, DT2 and a pair of access transistor AT1, AT2 for example is made up of the nMOS transistor, in p type well region (wellregion) PW1, the last formation of PW2 of the first type surface of Semiconductor substrate SB.In addition, each of a pair of load transistor LT1, LT2 for example is made up of the pMOS transistor, in the n type well region NW of the first type surface of Semiconductor substrate SB, forms.

Driver transistor DT1 has: a pair of n type extrinsic region NIR, the NIR that become a pair of regions and source; With grid electrode layer GE1.Be spaced from each other on the first type surface of each Semiconductor substrate SB in p type well region PW1 of a pair of n type extrinsic region NIR, NIR and form.Grid electrode layer GE1 clips gate insulator (not shown) and forms on the channel formation region territory that a pair of n type extrinsic region NIR, NIR clip.

Driver transistor DT2 has: a pair of n type extrinsic region NIR, the NIR that become a pair of regions and source; With grid electrode layer GE2.Be spaced from each other on the first type surface of each Semiconductor substrate SB in p type well region PW2 of a pair of n type extrinsic region NIR, NIR and form.Grid electrode layer GE2 clips gate insulator (not shown) and forms on the channel formation region territory that a pair of n type extrinsic region NIR, NIR clip.

Access transistor AT1 has: a pair of n type extrinsic region NIR, the NIR that become a pair of regions and source; With grid electrode layer GE3.Be spaced from each other on the first type surface of each Semiconductor substrate SB in p type well region PW1 of a pair of n type extrinsic region NIR, NIR and form.Grid electrode layer GE3 clips gate insulator (not shown) and forms on the channel formation region territory that a pair of n type extrinsic region NIR, NIR clip.

Access transistor AT2 has: a pair of n type extrinsic region NIR, the NIR that become a pair of regions and source; With grid electrode layer GE4.Be spaced from each other on the first type surface of each Semiconductor substrate SB in p type well region PW2 of a pair of n type extrinsic region NIR, NIR and form.Grid electrode layer GE4 clips gate insulator (not shown) and forms on the channel formation region territory that a pair of n type extrinsic region NIR, NIR clip.

Load transistor LT1 has: a pair of p type extrinsic region PIR, the PIR that become a pair of regions and source; With grid electrode layer GE1.Be spaced from each other on the first type surface of each Semiconductor substrate SB in n type well region NW of a pair of p type extrinsic region PIR, PIR and form.Grid electrode layer GE1 clips gate insulator GI and forms on the channel formation region territory CHN1 that a pair of p type extrinsic region PIR, PIR clip.

Load transistor LT2 has: a pair of p type extrinsic region PIR, the PIR that become a pair of regions and source; With grid electrode layer GE2.Be spaced from each other on the first type surface of each Semiconductor substrate SB in n type well region NW of a pair of p type extrinsic region PIR, PIR and form.Grid electrode layer GE2 clips gate insulator GI and forms on the channel formation region territory CHN2 that a pair of p type extrinsic region PIR, PIR clip.

One side of a pair of regions and source of the drain region of driver transistor DT1 and access transistor AT1 is formed by same n type extrinsic region NIR.In addition, a side of a pair of regions and source of the drain region of driver transistor DT2 and access transistor AT2 is formed by same n type extrinsic region NIR.

The grid electrode layer GE1 of driver transistor DT1 and the grid electrode layer GE1 of load transistor LT1 are formed by mutually the same conductive layer.The grid electrode layer GE2 of the grid electrode layer GE2 of driver transistor DT2 and load transistor LT2 is formed by mutually the same conductive layer in addition.

Mainly with reference to Fig. 5, form silicide layer (silicide layer) SCL with each grid electrode layer, the mode that regions and source is joined with these transistors DT1, DT2, AT1, AT2, LT1, LT2.In addition, stack gradually on Semiconductor substrate SB with each the mode of grid electrode layer, regions and source etc. that covers these transistors DT1, DT2, AT1, AT2, LT1, LT2 and be formed with liner nitride film (liner nitride film) LN and interlayer insulating film II1.Here, interlayer insulating film II1 for example is made up of silica.On liner nitride film LN and interlayer insulating film II1, be formed with a plurality of contact hole CH1～CH8 and a plurality of shared contact hole SC1, SC2.

Mainly with reference to Fig. 2, particularly, in liner nitride film LN and interlayer insulating film II1, be formed with each contact hole CH1, the CH2 of source region that arrives driver transistor DT1, DT2.Among this external liner nitride film LN and the interlayer insulating film II1, be formed with each a side's (drain region of each of driver transistor DT1, DT2) contact hole CH3, the CH4 of a pair of regions and source that arrives access transistor AT1, AT2.Among this external liner nitride film LN and the interlayer insulating film II1, be formed with each the opposing party's contact hole CH5, the CH6 of a pair of regions and source that arrives access transistor AT1, AT2.In addition, on liner nitride film LN and interlayer insulating film II1, be formed with each contact hole CH7, the CH8 of source region that arrives load transistor LT1, LT2.

In addition, in liner nitride film LN and interlayer insulating film II1, be formed with this two side's of drain region of the grid electrode layer GE1 that arrives load transistor LT1 and load transistor LT2 shared contact hole SC1.In addition, in liner nitride film LN and interlayer insulating film II1, be formed with this two side's of drain region of the grid electrode layer GE2 that arrives load transistor LT2 and load transistor LT1 shared contact hole SC2.

Mainly with reference to Fig. 5, in each the inside of above-mentioned a plurality of contact hole CH1～CH8 and shared contact hole SC1, SC2, be filled with conductive layer PL1 (Fig. 5).On interlayer insulating film II1, stack gradually and be formed with insulating barrier BL1 and interlayer insulating film II2.Here, insulating barrier BL1 for example is made up of silicon nitride, carborundum, silicon oxide carbide or carbonitride of silicium, and interlayer insulating film II2 for example is made up of silica.On this insulating barrier BL1 and interlayer insulating film II2, be formed with a plurality of through holes, imbed each of a plurality of conductive layers (the first metal layer) CL1 in each inside of a plurality of through holes.Constitute conductive layer pattern through these a plurality of conductive layer CL1.

Mainly with reference to Fig. 2, through this conductive layer CL1, thereby conductive layer PL1 in the shared contact hole SC1 and the conductive layer PL1 in the contact hole CH4 are electrically connected.A side of a pair of regions and source of the drain region of the drain region of the grid electrode layer GE1 of load transistor LT1, load transistor LT2, driver transistor DT2 and access transistor AT2 is electrically connected thus

In addition, through conductive layer CL1, conductive layer PL1 and the conductive layer PL1 in the contact hole CH3 in the shared contact hole SC2 are electrically connected.Thus, a side of a pair of regions and source of the drain region of the drain region of the grid electrode layer GE2 of load transistor LT2, load transistor LT1, driver transistor DT1 and access transistor AT1 is electrically connected.

Each the conductive layer PL1 of inside of contact hole CH1, CH2, CH5～CH8 also individually is electrically connected with conductive layer CL1 in addition.

Mainly with reference to Fig. 5, on interlayer insulating film II2, stack gradually and be formed with insulating barrier BL2 and interlayer insulating film II3.Here, insulating barrier BL2 for example is made up of silicon nitride, carborundum, silicon oxide carbide or carbonitride of silicium, and interlayer insulating film II3 for example is made up of silica.In this insulating barrier BL2 and interlayer insulating film II3, be formed with a plurality of through hole VH11～VH18, on the surface of interlayer insulating film II3, be formed with the ditch that conductive layer is imbedded usefulness with each mode that is communicated with a plurality of through holes (via hole) VH11～VH18.

In each of a plurality of through hole VH11～VH18, imbedded conductive layer PL2.These external a plurality of conductive layers are imbedded in each of ditch of usefulness, imbed each of a plurality of conductive layers (second metal level) CL2.Be formed with conductive layer pattern through these a plurality of conductive layer CL2.

Mainly with reference to Fig. 3, the conductive layer CL2 that is electrically connected with the opposing party of a pair of regions and source that reads transistor AT1 via through hole VH13 and contact hole CH5 is as bit line/BL performance function.In addition, the conductive layer CL2 that is electrically connected with the opposing party of a pair of regions and source of access transistor AT2 via through hole VH14 and contact hole CH6 is as bit line BL performance function.In addition, the conductive layer CL2 that is electrically connected with the source region of load transistor LT1 via through hole VH15 and contact hole CH7 and is electrically connected with the source region of load transistor LT2 via through hole VH16 and contact hole CH8 is as power line Vdd performance function.These bit lines BL ,/BL and power line Vdd extend with the parallel mode of longitudinal direction in figure.

The conductive layer PL2 of the inside of each of this accessibke porosity VH11, VH12, VH17, VH18 also individually is electrically connected with conductive layer CL2.

Mainly with reference to Fig. 5, on interlayer insulating film II3, stack gradually and be formed with insulating barrier BL3 and interlayer insulating film II4.Here, insulating barrier BL3 for example is made up of silicon nitride, carborundum, silicon oxide carbide or carbonitride of silicium, and interlayer insulating film II4 for example is made up of silica.In this insulating barrier BL3 and interlayer insulating film II4, be formed with a plurality of through hole VH21～VH24, on the surface of interlayer insulating film II4, to be formed with the ditch that conductive layer embeds usefulness with each mode that is communicated with of a plurality of through hole VH21～VH24.

In each of a plurality of through hole VH21～VH24, imbedded conductive layer (not shown).These external a plurality of conductive layers are imbedded in each of ditch of usefulness, imbed each of a plurality of conductive layers (the 3rd metal level) CL3.Be formed with conductive layer pattern through these a plurality of conductive layer CL3.

Mainly with reference to Fig. 4, the conductive layer CL3 that is electrically connected with the source region of driver transistor DT1 via through hole VH21, through hole VH11 and contact hole CH1 is as GND line performance function.The conductive layer CL3 that is electrically connected with the source region of driver transistor DT2 via through hole VH22, through hole VH12 and contact hole CH2 in addition, is as GND line performance function.In addition, the conductive layer CL3 that is electrically connected with the grid electrode layer GE3 of access transistor AT1 via through hole VH23, through hole VH17 and contact hole CH9 and is electrically connected with the grid electrode layer GE3 of access transistor AT2 via through hole VH24, through hole VH18 and contact hole CH10 is as word line WL performance function.These GND lines and word line W1 extend with the parallel mode of transverse direction in figure.

Then, near the structure the shared contact hole in the semiconductor device of this execution mode is at length explained.

With reference to Fig. 6, shared contact hole SC1 arrives the grid electrode layer GE1 of load transistor LT1 and drain region (p type extrinsic region) this two side of PIR of load transistor LT2.In addition, shared contact hole SC2 arrives the grid electrode layer GE2 of load transistor LT2 and drain region (p type extrinsic region) this two side of PIR of load transistor LT1.

In overlooking, grid electrode layer GE1 has sidewall E1, E2 and the opposing party's of a side toward each other sidewall E3, E4.In overlooking; One side's of the part that the shared contact hole SC1 of the GE1 of grid electrode layer arrives sidewall E2; Compare with the imaginary extended line of a side's of part on the channel formation region territory CHN1 of the load transistor LT1 that is positioned at grid electrode layer GE1 sidewall E1, be positioned on sidewall E3 to the opposing party, the position that E4 one lateral deviation leaves.In this external overlooking; The center line (C2-C2 line) of the line width D1 of the part that the shared contact hole of grid electrode layer GE1 arrives; Center line (C1-C1 line) with respect to the line width D2 of the part on the above-mentioned channel formation region territory CHN1 that is positioned at grid electrode layer GE1 is positioned on the position that the opposing party's sidewall E4 one lateral deviation leaves.Therefore, line width D1 becomes shorter than line width D2.In addition, line width D1 and line width D2 define with the line width with a sidewall E1 of a side and a side's sidewall E3 vertical direction.

With respect to the position deviation of the side's of the imaginary extended line E1a of an above-mentioned side's sidewall E1 sidewall E2, be to be provided with breach on the part that arrives through shared contact hole SC1 to produce at grid electrode layer GE1.That is to say; In overlooking; The part that the shared contact hole SC1 of grid electrode layer GE1 arrives has following breach, i.e. the breach of a side's of this part the sidewall E2 mode of moving back to the opposing party's sidewall E3 one rear flank with respect to the imaginary extended line E1a of a side sidewall E1.

In addition, a sidewall E2 of a side and a side's sidewall E1 is parallel in fact.In addition, the opposing party's of the part of the channel formation region territory CHN1 of the opposing party's of the part of the shared contact hole SC1 arrival of grid electrode layer GE1 sidewall E4 and grid electrode layer GE1 sidewall E3 is located along the same line in fact.In addition, in overlooking, (the p type extrinsic region) end of PIR, drain region of preferred load transistor LT2 and the beeline L of a side sidewall E2 are more than the 5nm.

In addition, grid electrode layer GE2 also has the structure same with grid electrode layer GE1.

Then, the manufacturing approach to the semiconductor manufacturing of this execution mode describes.

With reference to Fig. 7, on Semiconductor substrate SB, form p type trap PW1, PW2, n type trap NW.Form trench isolations on the first type surface of this external Semiconductor substrate SB and use ditch TR,, form the groove isolation construction that constitutes by STI through in this ditch TR, imbedding the filler TI that silica constitutes.

With reference to Fig. 8, formation gate insulator GI and gate electrode are used conductive layer GE on the first type surface of Semiconductor substrate SB.For example apply the photoresist PR of eurymeric on conductive layer GE at this gate electrode.

The pattern of photomask PM is exposed to this photoresist PR.This photomask PM has: the substrate TS that sees through the light of exposure; Cover light-shielding pattern (for example the being the chromium film) LS of the light transmission of exposure with being used to of on this substrate TS, forming.After this exposure, development photoresist PR.

With reference to Fig. 9, through above-mentioned development, the zone of the photoresist PR of the light of illuminated exposure is removed, and photoresist PR is patterned.Pattern with this photoresist PR is a mask, and gate electrode is applied etching with conductive layer GE.Thus, gate electrode is patterned with conductive layer, forms grid electrode layer GE1～GE4.Afterwards, remove the pattern of photoresist PR through ashing (ashing) etc.

With reference to Figure 10,, on the first type surface of Semiconductor substrate SB, form the low concentration region of regions and source through grid electrode layer GE1～GE4 etc. is carried out ion injection etc. as mask to impurity.At this moment, inject n type impurity and p type impurity respectively, form the low concentration region of n type and the low concentration region PIRL of p type.

With reference to Figure 11, form the insulating barrier that sidewall spacer is used with the last mode of cover gate electrode layer GE1～GE4.As the material of this insulating barrier, only use silica, or the formation silicon nitride also can after forming silica.Afterwards, implement whole deep etch and expose up to the first type surface of Semiconductor substrate SB, the insulating barrier that remaining sidewall spacer is used on each sidewall of grid electrode layer GE1～GE4 forms sidewall spacer SW.

Through this sidewall spacer SW and grid electrode layer GE1～GE4 etc. is carried out ion injection etc. as mask to impurity, on the first type surface of Semiconductor substrate SB, form the area with high mercury of regions and source.At this moment, inject n type impurity and p type impurity respectively, form the area with high mercury of n type and the area with high mercury PIRH of p type.

Like this, through n type low concentration region and area with high mercury, form the regions and source of n type with LDD (Lightly Doped Drain, lightly doped drain) structure.In addition, through p type low concentration region PIRL and area with high mercury PIRH, form the regions and source PIR of p type with LDD structure.

With reference to Figure 12, on whole of the first type surface of Semiconductor substrate SB, form high melting point metal layer, through applying heat treatment, form silicide layer SCL on the first type surface of and Semiconductor substrate SB last at grid electrode layer GE1～GE4.Afterwards, remove the part of the high melting point metal layer that does not become silicide.Here, the material of the refractory metal two or more material that can use Ni, Co, Pt, Pd, Hf, V, Er, Ir, Yb or therefrom select.

With reference to Figure 13,, on the first type surface of Semiconductor substrate SB, stack gradually the interlayer insulating film II1 that forms liner nitride film LN and constitute by silica with the mode of cover gate electrode layer GE1～GE4, sidewall spacer SW etc.

With reference to Figure 14, on liner nitride film LN and interlayer insulating film II1, use photomechanical process technology and etching technique to form shared contact hole SC1, SC2, contact hole CH1～CH10 etc.

Here, shared contact hole SC1 is with this two side's of drain region PIR of the grid electrode layer GE1 that arrives load transistor LT1 and load transistor LT2 mode (this two side's surface is exposed) formation.In addition, shared contact hole SC2 is with this two side's of drain region PIR of the grid electrode layer GE2 that arrives load transistor LT2 and load transistor LT1 mode (this two side's surface is exposed) formation.

With reference to Figure 15,, for example on interlayer insulating film II1, form the conductive layer that tungsten (W) constitutes through CVD (Chemical Vapor Deposition, chemical vapour deposition (CVD)) method with the mode that shared contact hole SC1, SC2, contact hole CH1～CH10 etc. are imbedded.Afterwards, conductive layer being carried out deep etch exposes up to the surface of interlayer insulating film II1.Thus, imbed shared contact hole SC1, SC2, contact hole CH1～CH10, form conductive layer PL1 as the contact plunger layer.

Afterwards, the semiconductor device of this execution mode shown in Figure 5 is made in the formation of the formation of insulating barrier and conductive layer repeatedly.

Then, the structure to the described photomask of Fig. 8 describes.

Mainly with reference to Figure 16, the eurymeric photoresist is made public and grid electrode layer is carried out the photomask PM of composition being used for, be positioned at the locational mode corresponding with light shielding part LS1, LS2 etc. and form light-shielding pattern LS with the pattern of gate electrode.In addition, under the situation of eurymeric, the size of light shielding part designs with the mode that the design load with respect to grid electrode layer becomes big slightly.Therefore, with respect to design load GE1D, the GE2D of grid electrode layer, each light shielding part LS1 of light-shielding pattern LS, the size of LS2 are set greatlyyer.Particularly because spread (diffraction) of the light that on each the end of each light shielding part LS1, LS2, makes public becomes many; So in the end of light shielding part LS1, LS2 (the 3rd pattern part) LS1c, LS2c; Compare with other part, big with respect to the expansion quantitative change of the pattern dimension of the design load GE1D of grid electrode layer, GE2D.

In this execution mode, light shielding part LS1 has at least: the first pattern part LS1a; The second pattern part LS1b; And the 3rd pattern part LS1c.The first pattern part LS1a is corresponding to the part of the grid electrode layer GE1 that on the CHN1 of the channel formation region territory of load transistor LT1, forms.The 3rd pattern part LS1c is corresponding to the part of the end of shared contact hole SC1 one side of grid electrode layer GE1.The second pattern part LS1b is corresponding to the part of the grid electrode layer GE1 that is clipped by the above-mentioned first pattern part LS1a and the 3rd pattern part LS1c in addition, and corresponding to the formation of grid electrode layer GE1 the part of breach.

Mainly with reference to Figure 17, in overlooking, light shielding part LS1 has sidewall E11, E12A, E12B and the opposing party's of a side toward each other sidewall E13, E14A, E14B.In overlooking; The side's of the second pattern part LS1b sidewall E12A; Compare with the imaginary extended line E11a of the side's of the first pattern part LS1a sidewall E11, be positioned on the position that E13, E14A, E14B one lateral deviation to the opposing party's of light shielding part LS1 sidewall one side leave.In this external overlooking; The line width of the second pattern part LS1b (2 * W12) center line (C12-C12 line); (2 * W11) center line (C11-C11 line) is positioned on the position that sidewall E13, E14A, E14B one lateral deviation to the opposing party leave with respect to the line width of the first pattern part LS1a.

In addition, a side sidewall E12A compares with the side's of the 3rd drafting department LS1c sidewall E12B, is positioned on the position of the opposing party's sidewall E13, E14A, E14B one side.

According to this execution mode, as shown in Figure 6, in overlooking, the side's of grid electrode layer GE1 sidewall E2 is positioned on the position of the opposing party's sidewall E3 one side with respect to the imaginary extended line E1a of a side sidewall E1.It is bad that opening takes place in the time of thus, can being suppressed at the formation of shared contact hole SC1.Below, it is described.

If, shown in figure 18, suppose that each linearity ground of grid electrode layer GE1, GE2 extends, do not have the situation of breach.In this case, the summary section along the XIX-XIX line of Figure 18 that forms in the way at shared contact hole is shown in figure 19.With reference to Figure 19, shared contact hole has the cone shape section shape that darker opening diameter becomes more little from the open end position usually.Therefore, when shared contact hole SC2 connected interlayer insulating film II1 arrival liner nitride film LN, the etching area of the liner nitride film LN that in the bottom of shared contact hole SC2, exposes also diminished.

In addition, when the etching of the formation that is used for shared contact hole SC2, have that sidewall spacer SW's on the sidewall be positioned at grid electrode layer GE1 is outstanding.Therefore, the distance W 1 along the bottom of the edge portion of the long side direction of the bottom of the part of the liner nitride film LN of sidewall spacer SW and shared contact hole SC2 diminishes.

And then because the superimposed error of mask, the position that from Figure 19, is represented by dotted lines in the formation position of shared contact hole SC2 is offset under the locational situation shown in the solid line, and above-mentioned distance W 1 further diminishes.

Under the situation that above-mentioned distance W 1 diminishes,, on the part of this distance W 1, produce the residue of interlayer insulating film II1 like this owing to micro loading effect.When under this state, liner nitride film LN being carried out etching, it is bad that opening takes place.

With respect to this; In this execution mode, as shown in Figure 6, in overlooking; In the part that the shared contact hole SC1 of grid electrode layer GE1 arrives, a side's of this part sidewall E2 moves back to the opposing party's sidewall E3 one rear flank with respect to the imaginary extended line E1a of a side sidewall E1.The part that arrives about the shared contact hole SC2 of grid electrode layer GE2 also is same.Thus, shown in figure 20, can make along the distance W 2 of the bottom of the edge portion of the long side direction of the bottom of the part of the liner nitride film LN of sidewall spacer SW and shared contact hole SC1 to increase than situation shown in Figure 19.Therefore, on the part of this distance W 2, be difficult to produce residue, the opening in the time of can suppressing shared contact hole SC1 and form is bad.

In addition, also be same about shared contact hole SC2, can suppress the bad generation of opening.

Execution mode 2

With reference to Figure 21, the structure of this execution mode is compared with the structure of execution mode 1, and difference is that a side sidewall E2 intersects with respect to a side sidewall E1 obliquely.Particularly; One side's sidewall E2 is with respect to the imaginary extended line E1a of a side sidewall E1; Tilt to the mode that move back the opposing party's sidewall E4 one rear flank more to leave channel formation region territory CHN1 more, a side sidewall E2 is with respect to imaginary extended line E1a angulation θ 1 and the intersection of a side sidewall E1.

In this external overlooking; The center line (C2-C2 line) of the line width D1 of the part that the shared contact hole SC1 of grid electrode layer GE1 arrives; Center line (C1-C1 line) with respect to the line width D2 of the part on the channel formation region territory CHN1 that is positioned at grid electrode layer GE1 is positioned on the position that the opposing party's sidewall E4 one lateral deviation leaves.In addition, the center line of line width D1 (C2-C2 line) tilts with respect to the center line (C1-C1 line) of line width D2.Have again, line width D1 and line width D2 with the line width definition of a sidewall E1 of a side and a side's sidewall E3 vertical direction.

With respect to the position deviation of the side's of the imaginary extended line E1a of an above-mentioned side's sidewall E1 sidewall E2, be to be provided with breach on the part that arrives through shared contact hole SC1 to produce at grid electrode layer GE1.That is to say that in overlooking, the part that the shared contact hole SC1 of grid electrode layer GE1 arrives has following breach, i.e. a side the sidewall E2 breach that moves back and tilt to the opposing party's sidewall E3 one rear flank with respect to the imaginary extended line E1a of a side sidewall E1.

In addition, the opposing party's of the part on the channel formation region territory CHN1 of the opposing party's of the part of the shared contact hole SC1 arrival of grid electrode layer GE1 sidewall E4 and grid electrode layer GE1 sidewall E3 is located along the same line in fact.In addition, in overlooking, (the p type extrinsic region) end of PIR, drain region of preferred load transistor LT2 and the beeline L of a side sidewall E2 are more than the 5nm.

In addition, grid electrode layer GE2 also has the structure same with grid electrode layer GE1.

About structure in addition, since roughly the same with the structure of execution mode 1, give same Reference numeral to same key element, do not repeat its explanation.

Then, the structure to the photomask that is used to form above-mentioned grid electrode layer describes.

With reference to Figure 22, in overlooking, the light shielding part LS1 of the photomask of this execution mode has sidewall E11, E12A, E12B and the opposing party's of a side toward each other sidewall E13, E14A, E14B.In overlooking, the side's of the second pattern part LS1b sidewall E12A compares with the imaginary extended line E11a of the side's of the first pattern part LS1a sidewall E11, is positioned on the position that sidewall one side E13, E14A, E14B one lateral deviation to the opposing party leave.In this external overlooking; The line width of the second pattern part LS1b (2 * W12) center line (C12-C12 line); (2 * W11) center line (C11-C11 line) is positioned on the position that sidewall E13, E14A, E14B one lateral deviation to the opposing party leave with respect to the line width of the first pattern part LS1a.

In addition; Compare a side the sidewall E12B of the 3rd drafting department LS1c of the front that is positioned at light shielding part LS1 with a side sidewall E12; Compare with the side's of the second drafting department LS1b sidewall E12A, further move back to the opposing party's sidewall E13, E14A, E14B one rear flank.

About structure in addition, since roughly the same with the structure of execution mode 1, so give same Reference numeral, do not repeat its explanation to same key element.

According to this execution mode, shown in figure 21, in overlooking, in the part that the shared contact hole SC1 of grid electrode layer GE1 arrives, a side's of this part sidewall E2 moves back to the opposing party's sidewall E3 one rear flank with respect to the imaginary extended line E1a of a side sidewall E1.Thus, same with execution mode 1, it is bad that opening takes place in the time of can being suppressed at the formation of shared contact hole SC1.

In addition, also be same about shared contact hole SC2, can suppress the bad generation of opening.

Execution mode 3

In above-mentioned execution mode 1 and 2; Explained the part that the shared contact hole SC1 (or SC2) of grid electrode layer GE1 (or GE2) arrives the opposing party sidewall E4 and be positioned at the opposing party's of the part on the channel formation region territory CHN1 (or CHN2) of grid electrode layer GE1 (or GE2) the situation of sidewall E3 on same straight line.But the present invention is positioned at the opposing party's sidewall E4 and the opposing party's sidewall E3 under the situation of different straight lines and also can uses.Therefore, in execution mode 3 and 4 sidewall E4 and the opposing party's of explanation the opposing party sidewall E3 in the situation of different straight lines.

With reference to Figure 23, the structure of this execution mode is compared with the structure of execution mode 1, and difference is that the opposing party's sidewall E4 and the opposing party's sidewall E3 are positioned on the different straight lines.

In this execution mode; The opposing party's of the part that the shared contact hole SC1 of grid electrode layer GE1 arrives sidewall E4; Sidewall E3 with respect to the opposing party of the part on the channel formation region territory CHN1 of grid electrode layer GE1 extends in fact abreast, and with respect to this opposing party's sidewall E3, be positioned on the position that the opposition side to a side sidewall E2 one side departs from.In addition, the line width D1 of the part that the shared contact hole SC1 of grid electrode layer GE1 arrives, identical with the line width D2 of part on the channel formation region territory CHN1 of grid electrode layer GE1 also can, difference also can.Have again, line width D1 and line width D2 with the line width definition of a sidewall E1 of a side and a side's sidewall E3 vertical direction.

In addition, grid electrode layer GE2 also has the structure same with grid electrode layer GE1.

About structure in addition, since roughly the same with the structure of execution mode 1, so give same Reference numeral, do not repeat its explanation to same key element.

Then, the structure to the photomask that is used to form above-mentioned grid electrode layer describes.

With reference to Figure 24, in overlooking, the light shielding part LS1 of the photomask of this execution mode has sidewall E11, E12A, E12B and the opposing party's of a side toward each other sidewall E13, E14A, E14B.In overlooking, the side's of the second pattern part LS1b sidewall E12A compares with the imaginary extended line E11a of the side's of the first pattern part LS1a sidewall E11, is positioned on the position that sidewall one side E13 one lateral deviation to the opposing party of light shielding part LS1 leaves.In this external overlooking; The line width of the second pattern part LS1b (2 * W12) center line (C12-C12 line); (2 * W11) center line (C11-C11 line) is positioned on the position that the opposing party's sidewall E13 one lateral deviation leaves with respect to the line width of the first pattern part LS1a.

In addition, the side's of the second drafting department LS1b sidewall E12A is positioned at a side the sidewall E12B of the 3rd drafting department LS1c of the front of light shielding part LS1 with respect to the sidewall E12A than this side, move back to the opposing party's sidewall E14A, E14B one rear flank.

In addition, the opposing party's sidewall E14A compares with the opposing party's sidewall E13, is positioned on the position that the opposition side to a side sidewall E12A departs from.In addition, the opposing party's sidewall E14B compares with the opposing party's sidewall E14A, is positioned on the position that the opposition side of sidewall E12A to a side, E12B departs from.

About structure in addition, since roughly the same with the structure of execution mode 1, so give same Reference numeral, do not repeat its explanation to same key element.

According to this execution mode, shown in figure 23, in overlooking, in the part that the shared contact hole SC1 of grid electrode layer GE1 arrives, a side's of this part sidewall E2 moves back to the opposing party's sidewall E3 one rear flank with respect to the imaginary extended line E1a of a side sidewall E1.Thus, same with execution mode 1, it is bad that opening takes place in the time of can being suppressed at the formation of shared contact hole SC1.

In addition, also be same about shared contact hole SC2, can suppress the bad generation of opening.

Execution mode 4

With reference to Figure 25; The structure of this execution mode is compared with the structure of execution mode 2; Difference be the opposing party's sidewall E4 and the opposing party's sidewall E3 on different straight lines, and each each inclination of a side sidewall E2 and the opposing party's sidewall E4 with respect to a side sidewall E1 and the opposing party's sidewall E3.

In this execution mode; One side's of the part that the shared contact hole SC1 of grid electrode layer GE1 arrives sidewall E2; With respect to a side's of the part on the channel formation region territory CHN1 of grid electrode layer GE1 sidewall E1, so that CHN1 leaves the mode of moving back to the opposing party's sidewall E4 one rear flank more and tilts from the channel formation region territory more.

The opposing party's of the part that arrives of the shared contact hole SC1 of grid electrode layer GE1 sidewall E4 in addition; With respect to the opposing party's of the part on the channel formation region territory CHN1 of grid electrode layer GE1 sidewall E3, so that CHN1 leaves more the mode of retreating to the opposition side of a side sidewall E2 and tilts from the channel formation region territory more.In addition, the line width D1 of the part that the shared contact hole SC1 of grid electrode layer GE1 arrives, identical with the line width D2 of part on the channel formation region territory CHN1 of grid electrode layer GE1 also can, difference also can.Have again, line width D2 with the line width definition of a sidewall E1 of a side and a side's sidewall E3 vertical direction, line width D1 defines with the line width with a sidewall E2 of a side and a side's sidewall E4 vertical direction.

In addition, grid electrode layer GE2 also has same structure with grid electrode layer GE1.

About structure in addition, since roughly the same with the structure of execution mode 2, give same Reference numeral to same key element, do not repeat its explanation.

Then, the structure to the photomask that is used to form above-mentioned grid electrode layer describes.

With reference to Figure 26, the light shielding part LS1 of the photomask of this execution mode in overlooking, has: sidewall E11, E12A, E12B and the opposing party's of a side toward each other sidewall E13, E14A～E14C.In overlooking, the side's of the second pattern part LS1b sidewall E12A compares with the imaginary extended line E11a of the side's of the first pattern part LS1a sidewall E11, is positioned on the position that sidewall one side E13 one lateral deviation to the opposing party of light shielding part LS1 leaves.In this external overlooking; The line width of the second pattern part LS1b (2 * W12) center line (C12-C12 line); (2 * W11) center line (C11-C11 line) is positioned on the position that the opposing party's sidewall E13 one lateral deviation leaves with respect to the line width of the first pattern part LS1a.

In addition, be positioned at a side the sidewall E12B of the 3rd drafting department LS1c of the front of light shielding part LS1 than a side sidewall E12A, compare, further move back to the opposing party's sidewall E13 one rear flank with the side's of the second drafting department LS1b sidewall E12A.

In addition, the opposing party's sidewall E14A compares with the opposing party's sidewall E13, is positioned on the position that the opposition side to a side sidewall E12A one side departs from.In addition, the opposing party's sidewall E14C compares with the opposing party's sidewall E14A, is positioned on the position that the opposition side to a side sidewall E12A one side departs from.In addition, the opposing party's sidewall E14B compares with the opposing party's sidewall E14C, is positioned on the position that the opposition side to the side of a side sidewall E12A departs from.

About structure in addition, since roughly the same with the structure of execution mode 1, give same Reference numeral to same key element, do not repeat its explanation.

According to this execution mode, shown in figure 25, in overlooking, in the part that the shared contact hole SC1 of grid electrode layer GE1 arrives, a side's of this part sidewall E2 moves back to the opposing party's sidewall E3 one rear flank with respect to the imaginary extended line E1a of a side sidewall E1.Thus, same with execution mode 1, the bad generation of opening in the time of can being suppressed at the formation of shared contact hole SC1.

In addition, also be same about shared contact hole SC2, can suppress the bad generation of opening.

In this execution mode; Explained that shared contact hole arrives grid electrode layer and the opposing party's the structure of drain region of load transistor of a side load transistor, but be that other transistorized grid electrode layer and the structure of other extrinsic region of shared contact hole arrival also can.

In addition, though as the element with shared contact hole SRAM has been described, as long as have shared contact hole, the present invention also can be applied to the element beyond the SRAM.

In addition, though be that the situation of MOS transistor is illustrated to each transistor that constitutes SRAM, the present invention is not limited to MOS transistor, can be applied to insulated-gate type field effect transistor.

(configurations of a plurality of SRAM memory cells)

The structure of the memory cell of the structure of each memory cell MC shown in Figure 27 and Fig. 2～shown in Figure 6 is roughly the same.

With reference to Figure 27, among Figure 27 on directions X each of adjacent memory cell MC, the imaginary element sides boundary line between having relative to each other and the plane figure of line symmetry each other.And adjacent memory cell MC has the side of grid electrode layer GE3 and GE4 each other on this directions X.That is to say; The grid electrode layer GE3 of the grid electrode layer GE3 of an adjacent side's memory cell MC and the opposing party's memory cell MC becomes whole conductive layer on directions X, or the grid electrode layer GE4 of grid electrode layer GE4 and the opposing party's of an adjacent side's memory cell MC memory cell MC becomes the conductive layer of integral body on directions X

In addition, in Figure 27 on the Y direction each of adjacent memory cell MC, the imaginary element sides boundary line between having relative to each other and the plane figure of line symmetry each other.And; On this Y direction among the adjacent memory cell MC; Each of the source region PIR of the regions and source NIR of access transistor AT1, load transistor LT2 and the source region NIR of driver transistor DT2 constitutes through single extrinsic region, or each of the source region NIR of the source region PIR of the regions and source NIR of access transistor AT2, load transistor LT1 and driver transistor DT1 constitutes through single extrinsic region.

On this external Y direction among the adjacent memory cell MC, the opposing party's of grid electrode layer GE2 sidewall E3, E4 in overlooking toward each other, or the opposing party's of grid electrode layer GE1 sidewall E3, E4 in overlooking toward each other

With the interval LE2a of the side's of the grid electrode layer GE2 of the opposing party's of grid electrode layer GE2 sidewall E3, E4 toward each other the mode side's of the grid electrode layer GE2 of the side's among the adjacent pair of memory MC memory cell MC on the Y direction in overlooking sidewall E1 and the opposing party's memory cell MC sidewall E1, bigger than the interval LE1a of the side's of the grid electrode layer GE2 of the side's of the grid electrode layer GE2 of this side's memory cell MC sidewall E2 and the opposing party's memory cell MC sidewall E2.

In addition; With the interval of the side's of the grid electrode layer GE1 of the opposing party's of grid electrode layer GE1 sidewall E3, E4 toward each other the mode side's of the grid electrode layer GE1 of the side's among the adjacent pair of memory MC memory cell MC on the Y direction in overlooking sidewall E1 and the opposing party's memory cell MC sidewall E1, also big than the interval of the side's of the grid electrode layer GE1 of the side's of the grid electrode layer GE1 of this side's memory cell MC sidewall E2 and the opposing party's memory cell MC sidewall E2.

Have, the structure of memory cell MC in addition and the structure of the described memory cell of Fig. 2～Fig. 6 are roughly the same again, therefore omit its explanation.

In addition; In the structure of the execution mode 2 that the above-mentioned structure that is listed as the SRAM memory cell of configuration with two row two shown in figure 28 also can likewise be applied to; In the structure of the execution mode that also can likewise be applied to 3 shown in figure 29 in addition, in the structure of the execution mode that also can likewise be applied to 4 shown in figure 30 in addition.

Have again; In Figure 29 and structure shown in Figure 30; With the opposing party's of grid electrode layer GE2 sidewall E3, E4 toward each other mode in overlooking; The interval LE2b of the opposing party's of the grid electrode layer GE2 of the opposing party's of the grid electrode layer GE2 of a side's on the Y direction among the adjacent pair of memory MC memory cell MC sidewall E3 and the opposing party's memory cell MC sidewall E3 is bigger than the interval LE1b of the side's of the grid electrode layer GE2 of the opposing party's of the grid electrode layer GE2 of this side's memory cell MC sidewall E4 and the opposing party's memory cell MC sidewall E4.

In addition; With the opposing party's of grid electrode layer GE1 sidewall E3, E4 toward each other mode in overlooking; The interval of the opposing party's of the grid electrode layer GE1 of the opposing party's of the grid electrode layer GE1 of a side's on the Y direction among the adjacent pair of memory MC memory cell MC sidewall E3 and the opposing party's memory cell MC sidewall E3, also big than the interval of the opposing party's of the grid electrode layer GE1 of the opposing party's of the grid electrode layer GE1 of this side's memory cell MC sidewall E4 and the opposing party's memory cell MC sidewall E4.

As stated; In the configuration structure of a plurality of SRAM memory cells; Through any combination of shapes of grid electrode layer, shown in Figure 27～30, in overlooking with execution mode 1～4; In the part that the shared contact hole SC1 of grid electrode layer GE1 arrives, a side's of this part sidewall E2 moves back to the opposing party's sidewall E3 one rear flank with respect to the imaginary extended line of a side sidewall E1.It is bad that opening takes place in the time of thus, can being suppressed at the formation of shared contact hole SC1.

In addition, also be same about shared contact hole SC2, can suppress the bad generation of opening.

(to the application of Content Addressable Memory)

The structure of above-mentioned execution mode 1～4 also can be applied to the content addressable memory (CAM) cell (CAM:Content Addressable Memory) that has the structure of SRAM memory cell at storage part.Below, as content addressable memory (CAM) cell, with the content addressable memory (CAM) cell that holds 3 Value Datas, be that TCAM (Ternary CAM) is that example describes.

At first circuit structure and the work thereof about the TCAM unit describes.

With reference to Figure 31, the TCAM unit comprises: data store MR, hold the retrieval alternate data; And search part SR, relatively should retrieval alternate data and retrieve data SL ,/SL, according to this comparative result driving and matching line (match line) ML.

Data store MR comprises two memory cells (X1 unit and Y1 unit).This X1 unit and Y1 unit have the structure of SRAM memory cell.Because X1 unit and Y1 unit both sides have mutually the same structure; And have and the identical structure of the described SRAM memory cell of Fig. 1; So in the X1 unit and Y1 unit in Figure 31; To giving identical Reference numeral, omit its explanation with the corresponding part of the SRAM memory cell of Fig. 1.

In this TCAM unit, through utilizing two memory cell X1, Y1, thereby can hold 3 Value Datas.

Search part SR comprises: corresponding to the MOS transistor TQ1 and the TQ2 of X1 unit setting; MOS transistor TQ3 and TQ4 corresponding to the setting of Y1 unit.MOX transistor T Q1 and TQ2 are connected in series between matched line ML and ground connection node.The memory node N2 of the grid of MOS transistor TQ1 and X1 unit links.MOS transistor TQ2 receives retrieval alternate data position S L at grid.

MOS transistor TQ3 and TQ4 are connected in series between matched line ML and the ground connection node.The memory node N2 of the grid of MOS transistor TQ3 and Y1 unit links.MOS transistor TQ4 receives the counter-rotating position/SL of retrieve data at grid.

X1 unit and Y1 unit can be according to word line drive signal WLX and WLY, and individually setting should the storage data.Be described below, 3 state of value are realized in this TCAM unit.

(1) the memory node N2 in the X1 unit is the memory node N2 of H level (logic high), Y1 unit when being L level (logic low):

In this case, if retrieve data position (below, only be called retrieve data) SL is the H level, MOS transistor TQ1 and TQ2 conducting together, matched line ML discharge.In the X1 unit, hold the reversal data of retrieving alternate data.Therefore, in this state, be miss state (miss hit state).On the other hand, if retrieve data SL is the L level, MOS transistor TQ2 is a nonconducting state, and MOS transistor TQ3 also is a nonconducting state in addition.Therefore, matched line ML does not discharge under this state, keeps precharge voltage level.This state is the hit condition (hit state) of retrieve data and storage data consistent.

(2) the memory node N1 in the X1 unit is the memory node N2 of L level, Y1 unit when being the H level:

In this case, if retrieve data SL is the H level, additional retrieve data/SL is the H level.Therefore, MOS transistor TQ3 and TQ4 conducting together, matched line ML discharge.Retrieve data/SL is the retrieve data of replenishing.Therefore, in this state, be miss state.On the other hand, if retrieve data SL is the H level, additional retrieve data/SL is the L level.Therefore, MOS transistor TQ4 becomes nonconducting state, and MOS transistor TQ1 also is a nonconducting state in addition.Therefore, matched line ML keeps the pre-charge voltage state.Therefore, this state is a hit condition.

When (3) the memory node N2 in X1 unit and Y1 unit all is the L level:

In this state, MOS transistor TQ1 and TQ3 all are nonconducting states.Therefore, the logical value of matched line ML and retrieve data SL is irrelevant, keeps precharge voltage level.Therefore, can realize " freely choosing state (don ' t care state) " to retrieve data SL through this state.

When (4) the memory node N2 in X1 unit and Y1 unit all is the H level:

Under this state, according to the logical value of retrieve data SL, side's conducting in the path of the path of MOS transistor TQ1 and TQ2 and MOS transistor TQ3 and TQ4, matched line ML discharge.Therefore, always be designated as miss state with retrieve data is irrelevant, so this state is used as illegal state usually.

As stated, this TCAM unit can be to comprising: 3 Value Datas of the L storage of the H storage of state (1), state (2) and the state of freely choosing of state (3) are stored.

Then, the plane figure with the structure applications of the execution mode 1 TCAM unit in the circuit structure shown in Figure 31 is described.

Figure 33 representes through component isolation structure by the active region of electric isolation and the extrinsic region that in this active region, forms.Figure 34 is illustrated in the structure of having appended grid electrode layer in the plane figure of Figure 33.Figure 35 is illustrated in the allocation position of the shared contact hole that forms on the interlayer insulating film of cover gate electrode layer etc. and common contact hole.Figure 36 is illustrated in the pattern of the conductive layer that forms on the interlayer insulating film of Figure 35.

With reference to Figure 32 and Figure 33, through on the surface of the Semiconductor substrate that is formed with p type well region PW1, PW2 and n type well region NW, forming component isolation structure selectively, thereby the mutual electric in a plurality of active regions is isolated on the surface of Semiconductor substrate.Be formed with n type extrinsic region NIR in each active region that is arranged in p type well region PW1, PW2, be formed with p type extrinsic region PIR in each active region that is arranged in n type well region NW.

N type extrinsic region NIR constitutes the transistorized regions and source of nMOS, between a pair of n type extrinsic region NIR, clips p type channel formation region territory CHN.In addition, p type extrinsic region PIR constitutes the transistorized regions and source of pMOS, between a pair of p type extrinsic region PIR, clips n type channel formation region territory CHN1 or CHN2.

With reference to Figure 32 and Figure 34, CHN, CHN1, the last grid electrode layer GE1～GE6 that is formed with respectively of CHN2 in the channel formation region territory.The SRAM memory cell of X1 unit among the data store MR and the flat shape of the grid electrode layer GE1～GE4 in the Y1 unit and plane figure and the described execution mode 1 of Fig. 2 is same.

In test section SR, constitute nMOS transistor T Q1 through a pair of n type extrinsic region NIR and grid electrode layer GE2, constitute nMOS transistor T Q2 through a pair of n type extrinsic region NIR and grid electrode layer GE5.In addition, constitute nMOS transistor T Q3, constitute nMOS transistor T Q4 through a pair of n type extrinsic region NIR and grid electrode layer GB6 through a pair of n type extrinsic region NIR and grid electrode layer GE2.

The grid electrode layer GE2 of nMOS transistor T Q1 is that whole conductive layer forms through each the grid electrode layer GE2 with the load transistor LT2 of X1 unit and driver transistor DT2.In addition, the grid electrode layer GE2 of nMOS transistor T Q3 is that whole conductive layer forms through each the grid electrode layer GE2 with the load transistor LT2 of X2 unit and driver transistor DT2.

With reference to Figure 32 and Figure 35, form interlayer insulating film (not shown) with the mode on cladding element isolation structure, active region and the grid electrode layer, in this interlayer insulating film, be formed with shared contact hole SC1, SC2 and common contact hole CH1～CH15.

The plane figure of shared contact hole SC1 in X1 unit among the data store MR and the Y1 unit, SC2 and common contact hole CH1～CH10 and the SRAM memory cell of the described execution mode 1 of Fig. 2 are same.

Contact hole CH11 arrives the regions and source NIR of nMOS transistor T Q1 in search part SR, and contact hole CH12 arrives the regions and source NIR of nMOS transistor T Q3.In addition, contact hole CH13 arrives the grid electrode layer GE5 of nMOS transistor T Q2, and contact hole CH14 arrives the grid electrode layer GE6 of nMOS transistor T Q4.In addition, contact hole CH15 arrives with nMOS transistor T Q2 and the total regions and source NIR of TQ4.

With reference to Figure 32 and Figure 36, on the interlayer insulating film that is formed with shared contact hole SC1, SC2 and contact hole CH1～CH10, be formed with the conductive layer CL1 that is patterned into the regulation shape.

The SRAM memory cell of X1 unit among the data store MR and the flat shape of the conductive layer CL1 in the Y1 unit and plane figure and the described execution mode 1 of Fig. 2 is same.

In search part SR, be formed with conductive layer CL1 with the contact hole CH2 of electrical connection X1 unit and the mode of contact hole CH11.In addition, be formed with conductive layer CL1 with the contact hole CH2 of electrical connection X2 unit and the mode of contact hole CH12.

In addition, the conductive layer CL1 that is electrically connected with contact hole CH13, the conductive layer CL1 that is electrically connected with contact hole CH14 form with the conductive layer CL1 that is electrically connected with contact hole CH15 each other isolator.

Figure 37 and Figure 38 are the plane graphs of plane figure on more upper strata that is illustrated in the plane figure of Figure 32 successively.Have, Figure 37 is illustrated in the allocation position of the through hole that forms on the interlayer insulating film that covers conductive layer again.Figure 38 is illustrated in the pattern of the conductive layer that forms on the interlayer insulating film of Figure 37.

With reference to Figure 37, be formed with interlayer insulating film (not shown) with the mode that covers on the conductive layer CL1, on this interlayer insulating film, be formed with through hole VH11, VH13～18 and VH31～35.

The SRAM memory cell of the plane figure of X1 unit among the data store MR and the through hole VH11 in the Y1 unit, VH13～18 and execution mode 1 shown in Figure 3 is same.

In search part SR, through hole VH31 arrives the conductive layer CL1 that is used to be electrically connected contact hole CH11 and contact hole CH2.Through hole VH32 arrives the conductive layer CL1 that is used to be electrically connected contact hole CH12 and contact hole CH2.Through hole VH33 arrives the conductive layer CL1 that is used to be electrically connected to contact hole CH13, and through hole VH34 arrives the conductive layer CL1 that is used to be electrically connected to contact hole CH14, and through hole VH35 arrives the conductive layer CL1 that is used to be electrically connected to contact hole CH15.

With reference to Figure 38, on the interlayer insulating film that is formed with through hole VH11～18 and VH31～35, be formed with the conductive layer CL2 that is patterned into the regulation shape.

The SRAM memory cell of X1 unit among the data store MR and the flat shape of the conductive layer CL2 in the Y1 unit and plane figure and the described execution mode 1 of Fig. 3 is same.

In search part SR, be formed with the retrieve data line SL that constitutes by the conductive layer CL2 that is electrically connected to through hole VH33.In addition, be formed with the retrieve data line/SL that replenishes that constitutes by the conductive layer CL2 that is electrically connected to through hole VH34.Retrieve data line SL and the retrieve data line/SL that replenishes extend parallel to each other.

In addition, with conductive layer CL2 that is electrically connected to through hole VH31 and the conductive layer CL2 that is electrically connected to through hole VH32, form isolator each other with the conductive layer CL2 that is electrically connected to through hole VH35.

Like this, constituted the plane figure that the structure applications of execution mode 1 is arrived the TCAM unit of circuit structure shown in Figure 31.

In addition; Plane figure structure to above-mentioned TCAM unit; Can use the structure of execution mode shown in Figure 39 2 too, can use the structure of execution mode shown in Figure 40 3 in addition too, can use the structure of execution mode shown in Figure 41 4 in addition too.

As stated; In the structure of content addressable memory (CAM) cell; Any shape of grid electrode layer through to execution mode 1～4 makes up, shown in Figure 32 and Figure 39～41, in overlooking; In the part that the shared contact hole SC1 of grid electrode layer GE1 arrives, a side's of this part sidewall E2 moves back to the opposing party's sidewall E3 one rear flank with respect to the imaginary extended line of a side sidewall E1.It is bad during etching in the time of thus, can being suppressed at shared contact hole SC1 and forming opening to take place.

In addition, also be same about shared contact hole SC2, it is bad to suppress that opening takes place.

The present invention is particularly conducive to and is applied to semiconductor device with the shared contact hole that arrives grid electrode layer and extrinsic region both sides and the photomask that is used for the composition of this grid electrode layer.

The present invention at length is illustrated, but this just expression for example is not to limit, and can understand scope of the present invention very clearly and explain through the desired scope of technical scheme of the present invention.

Claims (8)

1. semiconductor device, wherein,

Possess: Semiconductor substrate (SB) has first type surface; Extrinsic region (PIR) forms on said first type surface; (LT1 LT2), forms on said Semiconductor substrate insulated-gate type field effect transistor; Insulating barrier (II1) forms on said extrinsic region and said insulated-gate type field effect transistor,

Said insulated-gate type field effect transistor comprises: a pair of regions and source (PIR) forms on said first type surface; And grid electrode layer (GE1, GE2), across gate insulator (GI) in channel formation region territory that said a pair of regions and source clips (CHN1 CHN2) goes up and forms,

The insulating barrier that on said extrinsic region and said insulated-gate type field effect transistor, forms have the shared contact hole that arrives said grid electrode layer and this two side of said extrinsic region (SC1, SC2),

Said grid electrode layer in overlooking, have a side toward each other sidewall (E1, E2) with the opposing party's sidewall (E3, E4),

In overlooking; A said side's of the part that the said shared contact hole of said grid electrode layer arrives sidewall (E2); Compare with the imaginary extended line (E1a) of the said side's of part on the said channel formation region territory that is positioned at said grid electrode layer sidewall (E1), (E3 is on the position that E4) lateral deviation leaves to be positioned at sidewall to said the opposing party; And

In overlooking; The center line (C2-C2) of the line width of the part that the said shared contact hole of said grid electrode layer arrives; Center line (C1-C1) with respect to the line width of the part on the said channel formation region territory that is positioned at said grid electrode layer is positioned on the position of departing from.

2. semiconductor device according to claim 1, wherein,

Said shared contact hole (SC1; The said grid electrode layer of the part that SC2) arrives (GE1, said the opposing party's GE2) sidewall (E4) is with said channel formation region territory (CHN1; CHN2) (GE1, said the opposing party's GE2) sidewall (E3) is located along the same line the said grid electrode layer on.

3. semiconductor device according to claim 1, wherein,

Said the opposing party's of the said grid electrode layer of the part that said shared contact hole arrives sidewall (E4) is positioned on the different straight lines with said the opposing party's of said grid electrode layer on the said channel formation region territory sidewall (E3).

4. semiconductor device according to claim 1, wherein,

In overlooking, a said side's of the said grid electrode layer of the part that said shared contact hole arrives sidewall (E2), parallel with respect to the said side's of the said grid electrode layer on the said channel formation region territory sidewall (E1).

5. semiconductor device according to claim 1, wherein,

In overlooking, a said side's of the said grid electrode layer of the part that said shared contact hole arrives sidewall (E2) is with respect to the said side's of the said grid electrode layer on the said channel formation region territory sidewall (E1) inclination.

6. semiconductor device according to claim 1, wherein,

First and second memory cells that comprise said extrinsic region and said insulated-gate type field effect transistor respectively; Dispose adjacent to each other in opposite directions mode in overlooking with said the opposing party's of the said grid electrode layer of said the opposing party's of the said grid electrode layer of said first memory unit sidewall and said second memory unit sidewall

Be positioned at the part on the said channel formation region territory of said grid electrode layer of said first memory unit a said side sidewall (E1) and be positioned at a said side's of the part on the said channel formation region territory of said grid electrode layer of said second memory unit the interval (LE2a) of sidewall (E1); Said grid electrode layer (GE1 than said first memory unit; GE2) (SC1, the interval (LE1a) of a said side's of the part that the said shared contact hole of a said side's of the part that SC2) arrives the sidewall (E2) and the said grid electrode layer of said second memory unit arrives sidewall (E2) is big for said shared contact hole.

7. semiconductor device according to claim 1, wherein,

Said extrinsic region and said insulated-gate type field effect transistor constitution content addressable memory (CAM) cell.

8. a photomask (PM), in the manufacturing approach of the described semiconductor device of claim 1, be used for said grid electrode layer (GE1, composition GE2), wherein,

Have: substrate (TS) sees through the light that makes public; Photomask pattern (LS) forms on said substrate, covers the seeing through of light of said exposure,

Said photomask pattern has: and first pattern part (LS1a, LS2a), corresponding in said channel region (CHN1, the part of the said grid electrode layer that CHN2) go up to form; And second pattern part (LS1b, LS2b), compare with said first pattern part be positioned at said shared contact hole (SC1, a SC2) side,

In overlooking, said photomask pattern have a side toward each other sidewall (E11, E12A) with the opposing party's sidewall (E13, E14A),

In overlooking; A said side's of said second pattern part sidewall (E12A); Compare with the imaginary extended line (E11a) of the said side's of said first pattern part sidewall (E11); Be positioned on the position that sidewall (E13, the E14A) lateral deviation to said the opposing party of said photomask pattern leaves, and

In overlooking, the center line of the line width of said second pattern part (C12-C12), the center line (C11-C11) with respect to the line width of said first pattern part is positioned on the position of departing from.

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