CN101466039A - Device and method for decoding video - Google Patents
Device and method for decoding video Download PDFInfo
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- CN101466039A CN101466039A CN 200810247439 CN200810247439A CN101466039A CN 101466039 A CN101466039 A CN 101466039A CN 200810247439 CN200810247439 CN 200810247439 CN 200810247439 A CN200810247439 A CN 200810247439A CN 101466039 A CN101466039 A CN 101466039A
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Abstract
The invention relates to a video decoder device and a method thereof. The device comprises a device resources perceivable unit, a frequency control unit and a multitask decoder. The device resources perceivable unit is used for determining the present available power; the frequency control unit is used for assigning working frequency for each task according to the present available power determined by the device resources perceivable unit; the multitask decoder is used for dividing video code stream into a plurality of tasks and decoding each task according to the working frequency for each task assigned by the frequency control unit. In the invention, the multitask parallel processing is carried out on the decoder and the frequency of each task and each function module is dynamically adjusted, thus reducing the power consumption under the premise of satisfying the system performance.
Description
Technical field
The present invention relates to the digital video signal processing field, relate in particular to a kind of video decoder and method.
Background technology
Along with the continuous development of communications industry, terminal comprehensively develops to speech, data, image, music and multimedia direction gradually by the mobile phone of original single call function etc., specifically comprises smart mobile phone, PDA etc.
Yet, as most of terminals especially mobile model terminal, rely on battery to power fully, along with the function of mobile device from strength to strength, its power loss is also increasing.Therefore, must improve the service time and the stand-by time of terminal equipment.Problem hereto, two kinds of solutions are arranged at present: a kind of is to be equipped with more jumbo battery; But increase the cost that will increase entire equipment on the total trend of battery capacity.Another kind is to improve system design, sophistication, the power loss of reduction mobile device.
Therefore, start with from the master-plan of mobile device, the technology of application of advanced and device reduce the conceptual design of power loss, thereby prolong the service time of mobile device as far as possible.In fact, low power dissipation design has become more and more urgent problem in the mobile device design.
Decoder takies more resource in the system as the key component of the processing system for video of mobile device, consumes a large amount of power of terminal, so how to reduce the power consumption of decoder, has crucial effects useful life for the battery that prolongs terminal.
The reduction of decoder power consumption also has a lot of implementation methods at present, generally concentrates on to the reduction of the algorithm complex of decoder or to the simplification of part of module.Prior art is primarily aimed at the reduction of decoder algorithm complexity and studies, and less consideration the inner link of inner each module of Video Decoder and power consumption control.Adopt the method that reduces decoding complex degree mostly for the power consumption that reduces Video Decoder, though can reduce the power consumption of decoder to a certain extent, a lot of all when reducing complexity, reduce performance, be difficult to guarantee the video reconstruction quality.
Through research, the energy consumption of cmos circuit can be by the following formula approximate evaluation:
P＝aV
2·f
CLK·C
EFF (1)
Wherein: V is the supply power voltage of circuit;
f
CLKBe clock frequency;
C
EFFEffective switch-capacitor for circuit;
A is an activity factor, is generally 0.5.
As can be seen from the above equation, the energy consumption P of cmos circuit and circuit voltage V square are directly proportional, and frequency f
CLKTherefore be directly proportional, reduce voltage and clock frequency and be one of effective method that reduces the circuit energy consumption.And reduce voltage and frequency can play a multiplier role to reducing power consumption.
Summary of the invention
In order to solve above-mentioned technical problem, a kind of video decoder devices of multi-task parallel is provided, its purpose is to handle by decoder being carried out multi-task parallel, and each task and functional module are carried out the dynamic frequency adjustment, can satisfy under the prerequisite of systematic function, greatly reduce power consumption.
The invention provides a kind of video decoder, comprising: device resource perception unit, frequency control unit, and multitask decoder;
Device resource perception unit is used for determining current available horsepower;
Frequency control unit, the current available horsepower that is used for determining according to device resource perception unit is each task assignment operating frequency;
The multitask decoder is used for video code flow is divided into a plurality of tasks, and is the operating frequency of each task institute assignment each task of decoding according to frequency control unit.
Also comprise the reconstruction video memory block, be used to receive the output of multitask decoder, and after each task decoding of present frame is finished in video code flow, after the order rearrangement according to each task video flowing is exported.
Device resource perception unit also is used for the operating state of awareness apparatus.
The multitask decoder comprises decoder multitask division unit and a plurality of decoding task unit;
Decoder multitask division unit is used for video code flow is divided into a plurality of chips of separating;
The decoding task unit is used for decoding to respectively separating chip.
The decoding task unit comprises: entropy decoding control unit, inverse transformation inverse quantization unit, inter prediction unit, intraprediction unit, and deblocking filtering unit.
Frequency control unit is determined the operating frequency respectively separate chip according to following formula:
Wherein: V is the supply power voltage of circuit, f
CLKBe i operating frequency of separating chip, C
EFFBe effective switch-capacitor of circuit, P is current available horsepower, and n is a sum of separating chip, P
iBe i and separate the power that chip distributes, m
iBe i and separate the number of macroblocks that chip comprises, i, j are natural number, 1≤i≤n, and 1≤j≤n, a are activity factor.
In i the decoding task unit: the operating frequency of entropy decoding control unit is τ
1F
CLK, the operating frequency of inverse transformation inverse quantization unit is τ
2F
CLK, the operating frequency τ of inter prediction unit
3F
CLK, the operating frequency of intraprediction unit is τ
4F
CLK, the operating frequency of unit, deblocking filtering unit is τ
5F
CLKWherein: τ
1, τ
2, τ
3, τ
4And τ
5For processing time of entropy decoding control unit, inverse transformation inverse quantization unit, inter prediction unit, intraprediction unit and deblocking filtering unit with respect to the decode ratio in processing time of control unit or inverse transformation inverse quantization unit or inter prediction unit or intraprediction unit or deblocking filtering unit of entropy; I decoding task unit is i decoding task unit of separating chip of decoding.
About to τ
kF
CLKAgreement: adjustable arbitrarily as device (comprising terminal or the chip) operating frequency that can provide in calculation process, τ then
kF
CLKIt directly is result calculated; Consider on the other hand that for a part of device (comprising terminal or chip) adjustable extent of the operating frequency that can provide not necessarily changes continuously, for example provide the available work frequency to be [f
1, f
2, f
3, f
4, f
5, f
6, f
7, f
8] or [f
1, f
2...] etc., so for τ
kF
CLKValue, in the adjustable operating frequency range that can provide for this device, near τ
kF
CLKFrequency values.
The invention provides a kind of video encoding/decoding method, comprising:
Step 1 is determined current available horsepower;
Step 2 is divided into a plurality of tasks with video code flow, is each task assignment operating frequency according to current available horsepower;
Step 3 is according to each task of decoding for the operating frequency of each task institute assignment.
Also comprise step 4, the reconstruction video memory block receives the output of multitask decoder, and after each task decoding of present frame is finished in video code flow, after the order rearrangement according to each task video flowing is exported.
In the step 1, also comprise the operating state of awareness apparatus.
Step 2 comprises:
Wherein: V is the supply power voltage of circuit, f
CLKBe i operating frequency of separating chip, C
EFFBe effective switch-capacitor of circuit, P is current available horsepower, and n is a sum of separating chip, P
iBe i and separate the power that chip distributes, m
iBe i and separate the number of macroblocks that chip comprises, i, j are natural number, 1≤i≤n, 1≤j≤n.
In the step 3, according to each task of decoding for the operating frequency of each task institute assignment.
The decoding task unit comprises: entropy decoding control unit, inverse transformation inverse quantization unit, inter prediction unit, intraprediction unit, and deblocking filtering unit.
In the step 2: in i decoding task unit: the decode operating frequency of control unit of entropy is appointed as τ
1F
CLK, the operating frequency of inverse transformation inverse quantization unit is appointed as τ
2F
CLK, the operating frequency of inter prediction unit is appointed as τ
3F
CLK, the operating frequency of intraprediction unit is appointed as τ
4F
CLK, the operating frequency of unit, deblocking filtering unit is τ
5F
CLKWherein: τ
1, τ
2, τ
3, τ
4And τ
5For processing time of entropy decoding control unit, inverse transformation inverse quantization unit, inter prediction unit, intraprediction unit and deblocking filtering unit with respect to the decode ratio in processing time of control unit or inverse transformation inverse quantization unit or inter prediction unit or intraprediction unit or deblocking filtering unit of entropy; I decoding task unit is i decoding task unit of separating chip of decoding.
The present invention carries out multitask to the Video Decoder technology and divides, obtaining rational multi-job operation, and the FREQUENCY CONTROL suitable to each task, to reach under the situation that guarantees the decoding overall performance power consumption of maximized reduction decoder.The invention provides a kind of frequency conversion multitask video decode and realize the low-power consumption video frequency decoding method, at each task handling asynchronism(-nization), each task is carried out dynamic frequency regulates, reduce the free time of whole system, can reduce power consumption to a great extent, and not influence the decode time of whole video.The responding system resource requirement, according to the different resource grade, realize gradable decoder output power control method, processing time difference according to each module, from macro-block level a plurality of functional modules are carried out frequency adjustment, to obtain power consumption lower under a certain power mode, make decoder under this power consumption, obtain the fastest decoding speed simultaneously.Just decoder has the extendible output mode of power consumption, also is that the power that decoder consumed under each output mode is different, and the user can select different output modes.
Description of drawings
Fig. 1 is known video decoder structure figure;
Fig. 2 is multitask video encoding/decoding method flow chart according to the present invention;
Fig. 3 is according to the extendible video decoder structure chart of the power of the embodiment of the invention;
Fig. 4 is each functional module elements streamline division figure according to the embodiment of the invention.
Embodiment
The present invention mainly provides a kind of video decoder and method, and it can reduce power consumption to a great extent, and does not influence the decoding quality of whole video.
Video decoder provided by the invention comprises: device resource perception unit, frequency control unit, and multitask decoder;
Device resource perception unit is used for determining current available horsepower.Specifically be used for determining the current available horsepower of equipment.Equipment refers to support battery powered certain concrete terminal, can be PDA, smart mobile phone, Embedded Real-Time equipment etc.Operation video decode program can be supported the various video formats on the equipment, comprises QCIF, CIF, QVGA, VGA, D1 etc., and H.264 the video decompression standard can adopt, MPEG4, MPEG2, AVS etc.
Frequency control unit, the current available horsepower that is used for determining according to device resource perception unit is each task assignment operating frequency.Specifically the current available horsepower of determining according to device resource perception unit adopts the dynamic frequency control method, is each task assignment operating frequency, regulates the processing speed of multitask decoder.
The multitask decoder is used for video code flow is divided into a plurality of tasks, and is the operating frequency of each task institute assignment each task of decoding according to frequency control unit.
Wherein frequency control unit can be arranged within the multitask decoder, also can be arranged on outside the multitask decoder.
The multitask decoder comprises decoder multitask division unit, is used for Video Decoder is divided into a plurality of tasks, and in the operating frequency task queue that each Task Distribution is different;
The multitask decoder, comprise a plurality of task division, specifically comprise: entropy decoding task module, modules such as inverse discrete cosine transformation (IDCT) task module, deblocking filtering task module, Intra (in the frame) prediction task module and Inter (interframe) prediction task module are formed.
Another aspect of the present invention also provides a kind of power scalability video decoder, comprising:
1) device resource perception unit is used for determining current available horsepower;
2) multitask of setting decoder module is divided, and the operating frequency that sets the tasks; Realize the control of low-power consumption decoder;
3) described each functional module is handled output video to video under selected processing frequency.
In order to make technical scheme of the present invention and advantage clearer,, a kind of video decoder of the present invention and method are further elaborated below in conjunction with drawings and Examples.
Fig. 1 is the structural representation of known Video Decoder, and Video Decoder is made up of modules such as entropy decoder module 100, inverse discrete cosine transformation (IDCT) module 102, deblocking filtering module 104, Intra (in the frame) prediction module 110 and Inter (interframe) prediction module 112.One group of conversion coefficient X after bit stream after the compression obtains quantizing through decoder module 100 passes through inverse discrete cosine transformation module 102 again, obtains residual error D
n'.Information such as the predictive mode that Inter prediction module 112 or Intra prediction 110 obtain according to entropy decoder module 100 parsing video code flows, motion vector, reference frame, from frame of video buffer memory 108, take out corresponding reference image data and generate a prediction piece, predict piece and residual error D then
nAfter the addition, obtain the frame of non-filtered,, improve picture quality, again through getting decoding output image to the end behind the deblocking filtering 104 in order to remove noise.
The complexity of each module described in Fig. 1 is different, for processing time of each macro block also be inequality.So, how under power limited condition, reasonably select the processing frequency of each module, make to guarantee under the situation of video decode speed, thereby bigger reduction power consumption is vital to decoder.Comprehensive each module of the present invention has been carried out the dynamic frequency stage division and has been handled the influence and the computation complexity of video quality, has obtained the video encoding/decoding method of low-power consumption.
As shown in Figure 2, multitask video decoder of the present invention comprises the multitask Video Decoder 23 with a plurality of tasks 232, and device resource perception unit 21, frequency control unit 22, wherein:
Described device resource perception unit 21 is used for the operating state of awareness apparatus, and for example dump energy and user specify etc.;
The operating state of concrete device resource perception unit 21 awareness apparatus.Wherein operating state determine mainly following two aspects of foundation: the one, the user specifies, the user can be operated in according to the needs appointing system of oneself: under power saving, the common or sufficient electric weight isotype; The 2nd, the dump energy of present equipment, promptly determine that by dump energy the mode of operation of system is power saving, portable or sufficient electric weight isotype: for example: when electric weight can be defined as battery saving mode less than 30% the time, being in 30%～70% and being defined as general mode, is sufficient electric weight pattern more than 70%.Preferably, when equipment electric weight deficiency and the requirement of user's appointment when higher, be as the criterion with the equipment electric weight of perception.
The present invention is for the multitask decoder processes, at first decoder is divided into a plurality of subtasks by functional module, then each Task Distribution is handled in different TU task unit 232, each TU task unit is operated in the operating frequency that is calculated by frequency control unit 22.After decoder multitask division unit 231 is divided, directly handle, reduce the scheduling between the TU task unit in decode procedure by each task.Frequency control unit 22 has a plurality of outputs, and output is connected to 232 tasks 1 ..., the input of n.
The parallel multitasking of video decode can be carried out co-operation between image sets, sheet slice, macro block MB and each processing module.
One frame decoding data can comprise one or more chips of separating, for separating between the chip slice, can be relatively independent between the chip slice owing to separate, and so can carry out parallel decoding.
The present invention includes, the chip level multitask decode operation that walks abreast, frame decoding data can be decoded by a plurality of slice, and every slice comprises a plurality of macro block MB, and the macroblock number of every slice is fixing in the piece image.
Described multitask decoder 23 is used for utilizing a plurality of task modules 232, or multithreading, video code flow is carried out in the process of decoding processing, adopts the decoding of parallel mode carries out image; Described multinuclear decoder 23 adopts parallel mode to each sheet carries out image decoding, for a two field picture, carries out parallel decoding at a plurality of slice in this frame simultaneously.
Among the present invention, multitask decoder 23 adopts parallel mode to carry out in the handling process of these modules.After code stream is handled through multitask decoder 23, export corresponding reconstructed video storage district to; After treating whole frame decoding and handling, export display device then to according to section order and macro block order rearrangement again.
Because a frame is made up of a plurality of sections, the frame of decoding is equivalent to a plurality of sections of decoding, for a plurality of sections of decoding, can think a plurality of decoding task.
With each functional unit of decoder,, regard different TU task units as according to its processing speed difference.Each TU task unit is readjusted the processing frequency according to its processing speed then.For example, the loop filtering unit, it is long to occupy decode time, therefore distributes high-frequency, the inverse discrete cosine transformation unit, it is short to take decode time, therefore distributes low frequency.
Described multitask decoder 23, comprise a plurality of decoding task unit 232, each decoding task unit 232 comprises whole processing modules of existing video decode, comprises the modules such as entropy decoder module 100, inverse discrete cosine transformation (IDCT) module 102, deblocking filtering module 104, Intra (in the frame) prediction module 110 and Inter (interframe) prediction module 112 among Fig. 1.
As shown in Figure 3, a plurality of decoding task of the present invention unit (Fig. 2) 232 are described in detail in detail.Comprise: frequency control unit 300, entropy decoding control unit 302, inverse transformation inverse quantization unit 303, Intra predicting unit 304, Inter predicting unit 305, deblocking filtering unit 306.
For each TU task unit of decoding, because each module has correlation to the processing of macro block, so can adopt the method for each module parallel pipelining process to the processing of each macro block.And can according to demand and become original concrete the division to the division of streamline.
Because each time of implementation of these stream treatment unit is different, what have takes a long time, what have needs little time, after previous macro block is handled, then the processing unit of a macro block makes previous processing unit be in temporary transient idle condition because the time of implementation is slower, so relatively wastes resource, so the present invention adopts dynamic frequency to regulate the execution frequency of each processing unit, make each processing unit all finish processing simultaneously to macro block.
The dynamic frequency control method that the invention provides:
The available horsepower of first step awareness apparatus is adjusted the highest point of decoder thus and is managed frequency.After device resource perception unit 21 perceives the available horsepower P of current device, each task 232 that 23 li of multitask Video Decoders comprise is distributed its suitable power, because the number of macroblocks that each slice comprises is different, can number of macroblocks as the foundation of distributing.Comprise the many more power of distribution of number of macroblocks, the distribution less power that number of macroblocks is few.Just: current have a n task, and the number of macroblocks that each task comprises is defined as: m
1, m
2..., m
n, then the power of each Task Distribution is:
Wherein: P
iBe i the power that task is distributed, m
iBe i the number of macroblocks that task comprises.
It is benchmark that second step was handled frequency for each macro block with maximum, regulates the clock frequency of each processing module.The maximum acquisition of handling frequency:, can obtain the available horsepower P of each task according to top step
i, the maximum that can further obtain each task by (1) formula is handled frequency so
As a kind of embodiment, because each module adopts different algorithms, have the different processing times, the bottleneck that influences speed on parallel pipeline is the slowest that module and task, therefore, preferably, to the slowest module of processing speed on the parallel pipeline, with its processing Frequency Distribution is highest point reason frequency, adjusts the clock frequency of other module then as benchmark with it.
According to each module test statistics of running time on different platform, can obtain the processing time ratio of each module of each macro block on different platform streamline of following time, get the longest module running time, this module is decided to be reference frequency, other module is followed this module ratio of running time running time, is designated as τ
i, as basis.For example: Fig. 4 is an example, and decoder is divided into 4 grades of flowing water, is respectively: entropy decoding, inverse transformation, Inter predict (Intra prediction) and filtering.Generally, in each module of decoder, the loop filtering module is the longest running time, and the then calculating of reference frequency can the loop filtering module be the contrast foundation.On the other hand, if, quickened the loop filtering module, make other module to become module the most consuming time that then the entropy decoder module is a basis as the entropy decoder module by some technology.
The processing time ratio that (as DSP, but is not limited to the DSP platform) according to test statistics flowing water at different levels under a platform is: τ
1, τ
2, τ
3, τ
4, represent entropy decoding respectively, inverse transformation, Inter prediction, Intra prediction module are with respect to ratio running time of filtration module.Then the processing frequency with filtering is decided to be the highest processing frequency, is defined as: f
Max, then can regulate the processing frequency of other module according to this frequency, as: the frequency of entropy decoding then is: f
Vlc=τ
1F
Max, the processing frequency of inverse transformation is: f
Idct=τ
2F
Max, the processing frequency of Inter prediction is: f
Mc=τ
3F
Max, the processing frequency of Intra prediction is: f
Ip=τ
4F
Max
About to f
MaxAnd τ
kF
MaxAgreement: adjustable arbitrarily as device (comprising terminal or the chip) operating frequency that can provide in calculation process, f then
MaxAnd τ
kF
MaxIt directly is result calculated; On the other hand, consider that the adjustable extent of the operating frequency that can provide not necessarily changes continuously, for example provide the available work frequency to be [f for a part of device (comprising terminal or chip)
1, f
2, f
3, f
4, f
5, f
6, f
7, f
8] or [f
1, f
2...] etc., so for f
MaxAnd τ
kF
MaxValue, in the adjustable operating frequency range that can provide for this device, near f
MaxAnd τ
kF
MaxFrequency values.
Like this, after just can obtaining the available horsepower of equipment by perception, dynamically adjust the processing frequency of each module of each macro block, the processing time that can guarantee each module like this is essentially identical, like this, streamline can carry out smoothly, does not need on the streamline to wait for, can be connected well.Simultaneously, the maximum running frequency of guaranteeing entire equipment is f
Max, and do not reduce under the situation of decoding speed guaranteeing, the processing frequency of each module of dynamic adjustments can avoid on the streamline some module operation too fast, and needs to wait for and other slower module can greatly reduce power consumption like this.
Those skilled in the art can also carry out various modifications to above content under the condition that does not break away from the definite the spirit and scope of the present invention of claims.Therefore scope of the present invention is not limited in above explanation, but determine by the scope of claims.
Claims (14)
1. a video decoder is characterized in that, comprising: device resource perception unit, frequency control unit, and multitask decoder;
Device resource perception unit is used for determining current available horsepower;
Frequency control unit, the current available horsepower that is used for determining according to device resource perception unit is each task assignment operating frequency;
The multitask decoder is used for video code flow is divided into a plurality of tasks, and is the operating frequency of each task institute assignment each task of decoding according to frequency control unit.
2. video decoder as claimed in claim 1, it is characterized in that, also comprise the reconstruction video memory block, be used to receive the output of multitask decoder, and after each task decoding of present frame is finished in video code flow, after the order rearrangement according to each task video flowing is exported.
3. video decoder as claimed in claim 1 is characterized in that, device resource perception unit also is used for the operating state of awareness apparatus.
4. video decoder as claimed in claim 1 is characterized in that, the multitask decoder comprises decoder multitask division unit and a plurality of decoding task unit;
Decoder multitask division unit is used for video code flow is divided into a plurality of chips of separating;
The decoding task unit is used for decoding to respectively separating chip.
5. video decoder as claimed in claim 4 is characterized in that, the decoding task unit comprises: entropy decoding control unit, inverse transformation inverse quantization unit, inter prediction unit, intraprediction unit, and deblocking filtering unit.
6. video decoder as claimed in claim 5 is characterized in that, frequency control unit is determined the operating frequency respectively separate chip according to following formula:
Wherein: V is the supply power voltage of circuit, f
CLKBe i operating frequency of separating chip, C
EFFBe effective switch-capacitor of circuit, P is current available horsepower, and n is a sum of separating chip, P
iBe i and separate the power that chip distributes, m
iBe i and separate the number of macroblocks that chip comprises, i, j are natural number, 1≤i≤n, and 1≤j≤n, a are activity factor.
7. video decoder as claimed in claim 6 is characterized in that, in i the decoding task unit: the operating frequency of entropy decoding control unit is τ
1F
CLK, the operating frequency of inverse transformation inverse quantization unit is τ
2F
CLK, the operating frequency τ of inter prediction unit
3F
CLK, the operating frequency of intraprediction unit is τ
4F
CLK, the operating frequency of unit, deblocking filtering unit is τ
5F
CLKWherein: τ
1, τ
2, τ
3, τ
4And τ
5For processing time of entropy decoding control unit, inverse transformation inverse quantization unit, inter prediction unit, intraprediction unit and deblocking filtering unit with respect to the decode ratio in processing time of control unit or inverse transformation inverse quantization unit or inter prediction unit or intraprediction unit or deblocking filtering unit of entropy; I decoding task unit is i decoding task unit of separating chip of decoding.
8. a video encoding/decoding method is characterized in that, comprising:
Step 1 is determined current available horsepower;
Step 2 is divided into a plurality of tasks with video code flow, is each task assignment operating frequency according to current available horsepower;
Step 3 is according to each task of decoding for the operating frequency of each task institute assignment.
9. video encoding/decoding method as claimed in claim 8, it is characterized in that, also comprise step 4, the reconstruction video memory block receives the output of multitask decoder, and after each task decoding of present frame is finished in video code flow, after the order rearrangement according to each task video flowing is exported.
10. video encoding/decoding method as claimed in claim 8 is characterized in that, in the step 1, goes back the operating state of awareness apparatus.
11. video encoding/decoding method as claimed in claim 8 is characterized in that, step 2 comprises:
Step 21 is divided into a plurality of chips of separating with video code flow;
Step 22 is according to formula
Obtain P
i
Step 23 is according to formula P
i=aV
2F
CLKC
EFFObtain f
CLK
Wherein: V is the supply power voltage of circuit, f
CLKBe i operating frequency of separating chip, C
EFFBe effective switch-capacitor of circuit, P is current available horsepower, and n is a sum of separating chip, P
iBe i and separate the power that chip distributes, m
iBe i and separate the number of macroblocks that chip comprises, i, j are natural number, 1≤i≤n, and 1≤j≤n, a are activity factor.
12. video encoding/decoding method as claimed in claim 11 is characterized in that, in the step 3, according to each task of decoding for the operating frequency of each task institute assignment.
13. video encoding/decoding method as claimed in claim 12 is characterized in that, the decoding task unit comprises: entropy decoding control unit, inverse transformation inverse quantization unit, inter prediction unit, intraprediction unit, and deblocking filtering unit.
14. video encoding/decoding method as claimed in claim 13 is characterized in that, in the step 2: in i decoding task unit: the decode operating frequency of control unit of entropy is appointed as τ
1F
CLK, the operating frequency of inverse transformation inverse quantization unit is appointed as τ
2F
CLK, the operating frequency of inter prediction unit is appointed as τ
3F
CLK, the operating frequency of intraprediction unit is appointed as τ
4F
CLK, the operating frequency of unit, deblocking filtering unit is τ
5F
CLKWherein: τ
1, τ
2, τ
3, τ
4And τ
5For processing time of entropy decoding control unit, inverse transformation inverse quantization unit, inter prediction unit, intraprediction unit and deblocking filtering unit with respect to the decode ratio in processing time of control unit or inverse transformation inverse quantization unit or inter prediction unit or intraprediction unit or deblocking filtering unit of entropy; I decoding task unit is i decoding task unit of separating chip of decoding.
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| CN103246499A (en) * | 2013-05-28 | 2013-08-14 | 西安电子科技大学 | Device and method for parallelly processing images |
| CN104994389A (en) * | 2015-05-29 | 2015-10-21 | 常州北大众志网络计算机有限公司 | Implementation method of low power consumption decoder for special video encoding unit |
| CN105580366A (en) * | 2013-07-19 | 2016-05-11 | 法国布雷维茨公司 | Method of adaptive broadcasting of multimedia streams by using an energy index |
| CN105955823A (en) * | 2016-04-21 | 2016-09-21 | 深圳市万普拉斯科技有限公司 | Method and system for determining operation frequency of computing resource |
| CN105992005A (en) * | 2015-03-04 | 2016-10-05 | 广州市动景计算机科技有限公司 | Video decoding method and device and terminal device |
| CN106162185A (en) * | 2012-01-20 | 2016-11-23 | 索尼公司 | Chroma Quantization Parameter Extension |
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