CN101466037A - Method for implementing video decoder combining software and hardware - Google Patents
Method for implementing video decoder combining software and hardware Download PDFInfo
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- CN101466037A CN101466037A CN 200710303732 CN200710303732A CN101466037A CN 101466037 A CN101466037 A CN 101466037A CN 200710303732 CN200710303732 CN 200710303732 CN 200710303732 A CN200710303732 A CN 200710303732A CN 101466037 A CN101466037 A CN 101466037A
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Abstract
The invention belongs to the technical field of digital video encoding and decoding. The proposed realizing scheme of a software-hardware matched video decoder mainly comprises the following contents: source code stream is resolved into a plurality of segments by taking a start code as a mark by a code stream pretreatment function block and the source code stream is stored in a specific structure; the video decoder comprises image-level resolution and band-level decoding which are processed by different methods; wherein, the image-level resolution utilizes software processing (hardware acceleration can be considered to use at the same time for different applications) and the band-level decoding utilizes hardware processing; the software is responsible for complex and changeful processing such as scheduling, error correction and the like; the hardware is responsible for the processing with large calculation quantity such as decoding, and the like; the software and hardware cooperate to work and process data in a parallel manner. Under the premise of ensuring the entire performance, the video decoder reduces the complexity of the hardware design and enhances the realizing flexibility, thus leading the design to be capable of being applied to different video decoders; besides, the parallel processing of the software and hardware provides the probability for realizing a high-definition decoder under lower requirements for a system.
Description
Technical field
The present invention relates to a kind of method of digital video decoding technical field, specifically is a kind of whole implementation that is used for the Video Decoder design.
Background technology
Along with the formulation in succession of video compression standard, the application of Video Codec is increasingly extensive, has related to numerous areas such as broadcasting, communication, TV, amusement at present.AVS is as the autonomous second generation digital audio/video information source standard of formulating of China, and its code efficiency is suitable with international standard MPEG-4/H.264, because of it has state-owned intellectual property, is carried out energetically.
Along with the industrialization gradually of many new standards, Digital Television also begins to begin transition by SD to accurate high definition, high definition gradually.For realizing the real-time decoding of HD video, generally adopt integrated circuit (IC) design to realize.But new compression standard, as H.264, the AVS scheduling algorithm, introduce multinomial new technology, when realizing the high-quality picture, also brought higher computational complexity.Realize that its operand is excessive, is difficult to realize with regard to present CPU if depend merely on software.If only realize by hardware, for requirements such as the needed high error correction of practical application, high-performance, high image quality, hardware designs is complicated and be difficult to realize.So, in order to satisfy the requirement of decoding efficiency and flexibility aspect, certainly will require software, hardware system to cooperate, finish decoding task jointly.
Existing software and hardware cooperates is more common in dual mode.
A kind of is that software encapsulation, hardware are realized, its essence still belongs to hardware and realizes, just provides some APIs functions so that use to application.Its shortcoming not only is hard-wired complexity, also is the dependence to video protocols, but the reuse reduction is unfavorable for the realization of many standards.
Another kind of mode is the parsing that software has participated in all syntactic elements, and decoding function piece (as: modules such as inverse quantization, inverse transformation, prediction) is realized by hardware.Though this mode has reduced the complexity of hardware, improved the flexibility that realizes, for high-definition image, the increase severely increase of mutual time of hardware and software of being caused of data volume certainly will increase the weight of the burden of CPU.This realization mostly needs special-purpose CPU to cooperate decoding, certainly will increase the complexity and the cost of system like this.
Summary of the invention
The present invention overcomes the deficiency in above-mentioned two kinds of methods for designing, proposes a kind of implementation that is used for the Video Decoder design, reduces the complexity of hardware designs part, strengthens the flexibility of design, and improves the operational efficiency of decoder.
The technical solution used in the present invention has comprised code stream preprocessing function piece, image level analytical capabilities piece, slice level decoding function piece (be called slice level decoding function piece herein and be meant that the highest level information of the data of handling is the slice header) and software control functional block, as shown in Figure 1, wherein:
Described code stream preprocessing function piece, input code flow is carried out decapsulation according to corresponding format to be handled, serve as a mark with initial code simultaneously code stream is resolved into different segmentations, and store with organizational forms such as chained lists, search needed code stream information for the ease of software, the initial code value of gained in the code stream preprocessing process, position and other the relevant supplementarys that initial code occurs are stored separately with forms such as formations, and be associated with information such as pointers with the code stream segmental structure.
Described image level analytical capabilities piece is resolved the image level information of video protocols defined, decodes to slice level decoding function piece data passes afterwards when running into first slice.Described image level analytical capabilities piece adopts software to resolve, but also can resolve by using corresponding hardware-accelerated unit matching, improves decoding efficiency.
Described slice level decoding function piece passes to this module when image level analytical capabilities piece is decoded to first slice, this module is responsible for slice, macro block are resolved, and afterwards residual error is decoded, and finishes picture decoding, reconstruction according to different standards.This partial arithmetic amount is very big, adopts hardware to handle.
Described software control functional block, finish the task of error analysis, mistake recovery processing and transmitting control commands, coordinate the collaborative work of described image level analytical capabilities piece and slice level decoding function piece, scheduling hypograph level analytical capabilities piece and slice level decoding function piece all can be independently, the operation that walks abreast.
Described image level analytical capabilities piece is finished the correction process of the parameter of image level, owing to adopt software to realize, therefore can select more flexible complicated algorithm for use; Because slice level decoding function piece begins to resolve rather than common macro-block level from the slice one-level, therefore hardware also can be realized some simple wrong recoveries, hardware can adopt some masking algorithms when irrecoverable error occurring, searches next slice original position and continues decoding.
(as MPEG2, H.264, AVS etc.) all has the slice rank because most of commonly used video encoding and decoding standard, so with slice as the division of software and hardware applicable to multiple standards, but the actual slice head that is not limited to, can formulate flexibly according to the regulation of institute's adaptive video agreement, all can with the orientable unit with initial code of minimum.
Described image level analytical capabilities piece and slice level decoding function piece are divided with image slice, (comprise sequence head information, picture header information, extension header information or the like syntactic element) on the slice rank and belong to image level analytical capabilities piece; (comprise slice header, macro block header, irregular information or the like syntactic element) on the slice rank and belong to slice level decoding function piece;
The workflow of Video Decoder of the present invention is as follows, as shown in Figure 3:
At first, code stream preprocessing function piece carries out the detection of initial code when input code flow is carried out decapsulation, and serves as a mark with initial code code stream segmentation and supplementary are stored, and is convenient to software and searches needed code stream information.
Then, the software control functional block starts image level analytical capabilities piece, and image level analytical capabilities piece is finished the parsing of syntactic elements such as sequence head information, picture header information, extension header information, and the mistake that may occur is handled and recovered.
Then, the software control functional block is according to the information that obtains from image level analytical capabilities piece, and whether decision starts picture decoding, if start, then calls slice level decoding function piece and decodes.The initial code locating information that provides according to code stream preprocessing function piece finds the position of next initial code simultaneously, starts image level analytical capabilities piece and resolves the information of piece image down.
At last, after slice level decoding function piece is finished decoding task, the software control functional block is responsible for decoded picture is delivered to display device, and the data that image level analytical capabilities piece has been resolved down piece image is passed to slice level decoding function piece carry out the decoding of second two field picture.
From above-mentioned flow process as can be seen, after definite software is finished specific parsing work, just can dispatch hardware and begin to decode, software can begin the parsing of piece image down simultaneously, and the decoding of current image date hardware just can be carried out simultaneously with the next frame image analysis like this.
The error analysis of described software control functional block/mistake is recovered to handle with described slice level decoding function piece and is carried out synchronously, and software sends command adapted thereto to control the behavior of described slice level decoding function piece according to error analysis.Be illustrated in figure 4 as the state diagram of software control functional block, wherein order 1 to be the order of sending to image level analytical capabilities piece, order 2 is the orders of sending to slice level decoding function piece, and order 2 has polytypes such as decoding/frame-skipping/restart.
The mode that the present invention uses software and hardware to cooperatively interact realizes that software and hardware are independently of one another, parallel processing, and hardware submits to software control, scheduling.Decode procedure can be implemented in the continuous productive process (as shown in Figure 2) on the image level.
The present invention as the point of dividing the decoding function piece, has considered that the above code stream information of slice level is relevant with image mostly with the slice head, handles complexity, and can use complicated error correction, realizes more strong functions.And resolve the information decision that obtains according to image level and whether carry out picture decoding, under the situation that big error code occurs, do not decode, can effectively reduce system burden like this and improve display effect.Use the hardware decoding for the image data information of slice level, can make full use of hard-wired advantage, improve the efficient of decoding.
Code stream preprocessing function piece proposed by the invention has been realized separating between initial code section and the section, guarantees in the position of the above initial code of the next image level of present image decoding prelocalization, for the image level flowing water of realizing decoding provides condition.As can be seen from Figure 2, the decoding efficiency that the present invention can reach will only be controlled by the hardware decoding speed, provide the bigger time to reserve thereby realize error correction for software, promote decoding efficiency greatly, strengthen error correcting capability, therefore had significant advantage and technique effect.
Description of drawings
Fig. 1 is a functional block diagram of the present invention;
Fig. 2 is the image level flowing water figure that the present invention realizes;
Fig. 3 is a decoded portion flow chart among the present invention.
Fig. 4 is the state analysis schematic diagram of software control functional block.
Embodiment
The present invention is further detailed explanation below in conjunction with the concrete case of implementing of accompanying drawing and.
When decoding, hardware begins the decoding of next frame picture header information in order to be implemented in, necessarily require the position of the next image head initial code in location (a perhaps rank initial code on the image head) before the hardware decoding, the present invention is by code stream preprocessing function piece, in code stream analyzing (promptly separating packet header), carry out the detection of initial code, for realizing the data high-speed processing, generally adopt the mode of hardware-accelerated realization.As shown in Figure 1, be stored in two different buffer areas by the pretreated data of code stream respectively with the respective secondary supplementary information, data sementation serves as a mark with initial code and stores by the frame mode of chained list, for the ease of of the visit of follow-up functional block to initial code and other supplementarys, position, initial code byte and other information (being used for purposes such as decoding or broadcast) to the data segment of gained in the resolving are stored with the form of formation, and are associated by the data link table of address information with reality.Whole code stream pretreatment process is independent of decoding process.
Decoding process carries out as input with data link table and initial code formation that code stream preprocessing function piece is exported, comprises image level analytical capabilities piece, slice level decoding function piece and software control functional block, and concrete step comprises:
1) with the initial code is the flag decoding header; (image level analytical capabilities piece)
2) parameter that decoding is obtained is carried out the Software correction processing; (software control)
3) repeat 1), 2) until the initial code that searches the next frame image (a perhaps above rank initial code), wait for hardware;
4) after hardware is finished last decoding task,, then begin new decoding if new decodes commands is arranged; Otherwise wait command.
5) after hardware begins to decode present image, get back to 1); (slice level decoding function piece)
Below above-mentioned steps is done auxiliary explanation.
As main line, in the order that meets the new initial code decoding of transmission under the situation of certain condition or the order of picture decoding, the recipient of two kinds of orders is respectively image level analytical capabilities piece and slice level decoding function piece to whole decode procedure with software control.Send the order of first initial code decoding during the decoder initialization by the software control unit, thereafter image level analytical capabilities BOB(beginning of block) fill order, the software control unit waits for that this command execution back that finishes carries out error-correcting parsing and handle, and continues to send next initial code decodes commands and satisfy until condition and send the picture decoding order under faultless situation; After slice level decoding function piece receives the picture decoding order, beginning hardware decoding, this moment, the software control unit need not to wait for that the hardware decoding finishes can send next initial code decodes commands.
The condition of above-mentioned transmission picture decoding order is: image level analytical capabilities piece has been finished the decoding of next image head or the above header structure of image level.
From said process as can be seen, image level analytical capabilities piece and software control unit are in the serial relation, can include in the software control process, also can use special hardware to carry out.Slice level decoding function piece uses pure hardware mode to realize, has reduced the overhead that whole decode procedure produces alternately owing to software and hardware, and particularly for the code stream of many slice codings, its performance improves particularly evident.But for different video protocols, this division is not unique (for example, if every two field picture has only a slice, then can use software to separate all slice heads).Concerning AVS, because amount of information is few in the slice header structure, and error correcting system is single relatively, therefore realizes its decoding than being easier to hardware, so select with the division points of slice as two functional blocks.
For major part video encoding and decoding standard commonly used (as MPEG2, H.264, AVS etc.) the slice rank is arranged all, so with slice as the division of software and hardware applicable to multiple standards, but the actual slice head that is not limited to, can formulate flexibly according to the regulation of institute's adaptive video agreement, all can with the orientable unit with initial code of minimum.
By above-mentioned explanation as can be seen, the present invention has tangible efficient and improve, and the in good time participation of software makes it obtain compromise in time overhead and flexibility with respect to the implementation of serial decode header and data message.
Above case study on implementation only in order to the explanation the present invention and and unrestricted technical scheme described in the invention, therefore, although this specification has been described in detail the present invention with reference to each above-mentioned embodiment, but those of ordinary skill in the art is to be understood that, still can make amendment or be equal to replacement the present invention, and all do not break away from the technical scheme and the improvement thereof of the spirit and scope of the present invention, all should be encompassed in the middle of the claim scope of the present invention.
Claims (4)
1. the Video Decoder implementation method that cooperates of a software and hardware, comprised code stream preprocessing function piece, image level analytical capabilities piece,
Slice level decoding function piece and software control functional block is characterized in that:
1) described code stream preprocessing function piece carries out decapsulation to input code flow according to corresponding format and handles, and serves as a mark with initial code simultaneously code stream is resolved into each different sections, and the code stream segmentation is stored with organizational forms such as chained lists;
2) described image level analytical capabilities piece and slice level decoding function piece are divided with image slice, belong to image level analytical capabilities piece on the slice rank; Belong to slice level decoding function piece under the slice rank;
3) described image level analytical capabilities piece, image level information to the video protocols defined is resolved, when running into first slice, decode to slice level decoding function piece data passes afterwards, this part adopts software to resolve, but also can resolve, improve decoding efficiency by using corresponding hardware-accelerated unit matching;
4) described slice level decoding function piece, when being decoded to first slice, image level analytical capabilities piece passes to slice level decoding function piece, slice level decoding function piece is responsible for slice, macro block are resolved, afterwards residual error is decoded, and finish picture decoding, reconstruction according to different standards, this part adopts hardware to handle;
5) described software control functional block, finish the task of error analysis, mistake recovery processing and transmitting control commands, coordinate the collaborative work of described image level analytical capabilities piece and slice level decoding function piece, scheduling hypograph level analytical capabilities piece and slice level decoding function piece all can be independently, the operation that walks abreast.
2. the Video Decoder implementation method that a kind of software and hardware as claimed in claim 1 cooperates, it is characterized in that, with the criteria for classifying of slice as software and hardware, but be not limited to the slice head, can formulate flexibly according to the regulation of institute's adaptive video agreement, all can with the orientable unit with initial code of minimum.
3. the Video Decoder implementation method that a kind of software and hardware as claimed in claim 1 cooperates, it is characterized in that, after definite software is finished specific parsing work, just can dispatch hardware and begin decoding, software can begin the parsing of piece image down simultaneously, and the decoding of current image date hardware just can be carried out simultaneously with the next frame image analysis like this, and software and hardware are independently of one another, parallel processing, and hardware submits to software control, scheduling.
4. the Video Decoder implementation method that a kind of software and hardware as claimed in claim 1 cooperates is characterized in that image level analytical capabilities piece is finished the correction process of image level parameter, owing to adopt software to realize, therefore can select more flexible complicated algorithm for use; Because slice level decoding function piece begins to resolve rather than common macro-block level from the slice one-level, therefore hardware also can be realized some simple wrong recoveries, hardware can adopt some masking algorithms when irrecoverable error occurring, searches next slice original position and continues decoding.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103379330A (en) * | 2012-04-26 | 2013-10-30 | 展讯通信（上海）有限公司 | Code stream data decoding pretreatment method and decoding method, processor and decoder |
| CN104333764A (en) * | 2013-07-22 | 2015-02-04 | 安凯(广州)微电子技术有限公司 | Multi-channel video playing method and device |
| CN106658174A (en) * | 2016-10-31 | 2017-05-10 | 努比亚技术有限公司 | Video decoding terminal and method |
| CN107277505A (en) * | 2017-05-19 | 2017-10-20 | 北京大学 | The video decoder structures of AVS 2 based on HW/SW Partitioning |
| CN112422983A (en) * | 2020-10-26 | 2021-02-26 | 眸芯科技（上海）有限公司 | Universal multi-core parallel decoder system and application thereof |
-
2007
- 2007-12-21 CN CN 200710303732 patent/CN101466037A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103379330A (en) * | 2012-04-26 | 2013-10-30 | 展讯通信（上海）有限公司 | Code stream data decoding pretreatment method and decoding method, processor and decoder |
| CN104333764A (en) * | 2013-07-22 | 2015-02-04 | 安凯(广州)微电子技术有限公司 | Multi-channel video playing method and device |
| CN104333764B (en) * | 2013-07-22 | 2017-09-29 | 安凯(广州)微电子技术有限公司 | A kind of multi-channel video player method and device |
| CN106658174A (en) * | 2016-10-31 | 2017-05-10 | 努比亚技术有限公司 | Video decoding terminal and method |
| CN107277505A (en) * | 2017-05-19 | 2017-10-20 | 北京大学 | The video decoder structures of AVS 2 based on HW/SW Partitioning |
| CN107277505B (en) * | 2017-05-19 | 2020-06-16 | 北京大学 | AVS-2 video decoder device based on software and hardware partition |
| CN112422983A (en) * | 2020-10-26 | 2021-02-26 | 眸芯科技（上海）有限公司 | Universal multi-core parallel decoder system and application thereof |
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Open date: 20090624 |