CN101464839B - Access buffering mechanism and method - Google Patents
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Abstract
The invention discloses a device for buffering access storage and a method thereof. The method comprises the following steps: an up read channel receives read requests sent by a CPU, caches the read requests meeting buffer operation conditions, and transmits a read request for reading more data, and the read request contains the read address length of the read requests meeting buffer operation conditions; for the read requests not meeting buffer operation conditions, the read requests which do not meet buffer operation conditions are directly transmitted through a down read channel; the down read channel receives the read data return, and returns the read data of the read requests to the CPU after the read data is returned to the cache as the circumstances may require; or the data are directly returned to the CPU. The invention has the advantages that the effective transmission tape width of memory is increased and the access storage delay is reduced.
Description
Technical field
The present invention relates to internal memory control field, particularly relate to a kind of access buffering mechanism and method.
Background technology
The memory standard of main flow is DDR2 internal memory and DDR3 internal memory at present, and DDR wherein refers to Double DataRate, and Double Data Rate promptly transmits two secondary data in each clock period.DDR (makes a general reference DDR2/DDR3 here like this, actual data transfer down together) can work in high frequency of operation, but internal operating frequencies is relatively low owing to the data transmission frequency height of DDR, so adopt a kind of burst transfer mode (BURST) that is called when data transmission.
The burst transfer mode is meant that adjacent memory unit is carried out data transmission manner continuously in delegation, the quantity of transmitting involved storage unit (row) continuously be exactly burst-length (Burst Lengths, BL).In the DDR2 standard, a BL is 4, i.e. a read and write access causes the transmission of 4 data; And in the DDR3 standard, BL increases to 8, i.e. a read and write access causes the transmission of 8 data.Like this, internal storage access for a DDR3, if only need carry out the visit of data, have 7 extraneous data transfer bandwidth wastes, do not take any measure if carry out the low volume data transmission continuously, must cause memory access efficient extremely low, the bandwidth of greatly wasting internal storage access.
On the other hand, after the request of access of DDR is sent, need the processing of some time could be from return data on the internal memory, this also need to postpone to add delay that the processing through Memory Controller Hub self causes etc. in addition.For a typical DDR2/DDR3 Memory Controller Hub, the relatively more normal access delay of read access is about 50ns～150ns and does not wait, and when visit was intensive, this delay might reach about 300ns.
Application number is 200710034577.4 Chinese invention patent application, discloses a kind of reorder memory access way to play for time and device towards flow data.Compare with the present invention, it is by rearranging the order of visit, realizing effectively utilizing the bandwidth of internal storage access, but increased system overhead.
Summary of the invention
The object of the present invention is to provide a kind of access buffering mechanism and method,, reduce memory access and postpone to realize under a stable condition, improving effective bandwidth not changing the Memory Controller Hub self structure with the little expense of trying one's best in the read channel processing procedure.
Be a kind of access buffering mechanism of realizing that purpose of the present invention provides, be arranged on the read channel between CPU and the Memory Controller Hub, and be connected, described access buffering mechanism with write access, comprise: judge module, data memory module, read request forwarding module and read data return module, wherein:
Described judge module is used for the read request that receives according to receiver module, judges whether described read request should be buffered;
Described data memory module is used for the judged result according to described judge module, and the address of reading of the read request that buffer memory should be buffered is returned with the read data of reading address size and sent by described Memory Controller Hub, in different table;
Described read request forwarding module is used for the judged result according to judge module, to meeting the read request of buffer operation condition, transmit one comprise the described read request that meets the buffer operation condition read the more multidata read request of reading of address size;
Described read data returns module, being used to receive the read data that is sent by described Memory Controller Hub returns, and, described read data return cache is returned to CPU behind described data memory module according to the judged result of described judge module, perhaps directly described read data is returned and return to CPU.
Described access buffering mechanism also comprises:
The write request module is used in the address superposed part of reading mark and write request on the address, and will be labeled read the described judge module of address notification, forbid that the address of reading that is labeled accepts read request again.
Described judge module comprises:
The null term discrimination module is used to judge whether described different table exists null term;
The buffer memory judge module is used to judge whether read request meets the buffer memory condition;
Read the matching addresses module, be used for judging that whether described read request hit in the address reading of storing of data memory module.
Described data memory module comprises:
The read request address module is used to safeguard the read request address table, the read request that buffer memory should be buffered read the address;
Read the address size information module, be used for safeguarding and read the address size information table, the read request that buffer memory should be buffered read address size;
Read data returns buffer module, is used to safeguard that read data returns buffer queue, and the read data that buffer memory should be buffered returns.
Described different table can be adjusted wherein item number, the width of list item according to the environment and the behavior of accessing operation.
For realizing purpose of the present invention, a kind of memory access way to play for time also is provided, be used to improve the effective transmission bandwidth of internal memory, described method comprises the following steps:
The up read channel of step 100. is received the read request that CPU sends, according to circumstances, the read request that meets the buffer operation condition is carried out buffer memory, and transmit one comprise the described read request that meets the buffer operation condition read the more multidata read request of reading of address size; To not meeting the read request of buffer operation condition, directly transmit the described read request that does not meet the buffer operation condition by down read channel;
After the described step 200, also comprise the following steps:
Described memory access way to play for time also comprises the following steps:
Step 400. receives at read channel and receives write request on the write access in the read request process that mark and the described address superposed part of reading no longer receive read request hitting this address.
Described step 100 also comprises the following steps:
The up read channel of step 110. is received the read request that CPU sends, and judges whether described read request meets the buffer operation condition, if then execution in step 120; Otherwise, directly transmit described read request by down read channel;
Step 120. judges whether described read request hits in the read request address table, if then execution in step 130; Otherwise, execution in step 140;
Step 130. is appended the address size of reading of described read request in the list item of reading the address size information table of reading the address correspondence of described read request, do not send read request to Memory Controller Hub, and the read data of a wait and a last read request returns in the lump and returns;
Step 140. writes down reading the address and reading address size of described read request respectively at described read request address table and reading in the address size information table, and send one comprise described read request read the more multidata read request of reading of address size.
Described buffer operation condition is to set flexibly according to the behavial factor of chip structure, memory access, includes but not limited to following situation: (1) request length is less than or equal to the BURST length of DDR2/DDR3; (2) request type is a sequential access.
Described step 130 comprises the following steps:
Step 131. judges describedly read whether null term is arranged in the address size information table, if having, then execution in step 132; Otherwise then execution in step 140, and described read request is added in the described read request address table as a new read request;
Step 132. judges whether the described address of reading is marked by write request, if then execution in step 140; Otherwise, execution in step 133;
Step 133. sends read request no longer in addition, only appends the address size of reading of this read request, and the read data of a wait and a last read request returns in the lump and returns.
Described step 140 comprises the following steps:
Step 141. judges in the described read request address table whether still have null term to use, if then execution in step 142; Otherwise, execution in step 143;
Step 142. is the reading the address and read address size to read request address table and reading in the address size information table of the described read request of buffer memory respectively, and send one by down read channel and comprise the described more multidata read request of reading of address size of reading;
Step 143. is directly transmitted described read request by down read channel.
Described address size information table and the described read request address table read according to the behavial factor of chip structure, memory access, can not set different processing modes when having null term in the table flexibly.
Described step 200 comprises the following steps:
Step 210. is judged that read data returns and whether is hit the described address of reading, if then execution in step 220; Otherwise, execution in step 230;
Step 220, with described read data return cache, and according to returning the described information of reading to write down the address size with the described corresponding address size of reading in address of reading from up read channel;
Step 230. is directly returned described read data from up read channel and is returned.
Described step 400 also comprises the following steps:
Step 410. judges whether the address of described write request overlaps with the described address of reading, if then execution in step 420; Otherwise execution in step 430;
Marking in the address of reading that step 420. will overlap with the address of described write request, no longer receives read request and read hitting of address to described;
Step 430. is carried out write operation.
Beneficial effect of the present invention is:
1. can not cause additional delay for the read request that need not through buffering;
2. can not cause additional delay for write request;
3. do not influence the correctness of staggered read-write;
4. the resource overhead that is increased is little, the bigger lifting that brings performance for the read request of hitting in the memory access buffering;
5. need not to revise Memory Controller Hub, can not bring extra modification the read channel write access.
Description of drawings
Fig. 1 is the synoptic diagram of the set-up mode of a kind of access buffering mechanism of the present invention;
Fig. 2 is the structural representation of a kind of access buffering mechanism of the present invention;
Fig. 3 is the process flow diagram of a kind of memory access way to play for time of the present invention;
Fig. 4 is the process flow diagram that receives read request and buffer memory among the present invention;
Fig. 5 receives read data to return the also process flow diagram of buffer memory among the present invention;
Fig. 6 is the process flow diagram of memory access buffering implementation method when receiving write request on the write access among the present invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, a kind of access buffering mechanism of the present invention and method are further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
A kind of access buffering mechanism of the present invention and method, its ultimate principle is, the read request on the cache read passage at first, send the effective bandwidth of not wasting DDR to Memory Controller Hub again than the longer read request of original request length, if before read data returns, there is new request to drop in the relative address of this visit on the read channel, then needn't send read request to Memory Controller Hub again, only need the corresponding information of record, when first read data returns, return corresponding data and get final product.Like this, reduce the waste of DDR bandwidth, reduced the delay of returning of part read request simultaneously, reduced the quantity that receives read-write requests on the Memory Controller Hub, be convenient to the better scheduling of Memory Controller Hub read write command, further improved effective readwrite bandwidth.
Introduce a kind of access buffering mechanism of the present invention in detail below in conjunction with above-mentioned target, Fig. 1 is the synoptic diagram of the set-up mode of a kind of access buffering mechanism of the present invention, Fig. 2 is the structural representation of a kind of access buffering mechanism of the present invention, as shown in Figure 1 and Figure 2, described access buffering mechanism 10, be arranged on the read channel between CPU and the Memory Controller Hub, and be connected with write access, it comprises: judge module 1, data memory module 2, read request forwarding module 3, read data return module 4 and write request module 5, wherein:
Described judge module 1 is used for judging according to the read request that receives whether described read request should be buffered;
Described judge module 1 comprises:
Null term discrimination module 11 is used to judge whether different table exists null term;
Buffer memory judge module 12 is used to judge whether read request meets the buffer memory condition;
Read matching addresses module 13, be used for judging described read request whether data memory module 2 storages read hit in the address;
Described data memory module 2 is used for the judged result according to described judge module 1, and the address of reading of the read request that buffer memory should be buffered is returned with the read data of reading address size and sent by described Memory Controller Hub, in different table;
Described data memory module 2 comprises:
Read request address module 21 is used to safeguard the read request address table, the read request that buffer memory should be buffered read the address;
Read address size information module 22, be used for safeguarding and read the address size information table, the read request that buffer memory should be buffered read address size;
Read data returns buffer module 23, is used to safeguard that read data returns buffer queue, and the read data that buffer memory should be buffered returns.
Preferably, in specific implementation, can be according to the environment and the behavior of accessing operation, the item number of suitable each list item of adjustment, width or the like.
Described read request forwarding module 3 is used for the judged result according to judge module 1, to meeting the read request of buffer operation condition, transmit one comprise the described read request that meets the buffer operation condition read the more multidata read request of reading of address size;
Described read data returns module 4, being used to receive the read data that is sent by Memory Controller Hub returns, and, described read data return cache is returned to CPU behind described data memory module according to the judged result of described judge module, perhaps directly described read data is returned and return to CPU.
Access buffering mechanism of the present invention also comprises:
Write request module 5 is used in the address superposed part of reading mark and write request on the address, and will be labeled read the described judge module of address notification, forbid that the address of reading that is labeled accepts read request again.
Corresponding to a kind of access buffering mechanism of the present invention, a kind of memory access way to play for time also is provided, and Fig. 3 is the process flow diagram of a kind of memory access way to play for time of the present invention, and Fig. 4 is the process flow diagram that receives read request and buffer memory among the present invention, as shown in Figure 3, Figure 4, described method comprises the following steps:
The up read channel of step 100. is received the read request that CPU sends, according to circumstances, the read request that meets the buffer operation condition is carried out buffer memory, and transmit one comprise the described read request that meets the buffer operation condition read the more multidata read request of reading of address size; To not meeting the read request of buffer operation condition, directly transmit the described read request that does not meet the buffer operation condition by down read channel;
The objective of the invention is to improve effective transmission bandwidth of internal memory, in the time only need carrying out accessing operation to low volume data, waste that will some data transfer bandwidth, therefore, the accessing operation that this low volume data is carried out will advanced row cache, and transmit one and comprise the memory access request that reading of described low volume data equals the data of internal memory transmission bandwidth, so just can avoid the waste of data transfer bandwidth; And for those greater than the accessing operation of the data of internal memory transmission bandwidth, then do not need to carry out buffer memory, directly transmit this accessing operation and get final product.
Described step 100 comprises the following steps:
The up read channel of step 110. is received the read request that CPU sends, and judges whether described read request meets the buffer operation condition, if then execution in step 120; Otherwise, directly transmit described read request by down read channel;
Preferably, in specific implementation, described buffer operation condition can be carried out permissive provision according to the factors such as concrete behavior of chip structure, memory access.Include but not limited to following situation: (1) request length is less than or equal to the BURST length of DDR2/DDR3; (2) request type is sequential access or the like.
As a kind of embodiment, the condition of buffer operation described in the present invention is the BURST length that read request length is less than or equal to DDR2/DDR3.
Step 120. judges whether described read request hits in read request address table (reading Address requests module 21), if then execution in step 130; Otherwise, execution in step 140;
For not writing down the read request of reading the address and reading address size, the read request of sending first as CPU, the read request of sending first for CPU, then need to read earlier matching addresses, judge the address accessed mistake whether need reading of data, if accessed mistake does not then need to send read request by access buffering mechanism to Memory Controller Hub again, and only need write down the corresponding address size of reading, wait is returned in the lump with the data that a last read request is returned; Otherwise write down reading the address and reading address size of described read request, and to Memory Controller Hub send one comprise described read request read the more multidata read request of reading of address size.
Step 130. is appended the address size of reading of described read request in the described list item of reading the address size information table of reading the address correspondence, do not send read request to Memory Controller Hub, waits for that read data with a last read request returns in the lump to return;
Described step 130 comprises the following steps:
Step 131. judges describedly read whether null term is arranged in the address size information table, if having, then execution in step 132; Otherwise then execution in step 140, and described read request is added in the described read request address table as a new read request;
Preferably, when specific implementation, the processing mode when table is full also can be different, can take to suspend the method for delivering toward descending read channel when expiring such as the read request address table.The user can carry out permissive provision according to the factors such as concrete behavior of chip structure, memory access.
Step 132. judges whether the described address of reading is marked by write request, if then execution in step 140; Otherwise, execution in step 133;
Step 133. sends read request no longer in addition, only appends the address size of reading of this read request, and the read data of a wait and a last read request returns in the lump and returns.
Step 140. writes down reading the address and reading address size of described read request respectively at described read request address table and reading in the address size information table, and send one comprise described read request read the more multidata read request of reading of address size;
That send first for CPU and meet the read request of buffer operation condition, access buffering mechanism needs advanced row cache, send the original longer visit of read request length, promptly identical read request, and the effective bandwidth of not wasting DDR to Memory Controller Hub again with the bandwidth length of DDR.
Described step 140 comprises the following steps:
Step 141. judges in the described read request address table (reading Address requests module 21) whether still have null term to use, if then execution in step 142; Otherwise, execution in step 143;
Step 142. is the reading the address and read address size to read request address table and reading in the address size information table of the described read request of buffer memory respectively, and send one by down read channel and comprise the described more multidata read request of reading of address size of reading;
As a kind of embodiment, with the DDR3 standard is example, its read and write access causes the transmission of 8 data, suppose that CPU sends first and meet the only transmission of 5 data of needs of read request of buffer operation condition, so, access buffering mechanism sends the read request that reads 8 data that comprises these 5 data to Memory Controller Hub again after the reading the address and read address size of this read request of buffer memory, promptly ask to get 3 data reading on the basis of 5 data of read request originally mutiread again.
Step 143. is directly transmitted described read request by down read channel.
Preferably, when specific implementation, the processing mode when the read request address table is full also can be different.The user can carry out permissive provision according to the factors such as concrete behavior of chip structure, memory access.
In the step 200, receive on the down read channel that read data returns, judge at first that read data returns whether to hit the described address of reading that if hit, then expression is returned corresponding read request with described read data and sent to Memory Controller Hub by access buffering mechanism; If do not hit, represent that then returning corresponding read request with described read data is not pass through the access buffering mechanism buffer memory.
Fig. 5 receives read data to return the also process flow diagram of buffer memory among the present invention, as shown in Figure 5, described step 200 comprises the following steps:
Step 210. is judged that read data returns and whether is hit the described address of reading, if then execution in step 220; Otherwise, execution in step 230;
Step 220, with described read data return cache, and according to returning the described information of reading to write down the address size with the described corresponding address size of reading in address of reading from up read channel;
Step 230. is directly returned described read data from up read channel and is returned.
In order not influence the correctness of read-write order, a kind of memory access way to play for time of the present invention also comprises the following steps:
Step 400. receives at read channel and receives write request on the write access in the read request process that mark and the described address superposed part of reading no longer receive read request hitting this address.
Generally, access buffering mechanism is seen write request on write access, at first the address of described write request and the address set of read request are mated, if the match is successful, then represent the data that read request will read, be written into, do not allow read request to read the data of storing on the described address described address mark this moment.
Fig. 6 is the process flow diagram of memory access buffering implementation method when receiving write request on the write access among the present invention, and as shown in Figure 6, described step 400 also comprises the following steps:
Step 410. judges whether the address of described write request overlaps with the described address of reading, if then execution in step 420; Otherwise execution in step 430;
Marking in the address of reading that step 420. will overlap with the address of described write request, no longer receives read request and read hitting of address to described;
In this step, suppose reading after the address write mark of read request A correspondence, expression all can not reuse the data of being read back by read request A from the later same address read request B of this write request, and the read request C that has hit before the read request A hereto, still normal return data.
Step 430. is carried out write operation.
Preferably,, on a chip, realize that the memory access way to play for time is an example below, a kind of memory access way to play for time of the present invention is elaborated as a kind of embodiment.
In this chip, read-write channel all is based on the AMBA3.0 standard, so wherein read the relevant information records AMBA bus message in the address size information table.
In this chip, read request address list item number is 8, and the read request length that access buffering mechanism sends is 512 bits, and the read request address table only need be preserved 36 ~ 6 of address, whether also have this item of a bit representation effective in each, whether a bit representation is by the write request mark.
It is corresponding with the read request address table to read the address size information table, and item number also is 8, wherein preserves hitting of two read requests at most for every, preserves its read request Data Position, information such as read request serial number.
And read data buffering to return formation be one two formation, each is 512 bits, and is corresponding with the request length that sends out.
In this chip, realize described memory access way to play for time, comprise the following steps:
Step 100 '. up read channel is received the read request that CPU sends, according to circumstances, the read request that meets the buffer operation condition is carried out buffer memory, and transmit one comprise the described read request that meets the buffer operation condition read the more multidata read request of reading of address size; To not meeting the read request of buffer operation condition, directly transmit the described read request that does not meet the buffer operation condition by down read channel;
Step 110 '. up read channel is received the read request that CPU sends, and judges whether described read request meets the buffer operation condition, if, execution in step 120 ' then; Otherwise, directly transmit described read request by down read channel;
Have only in this chip and just be judged as available buffer when satisfying following situation simultaneously: (1) request length is less than or equal to 8; (2) request type is a sequential access; (3) asking length must ask width greater than 1 is 128 bits.
Step 120 '. judge whether described read request hits in the read request address table, if, execution in step 130 ' then; Otherwise, execution in step 140 ';
Step 130 ' in the described list item of reading the address size information table of reading the address correspondence, append the address size of reading of described read request, do not send read request to Memory Controller Hub, wait for that read data with a last read request returns in the lump to return.
Step 131 '. judge whether the described respective items of reading the address size information table of reading the address correspondence does not take two read requests, if do not take, execution in step 132 ' then; Otherwise this read request is not recorded, and directly mails to down read channel and gives Memory Controller Hub;
Step 132 '. judge whether the described address of reading is marked by write request, if, execution in step 140 ' then; Otherwise, execution in step 133 ';
Step 133 '. send read request no longer in addition, only append the address size of reading of this read request, the read data of a wait and a last read request returns in the lump and returns.
Step 140 '. write down reading the address and reading address size of described read request in the address size information table respectively at described read request address table and reading, and send one comprise described read request read the more multidata read request of reading of address size;
Described step 140 ', comprise the following steps:
Step 141 '. judge in the described read request address table whether do not take 8, if do not take, execution in step 142 ' then; Otherwise, execution in step 143 ';
Step 142 '. that writes down described read request reads address and read address size, and sends one by down read channel and comprise the described more multidata read request of reading of address size of reading;
Step 143 '. directly transmit described read request by down read channel.
Step 200 '. down read channel receives that read data returns, and according to circumstances, returns to CPU with behind the described read data return cache read data of wherein said read request being returned; Perhaps direct read data with described read request returns and returns to CPU.
Step 210 '. judge that read data returns and whether hit the described address of reading, if, execution in step 220 ' then; Otherwise, execution in step 230 ';
Step 220 ', with described read data return cache, and according to returning the described information of reading to write down the address size with the described corresponding address size of reading in address of reading from up read channel;
Step 230 '. directly return described read data and return from up read channel.
Step 300 '. with the read data of whole described read requests return return finish after, the read data of removing and describedly read the address, read address size and the described read data that the reads more multidata read request corresponding described read request in returning returns.
Step 400 '. receive at read channel and to receive write request on the write access in the read request process, mark and the described address superposed part of reading no longer receive read request hitting this address.
Step 410 '. whether the address of judging described write request overlaps with the described address of reading, if, execution in step 420 ' then; Otherwise execution in step 430 ';
Step 420 '. marking in the address of reading that will overlap with the address of described write request, no longer receives read request and read hitting of address to described;
Step 430 '. carry out write operation.
Beneficial effect of the present invention is:
1. can not cause additional delay for the read request that need not through buffering;
2. can not cause additional delay for write request;
3. do not influence the correctness of staggered read-write;
4. the resource overhead that is increased is little, the bigger lifting that brings performance for the read request of hitting in the memory access buffering;
5. need not to revise Memory Controller Hub, can not bring extra modification the read channel write access.
In conjunction with the drawings to the description of the specific embodiment of the invention, others of the present invention and feature are conspicuous to those skilled in the art.
More than specific embodiments of the invention are described and illustrate it is exemplary that these embodiment should be considered to it, and be not used in and limit the invention, the present invention should make an explanation according to appended claim.
Claims (14)
1. an access buffering mechanism is arranged on the read channel between CPU and the Memory Controller Hub, and is connected with write access, it is characterized in that, described access buffering mechanism comprises: judge module, data memory module, read request forwarding module and read data return module, wherein:
Described judge module is used for judging according to the read request that receives whether described read request meets the buffer operation condition;
Described data memory module is used for the judged result according to described judge module, and buffer memory meets the address of reading of the read request of buffer operation condition and returns with the read data of reading address size and sent by described Memory Controller Hub, in different table;
Described read request forwarding module, be used for judged result according to judge module, to meeting the read request of buffer operation condition, if in the read request address table, hit, then in the list item of reading the address size information table of reading the address correspondence of described read request, append the address size of reading of described read request, do not send read request to Memory Controller Hub, the read data of a wait and a last read request returns in the lump and returns; Otherwise, write down reading the address and reading address size of described read request in the address size information table respectively at described read request address table and reading, and transmit one comprise the described read request that meets the buffer operation condition read the more multidata read request of reading of address size;
Described read data returns module, being used to receive the read data that is sent by described Memory Controller Hub returns, and, described read data return cache is returned to CPU behind described data memory module according to the judged result of described judge module, perhaps directly described read data is returned and return to CPU.
2. access buffering mechanism according to claim 1 is characterized in that, described access buffering mechanism also comprises:
The write request module is used in the address superposed part of reading mark and write request on the address, and will be labeled read the described judge module of address notification, forbid that the address of reading that is labeled accepts read request again.
3. access buffering mechanism according to claim 1 is characterized in that, described judge module comprises:
The null term discrimination module is used to judge whether described different table exists null term;
The buffer memory judge module is used to judge whether read request meets the buffer memory condition;
Read the matching addresses module, be used for judging that whether described read request hit in the address reading of storing of data memory module.
4. access buffering mechanism according to claim 1 is characterized in that, described data memory module comprises:
The read request address module is used to safeguard the read request address table, buffer memory meet the buffer operation condition read request read the address;
Read the address size information module, be used for safeguarding and read the address size information table, buffer memory meet the buffer operation condition read request read address size;
Read data returns buffer module, is used to safeguard that read data returns buffer queue, and the read data that buffer memory meets the buffer operation condition returns.
5. access buffering mechanism according to claim 4 is characterized in that, described different table according to the environment and the behavior of accessing operation, is adjusted item number, the width of list item in the described different table.
6. a memory access way to play for time is used to improve the effective transmission bandwidth of internal memory, it is characterized in that described method comprises the following steps:
The up read channel of step 100. is received the read request that CPU sends, and the read request that meets the buffer operation condition is carried out buffer memory, and transmit one comprise the described read request that meets the buffer operation condition read the more multidata read request of reading of address size; To not meeting the read request of buffer operation condition, directly transmit the described read request that does not meet the buffer operation condition by down read channel;
Described step 100 comprises the following steps:
The up read channel of step 110. is received the read request that CPU sends, and judges whether described read request meets the buffer operation condition, if then execution in step 120; Otherwise, directly transmit described read request by down read channel;
Step 120. judges whether described read request hits in the read request address table, if then execution in step 130; Otherwise, execution in step 140;
Step 130. is appended the address size of reading of described read request in the list item of reading the address size information table of reading the address correspondence of described read request, do not send read request to Memory Controller Hub, and the read data of a wait and a last read request returns in the lump and returns;
Step 140. writes down reading the address and reading address size of described read request respectively at described read request address table and reading in the address size information table, and send one comprise described read request read the more multidata read request of reading of address size;
Step 200. down read channel receives that read data returns, and according to circumstances, the read data of the read request behind the described read data return cache wherein said CPU sent is returned return to CPU; Perhaps directly described read data is returned and return to CPU.
7. memory access way to play for time according to claim 6 is characterized in that, after the described step 200, also comprises the following steps:
The read data of whole read requests that step 300. is sent CPU return return finish after, the read data of reading the read request that address size and the described read data that the reads more multidata read request corresponding CPU in returning sends of reading whole read requests of address, CPU sending of removing whole read requests that CPU sends returns.
8. memory access way to play for time according to claim 6 is characterized in that, described memory access way to play for time also comprises the following steps:
Step 400. receives at read channel and receives write request on the write access in the read request process that mark and the described address superposed part of reading no longer receive read request hitting this address.
9. memory access way to play for time according to claim 6 is characterized in that, described buffer operation condition is to set flexibly according to the behavial factor of chip structure, memory access.
10. memory access way to play for time according to claim 8 is characterized in that described step 130 comprises the following steps:
Step 131. judges describedly read whether null term is arranged in the address size information table, if having, then execution in step 132; Otherwise then execution in step 140, and described read request is added in the described read request address table as a new read request;
Step 132. judges whether the described address of reading is marked by write request, if then execution in step 140; Otherwise, execution in step 133;
Step 133. sends read request no longer in addition, only appends the address size of reading of this read request, and the read data of a wait and a last read request returns in the lump and returns.
11. memory access way to play for time according to claim 6 is characterized in that described step 140 comprises the following steps:
Step 141. judges in the described read request address table whether still have null term to use, if then execution in step 142; Otherwise, execution in step 143;
Step 142. is the reading the address and read address size to read request address table and reading in the address size information table of the described read request of buffer memory respectively, and send one by down read channel and comprise the described more multidata read request of reading of address size of reading;
Step 143. is directly transmitted described read request by down read channel.
12. according to claim 10 or 11 described memory access ways to play for time, it is characterized in that, described address size information table and the described read request address table read according to the behavial factor of chip structure, memory access, can not set different processing modes when having null term in the table flexibly.
13. memory access way to play for time according to claim 6 is characterized in that described step 200 comprises the following steps:
Step 210. is judged that read data returns and whether is hit the described address of reading, if then execution in step 220; Otherwise, execution in step 230;
Step 220, with described read data return cache, and according to returning the described information of reading to write down the address size with the described corresponding address size of reading in address of reading from up read channel;
Step 230. is directly returned described read data from up read channel and is returned.
14. memory access way to play for time according to claim 8 is characterized in that described step 400 also comprises the following steps:
Step 410. judges whether the address of described write request overlaps with the described address of reading, if then execution in step 420; Otherwise execution in step 430;
Marking in the address of reading that step 420. will overlap with the address of described write request, no longer receives read request and read hitting of address to described;
Step 430. is carried out write operation.
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| CN115454502B (en) * | 2022-09-02 | 2023-06-02 | 杭州登临瀚海科技有限公司 | Method for scheduling return data of SIMT architecture processor and corresponding processor |
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