CN101449311A

CN101449311A - Method and system for light emitting device displays

Info

Publication number: CN101449311A
Application number: CNA200780013047XA
Authority: CN
Inventors: 阿罗基亚·内森; G·雷扎·查吉
Original assignee: Ignis Innovation Inc
Current assignee: Ignis Innovation Inc
Priority date: 2006-02-10
Filing date: 2007-02-09
Publication date: 2009-06-03
Anticipated expiration: 2027-02-09
Also published as: CA2536398A1; CN101449311B; CA2541347A1

Abstract

The present invention provides a method and system for light emitting device displays. The system includes one or more pixels, each having a light emitting device, a drive transistor for driving the light emitting device, and a switch transistor for selecting the pixel; and a circuit for monitoring and extracting the change of the pixel to calibrate programming data for the pixel. Programming data is calibrated using the monitoring result.

Description

The method and system that is used for light emitting device display

Technical field

The present invention relates to display technique, more specifically relate to method and system about light emitting device display.

Background technology

Electroluminescent display is widely used in such as various devices such as cell phones.Particularly, utilize amorphous silicon (a-Si), polysilicon, organic or other drive active matrix organic light-emitting diode (AMOLED) display of backboards, because, respectively advantage such as rate height and width visual angle lower, and the more attractive that becomes such as practicable flexible demonstration, manufacturing cost.

The AMOLED display comprise multiple lines and multiple rows pixel array, each pixel has Organic Light Emitting Diode (OLED) and is arranged in back plane electronics in the column array.Because OLED is a current driving apparatus, so the image element circuit of AMOLED should be able to provide accurate and constant drive current.

A kind of method and system that constant luminance can be provided accurately need be provided.

Summary of the invention

The purpose of this invention is to provide the method and system that to avoid or to eliminate at least one shortcoming of existing system.

According to an aspect of the present invention, provide a kind of display system that comprises one or more pixels.Each pixel comprises light-emitting device, be used to the switching transistor that drives the driving transistors of this light-emitting device and be used to select this pixel.This display system comprises and is used for monitoring and extracts (extract) pixel and change circuit with the programming data of calibrating this pixel.

According to a further aspect in the invention, provide a kind of method that drives display system.This display system comprises one or more pixels.This method may further comprise the steps: at extracting cycle (extraction cycle), operation signal is provided, monitors node, wearing out based on supervision result extraction (extract) pixel in this pixel to pixel; And, come programming data is calibrated and provided programming data to this pixel based on extraction to pixel ageing in programming cycle.

Description of drawings

By the description of having done below with reference to accompanying drawing, these and other features of the present invention will become more obvious, in the accompanying drawing:

Fig. 1 shows the example of suitably having used according to the pel array of the image element circuit with 2 transistors (2T) of the pixel operation technology of the embodiment of the invention;

Fig. 2 shows another example of the pel array with 2T image element circuit of suitably having used the pixel operation technology relevant with Fig. 1;

Fig. 3 A shows the example of the signal waveform of the image element circuit that is applied to Fig. 1 and 2 in extracting operation (extraction operation);

Fig. 3 B shows the example of the signal waveform of the image element circuit that is applied to Fig. 1 and 2 in normal running;

Fig. 4 show driving transistors in the extracting cycle of Fig. 3 A threshold voltage depart from influence to the voltage of VDD;

Fig. 5 shows the example of the display system of the pel array with Fig. 1 or 2;

Fig. 6 shows the example of the normal and extracting cycle of the pel array that is used to drive Fig. 5;

Fig. 7 shows and has suitably used the example of 3 transistors (3T) image element circuit of pixel operation technology according to another embodiment of the present invention;

Fig. 8 shows another example of the 3T image element circuit of suitably having used the pixel operation technology relevant with Fig. 7;

Fig. 9 A shows the example of the signal waveform of the image element circuit that is applied to Fig. 7 and 8 in extracting operation;

Fig. 9 B shows the example of the signal waveform of the image element circuit that is applied to Fig. 7 and 8 in normal running;

Figure 10 shows the example of the display system of the image element circuit with Fig. 7 or 8;

Figure 11 A shows the example of the normal and extracting cycle of the pel array that is used to drive Figure 10;

Figure 11 B shows another example of the normal and extracting cycle of the pel array that is used to drive Figure 10;

Figure 12 shows another example of the display system of the image element circuit with Fig. 7 or 8;

Figure 13 shows the example of the normal and extracting cycle of the pel array that is used to drive Figure 12;

Figure 14 shows the example of 4 transistors (4T) image element circuit of suitably having used pixel operation technology according to still another embodiment of the invention;

Figure 15 shows another example of the 4T image element circuit of suitably having used the pixel operation technology relevant with Figure 14;

Figure 16 A shows the example of the signal waveform of the image element circuit that is applied to Figure 14 and 15 in extracting operation;

Figure 16 B shows the example of the signal waveform of the image element circuit that is applied to Figure 14 and 15 in normal running;

Figure 17 shows the example of the display system of the image element circuit with Figure 14 or 15;

Figure 18 shows the example of the normal and extracting cycle of the pel array that is used to drive Figure 17;

Figure 19 shows another example of the display system of the image element circuit with Figure 14 or 15;

Figure 20 shows the example of the normal and extracting cycle of the pel array that is used to drive Figure 19;

Figure 21 shows the example of the 3T image element circuit of suitably having used pixel operation technology according to still another embodiment of the invention;

Figure 22 shows another example of the 3T image element circuit of suitably having used the pixel operation technology relevant with Figure 21;

Figure 23 A shows the example of the signal waveform of the image element circuit that is applied to Figure 21 and 22 in extracting operation;

Figure 23 B shows the example of the signal waveform of the image element circuit that is applied to Figure 21 and 22 in normal running;

Figure 24 shows the example of the display system of the image element circuit with Figure 21 or 22;

Figure 25 A shows the example of the normal and extracting cycle of the pel array that is used to drive Figure 24;

Figure 25 B shows another example of the normal and extracting cycle of the pel array that is used to drive Figure 24;

Figure 26 shows the example of suitably having used according to the 3T image element circuit of the pixel operation technology of further embodiment of this invention;

Figure 27 shows another example of the 3T image element circuit of suitably having used the pixel operation technology relevant with Figure 26;

Figure 28 A shows the example of the signal waveform of the image element circuit that is applied to Figure 26 and 27 in extracting operation;

Figure 28 B shows the example of the signal waveform of the image element circuit that is applied to Figure 26 and 27 in normal running;

Figure 29 shows the example of the display system of the image element circuit with Figure 26 or 27;

Figure 30 illustrates the example of the normal and extracting cycle of the pel array that is used to drive Figure 29;

Figure 31 A shows image element circuit capable at j and that the i row have readout capacity;

Figure 31 B shows another image element circuit capable at j and that the i row have readout capacity;

Figure 32 shows the example of the image element circuit of suitably having used Driving technique according to still another embodiment of the invention;

Figure 33 shows the example of the signal waveform of the pixel arrangement that is applied to Figure 32;

Figure 34 shows another example of the image element circuit of suitably having used the Driving technique relevant with Figure 32;

Figure 35 shows the example of the signal waveform of the pixel arrangement that is applied to Figure 34;

Figure 36 shows the example of pel array according to still another embodiment of the invention;

Figure 37 shows the RGBW structure of the pel array that uses Figure 36; And

Figure 38 shows the domain of the image element circuit that is used for Figure 37.

Embodiment

Utilization has light-emitting device (for example, Organic Light Emitting Diode (OLED)) and a plurality of transistorized image element circuit is described embodiments of the invention.Image element circuit in following examples or the transistor in the display system can be n transistor npn npn, p transistor npn npn or its combination.Image element circuit in following examples or the transistor in the display system can use the manufacturings of amorphous silicon, nanometer/microcrystal silicon, polysilicon, organic semiconductor technology (for example, organic tft), NMOS/PMOS technology or CMOS technology (for example MOSFET).Display with image element circuit can be monochromatic, polychrome or full-color display, and can comprise one or more than one electroluminescence (EL) element (for example organic EL).Display can be the active matrix light-emitting display (for example, AMOLED).Display can be used in TV, DVD, PDA(Personal Digital Assistant), graphoscope, cell phone or other application.Display can be dull and stereotyped.

In the following description, " image element circuit " and " pixel " uses interchangeably.In the following description, term " signal " and " line " use interchangeably.In the following description, term " line " and " node " use interchangeably.In the description, term " selection wire " and " address wire " are used interchangeably.In the following description, " connect (or being connected) " and " coupling (or being coupled) " uses interchangeably, and can be used to represent two or more elements each other directly or indirectly physically or electricity contact.In the description, i pixels (circuit) capable and the j row can be called as position (i, the pixel of j) locating (circuit).

Fig. 1 shows the example of suitably having used according to the pel array with 2 transistors (2T) image element circuit of the pixel operation technology of the embodiment of the invention.The pel array 10 of Fig. 1 comprises a plurality of image element circuits 12 of arranging with " n " row and " m " row.In Fig. 1, show the capable image element circuit of i 12.

Each image element circuit 12 comprises OLED 14, holding capacitor 16, switching transistor 18 and driving transistors 20.The drain terminal of driving transistors 20 is connected to the power lead (for example VDD (i)) of corresponding line, and the source terminal of driving transistors 20 is connected to OLED 14.A terminal of switching transistor 18 be connected to respective column data line (VDATA (1) for example ..., or VDATA (m)), and the another terminal of switching transistor 18 is connected to the gate terminal of driving transistors 20.The gate terminal of switching transistor 18 is connected to the selection wire (for example SEL (i)) that is used for corresponding line.A terminal of holding capacitor 16 is connected to the gate terminal of driving transistors 20, and the another terminal of holding capacitor 16 is connected to the source terminal of OLED 14 and driving transistors 20.OLED 14 is connected between the source terminal of power supply (for example, ground) and driving transistors 20.As described below, extract the aging of image element circuit 12 by the voltage that monitors power lead VDD (i).

Fig. 2 shows another example of the pel array with 2T image element circuit of suitably having used the pixel operation technology relevant with Fig. 1.The pel array 30 of Fig. 2 is similar to the pel array 10 of Fig. 1.Image element circuit array 30 comprises a plurality of image element circuits 32 that are arranged to " n " row and " m " row.In Fig. 2, show the capable image element circuit of i 32.

Each image element circuit 32 comprises OLED 34, holding capacitor 36, switching transistor 38 and driving transistors 40.OLED 34 is corresponding to the OLED 14 of Fig. 1.Holding capacitor 36 is corresponding to the holding capacitor 16 of Fig. 1.Switching transistor 38 is corresponding to the switching transistor 18 of Fig. 1.Driving transistors 40 is corresponding to the driving transistors 20 of Fig. 1.

The source terminal of driving transistors 40 is connected to the power lead (for example VSS (i)) that is used for corresponding line, and the drain terminal of driving transistors 40 is connected to OLED 34.A terminal of switching transistor 38 be connected to the data line that is used for respective column (for example, VDATA (1) ..., or VDATA (m)), and the another terminal of switching transistor 38 is connected to the gate terminal of driving transistors 40.A terminal of holding capacitor 34 is connected to the gate terminal of driving transistors 40, and the another terminal of holding capacitor 34 is connected to corresponding power lead (for example, VSS (i)).OLED 34 is connected between the drain terminal of power supply and driving transistors 40.As described below, extract the aging of image element circuit by the voltage that monitors power lead VSS (i).

Fig. 3 A shows the example of the signal waveform of the image element circuit that is applied to Fig. 1 and 2 in extracting operation.Fig. 3 B shows the example of the signal waveform of the image element circuit that is applied to Fig. 1 and 2 in normal running.In Fig. 3 A, VDD (i) is the power lead/signal of the VDD (i) corresponding to Fig. 1, and VSS (i) is the power lead/signal of the VSS (i) corresponding to Fig. 2." Ic " is applied to position (i, the steady current of the VDD of the pixel of j) locating (i) that just is being calibrated.Because the voltage that electric current I c produces on VDD (i) line is (V _CD+ Δ V _CD), V wherein _CDBe the DC bias point of circuit, and Δ V _CDIt is the skew of the amplification in the threshold voltage of OLED voltage and driving transistors (20 or Fig. 2 of Fig. 1 40).

With reference to figure 1,2 and 3A, come extracting position (i, the pixel of j) locating aging by monitoring power lead (VSS (i) of the VDD of Fig. 1 (i) or Fig. 2).Among Fig. 3 A (i, the operation of the pixel of j) locating comprises first and second extracting

cycles

50 and 52 for the position.In first extracting cycle 50, (i, the gate terminal of the driving transistors in the pixel of j) locating (20 or Fig. 2 of Fig. 1 40) is charged to calibration voltage V in the position _CGThis calibration voltage V _CGComprise ageing predetermination and bias voltage based on original aging data computation.And in first extracting cycle, another image element circuit that i is capable is programmed to zero.

In second extracting cycle 52, SEL (i) vanishing, and make that (i, the grid voltage of the driving transistors in the pixel of j) locating (20 or Fig. 2 of Fig. 1 40) is subjected to the influence of the dynamic effect such as electric charge injects (chargeinjection) and clock feedthrough (clock feed-through) in the position.In this cycle, driving transistors (20 or Fig. 2 of Fig. 1 40) is as amplifier, because with by the steady current of the capable power lead of i (VSS (i) of the VDD of Fig. 1 (i) or Fig. 2) it being setovered.Therefore, (i, the effect of the skew of the threshold voltage (VT) of the driving transistors in the pixel of j) locating (20 or Fig. 2 of Fig. 1 40) is exaggerated, and the voltage of power lead (VSS (i) of the VDD of Fig. 1 (i) or Fig. 2) correspondingly changes in the position.Therefore, this method can be extracted indivisible VT skew, thereby makes the calibration can be very accurate.The variation of VDD (i) or VSS (i) is monitored.Then, the variation with VDD (i) or VSS (i) comes programming data is calibrated.

With reference to figure 1,2 and Fig. 3 B, (i, the normal running of the pixel of j) locating comprises programming cycle 62 and drive cycle 64 in the position.In programming cycle 62, by use monitoring result (for example, VDD or VSS (one or more) change), (i, the gate terminal of the driving transistors in the pixel of j) locating (20 or Fig. 2 of Fig. 1 40) is charged to the program voltage V of calibration in the position _CPThis voltage V _CPGray scale and aging (for example, the aging sum that relates to the voltage of gray scale and in calibration cycle, extract) definition by pixel.Next, in drive cycle 64, selection wire SEL (i) is low (low), and (i, (i, the OLED in the pixel of j) locating (14 or Fig. 2 of Fig. 1 34) provides electric current to the driving transistors in the pixel of j) locating (20 or Fig. 2 of Fig. 1 40) for the position in the position.

Fig. 4 shows skew (VT skew) in the threshold voltage of driving transistors in the extracting cycle of Fig. 3 A to the influence of the voltage of power lead VDD.It will be apparent to those skilled in the art that driving transistors can provide reasonable gain, thereby make the extraction of little VT skew become possibility.

Fig. 5 shows the example of the display system of the pel array with Fig. 1 or 2.The display system 1000 of Fig. 5 comprises the pel array 1002 with a plurality of pixels 1004.In Fig. 5, show 4 pixels 1004.But, the quantity of pixel 1004 can be according to system design variations, and is not limited to 4.Pixel 1004 can be the image element circuit 12 of Fig. 1 or the image element circuit 32 of Fig. 2.Pel array 1002 is active matrix light-emitting displays, and can form the AMOLED display.

SEL (k) (k=i is to be used to the selection wire of selecting k capable i+1), and corresponding to the SEL (i) of Fig. 1 and Fig. 2.V (k) is a power lead, and corresponding to the VDD (j) of Fig. 1 and the VSS (j) of Fig. 2.VDATA (1) (1=j j+1) is data line, and corresponding to the VDATA (1) of Fig. 1 and Fig. 2 ..., VDATA (m) one of them.SEL (k) and V (k) share in the common row pixel of pel array 1002 and use.VDATA (1) shares in the common column pixel of pel array 1002 and uses.

Gate drivers 1006 drives SEL (k) and V (k).Gate drivers 1006 comprises the address driver that is used to SEL (k) that address signal is provided.Gate drivers 1006 comprises the monitor 1010 that is used to drive V (k) and monitors the voltage of V (k).V (k) is suitably encouraged, to be used for the operation of Fig. 3 A and Fig. 3 B.Data driver 1008 produces programming data, and drives VATA (1).Extraction apparatus piece 1014 is aging based on the last voltage calculating pixel that produces of VDD (i).Use and monitor result's (for example, variation of data line V (k)) calibration VDATA (1).Monitor that the result can be provided for controller 1012.Gate drivers 1006, controller 1012, extraction apparatus 1014 or its combination can comprise the storer that is used to store the supervision result.As mentioned above, controller 1012

Control Driver

1006 and 1008 and extraction apparatus 1014 are to drive pixel 1004.The voltage V of Fig. 3 A and 3B _CO, V _CPBy using row driver to produce.

Fig. 6 shows the example of the normal and extracting cycle of the pel array 1002 that is used to drive Fig. 5.In Fig. 6, ROWi (i=1,2 ...) wherein each represents i capable, " P " represents programming cycle, and corresponding to 60 of Fig. 3 B; " D " represents drive cycle, and corresponding to 62 of Fig. 3 B; " E1 " represents first extracting cycle, and corresponding to 50 of Fig. 3 A; And " E2 " represents second extracting cycle, and corresponding to 52 of Fig. 3 A.Extraction can take place in the blanking time (blanking time) in ending place at each frame.In this time, can extract the aging of some pixels.And, can between all being some frames of OFF, all pixels can insert extra frame.In this frame, can not influence picture quality ground and extract the aging of some pixels.

Fig. 7 shows the suitable example of 3 transistors (3T) image element circuit of pixel operation technology according to another embodiment of the present invention of having used.The image element circuit 70 of Fig. 7 comprises OLED72, holding capacitor 74, switching transistor 76 and driving transistors 78.Image element circuit 70 forms the AMOLED display.

The drain terminal of driving transistors 78 is connected to power lead VDD, and the source terminal of driving transistors 78 is connected to OLED 72.A terminal of switching transistor 76 is connected to data line VDATA, and the another terminal of switching transistor 76 is connected to the gate terminal of driving transistors 78.The gate terminal of switching transistor 76 is connected to the first selection wire SEL1.A terminal of holding capacitor 74 is connected to the gate terminal of driving transistors 78, and the another terminal of holding capacitor 74 is connected to the source terminal of OLED 72 and driving transistors 78.

For image element circuit 70 provides sensing transistor (sensing transistor) 80.Transistor 80 can be included in the image element circuit 70.A terminal of transistor 80 is connected to output line VOUT, and the another terminal of transistor 80 is connected to the source terminal and the OLED 72 of driving transistors 78.The gate terminal of transistor 80 is connected to the second selection wire SEL2.

The aging of image element circuit 70 is to extract by the voltage that monitors output line VOUT.In one example, VOUT can be independent of VDATA.In another example, VOUT can be the data line VDATA that is used for physical abutment row (OK).SEL1 is used for programming, and SEL1 and SEL2 are used to extract pixel ageing.

Fig. 8 shows another example of the 3T image element circuit of suitably having used the pixel operation technology relevant with Fig. 7.The image element circuit 90 of Fig. 8 comprises OLED 92, holding capacitor 94, switching transistor 96 and driving transistors 98.OLED 92 is corresponding to the OLED 72 of Fig. 7.Holding capacitor 94 is corresponding to the holding capacitor 74 of Fig. 7.

Transistor

96 and 98

transistors

76 and 78 corresponding to Fig. 7.Image element circuit 90 forms the AMOLED display.

The source terminal of driving transistors 98 is connected to power lead VSS, and the drain terminal of driving transistors 98 is connected to OLED 92.Switching transistor 96 is connected between the gate terminal of data line VDATA and driving transistors 98.The gate terminal of switching transistor 96 is connected to the first selection wire SEL1.A terminal of holding capacitor 94 is connected to the gate terminal of driving transistors 98, and the another terminal of holding capacitor 94 is connected to VSS.

For image element circuit 90 provides sensing transistor 100.Transistor 100 can be included in the image element circuit 90.A terminal of transistor 100 is connected to output line VOUT, and the another terminal of transistor 100 is connected to the drain terminal and the OLED 92 of driving transistors 98.The gate terminal of transistor 100 is connected to the second selection wire SEL2.

Voltage subtraction image element circuit 90 by monitoring output line VOUT aging.In one example, VOUT can be independent of VDATA.In another example, VOUT can be the data line VDATA that is used for physical abutment row (OK).SEL1 is used for programming, and SEL1 and SEL2 are used to extract pixel ageing.

Fig. 9 A shows the example of the signal waveform of the image element circuit that is applied to Fig. 7 and 8 in extracting operation.Fig. 9 B shows the example of the signal waveform of the image element circuit that is applied to Fig. 7 and 8 in normal running.

Reference 7,8 and Fig. 9 A, (i, the extraction operation of the pixel of j) locating comprises first and second extracting

cycles

110 and 112 for the position.In first extracting cycle 110, the gate terminal of driving transistors (78 or Fig. 8 of Fig. 7 98) is charged to calibration voltage V _CGThis calibration voltage V _CGComprise ageing predetermination based on original aging data computation.In second extracting cycle 112, the first selection wire SEL1 vanishing makes the grid voltage of driving transistors (78 or Fig. 8 of Fig. 7 98) be comprised that electric charge injects and the dynamic effect of clock feedthrough (clock feed-through) influences.In second extracting cycle 112, driving transistors (78 or Fig. 8 of Fig. 7 98) is as amplifier, because use steady current (Ic) by VOUT with its biasing.The voltage that occurs on VOUT owing to be applied to the electric current I c on the VOUT is (V _CD+ Δ V _CD).Therefore, the aging of pixel is exaggerated, and the voltage of VOUT correspondingly changes.Therefore, this method can be extracted indivisible threshold voltage (VT) skew, thereby can realize calibration highly accurately.Variation among the VOUT is monitored.Then, (one or more) among the VOUT change the calibration that is used for programming data.

And, by in extracting cycle, applying current/voltage, can extract the voltage/current of OLED, and system determines the aging action of OLED, and calibrate illumination data more accurately with it to OLED.

With reference to figure 7,8 and 9B, (i, the normal running of the pixel of j) locating comprises programming cycle 120 and drive cycle 122 to be used for the position.In programming cycle 120, by use monitoring result's (for example, the variation of VOUT), the gate terminal of driving transistors (78 or Fig. 8 of Fig. 7 98) is charged to the program voltage V of calibration _CPNext, in drive cycle 122, selection wire SEL1 is low, and driving transistors (78 or Fig. 8 of Fig. 7 98) provides electric current for OLED (72 or Fig. 8 of Fig. 7 92).

Figure 10 shows the example of the display system of the image element circuit with Fig. 7 or 8.The display system 1020 of Figure 10 comprises pel array 1022, and this pel array 1022 has a plurality of pixels 1004 of arranging with the form of row and column.In Figure 10, show 4 pixels 1024.But, the quantity of pixel 1024 can be according to system design variations, and is not limited to 4.Pixel 1024 can be the image element circuit 70 of Fig. 7 or the image element circuit 90 of Fig. 8.Pel array 1022 is active matrix light-emitting displays, and can be the AMOLED display.

SEL1 (k) (k=i is to be used to first selection wire of selecting k capable i+1), and corresponding to the SEL1 of Fig. 7 and Fig. 8.SEL2 (k) (k=i is to be used to second selection wire of selecting k capable i+1), and corresponding to the SEL2 of Fig. 7 and Fig. 8.VOUT (1) (1=j j+1) is the output line that is used for the 1st row, and corresponding to the VOUT of Fig. 7 and Fig. 8.VDATA (1) is the data line that is used for the 1st row, and corresponding to the VDATA of Fig. 7 and Fig. 8.

Gate drivers 1026 drives SEL1 (k) and SEL2 (k).Gate drivers 1026 comprises the address driver that is used to SEL1 (k) and SEL2 (k) that address signal is provided.Data driver 1028 produces programming data, and drives VATA (1).Data driver 1028 comprises the monitor 1030 that is used for driving and monitoring the voltage of VOUT (1).Extraction apparatus piece 1034 is aging based on the last voltage calculating pixel that produces of VOUT (i).VDATA (1) and VOUT (1) are suitably encouraged, to be used for the operation of Fig. 9 A and 9B.Use and monitor that result's (for example, variation of VOUT (1)) calibrates VDATA (1).Monitor that the result can be provided for controller 1032.Data driver 1028, controller 1032, extraction apparatus 1034 or its combination can comprise the storer that is used to store the supervision result.As mentioned above, controller 1032

Control Driver

1026 and 1028 and extraction apparatus 1034 are to drive pixel 1004.

Figure 11 A and 11B show two examples of the normal and extracting cycle of the pel array that is used to drive Figure 10.In Figure 11 A and 11B, ROWi (i=1,2 ...) wherein each represents i capable, " P " represents programming cycle, and corresponding to 120 of Fig. 9 B; " D " represents drive cycle, and corresponding to 122 of Fig. 9 B; " E1 " represents first extracting cycle and corresponding to 110 of Fig. 9 A; And " E2 " represents second extracting cycle, and corresponding to 112 of Fig. 9 A.In Figure 11 A, extraction can take place in the blanking time in ending place at each frame.In this time, can extract the aging of some pixels.And, can all be to insert extra frame between some frames of OFF in all pixels.In this frame, can not influence picture quality ground and extract the aging of some pixels.Figure 11 B shows and can be parallel to the situation that programming cycle is finished extraction.

Figure 12 shows another example of the display system of the image element circuit with Fig. 7 or 8.The display system 1040 of Figure 12 comprises the pel array 1042 with a plurality of pixels 1044 of arranging with the form of row and column.Display system 1040 is similar to the display system 1020 of Figure 10.In Figure 12, data line VDATA (j+1) is as the aging output line VOUT (j) that monitors pixel.

Gate drivers 1046 is identical or similar with the gate drivers 1026 of Figure 10.Gate drivers 1046 comprises the address driver that is used to SEL1 (k) and SEL2 (k) that address signal is provided.Data driver 1048 produces programming data and drives VDATA (1).Data driver 1048 comprises the monitor 1050 of the voltage that is used to monitor VDATA (1).VDATA (1) is suitably encouraged, to be used for the operation of Fig. 9 A and 9B.Extraction apparatus piece 1054 is aging based on the last voltage calculating pixel that produces of VDATA (1).Use and monitor result's (for example, variation of VDATA (1)) calibration VDATA (1).Monitor that the result can be provided for controller 1052.Data driver 1048, controller 1052, extraction apparatus 1054 or its combination can comprise the storer that is used to store the supervision result.As mentioned above, controller 1052

Control Driver

1046 and 1048 and extraction apparatus 1054 are to drive pixel 1004.

Figure 13 illustrates the example of the normal and extracting cycle of the pel array 1042 that is used to drive Figure 12.In Figure 13, ROWi (i=1,2 ...) wherein each represents i capable, " P " represents programming cycle, and corresponding to 120 of Fig. 9 B; " D " represents drive cycle, and corresponding to 122 of Fig. 9 B; " E1 " represents first extracting cycle, and corresponding to 110 of Fig. 9 A; And " E2 " represents second extracting cycle, and corresponding to 112 of Fig. 9 A.Extraction can take place in the blanking time in ending place at each frame.In this time, can extract the aging of some pixels.And, can all be to insert extra frame between some frames of OFF in all pixels.In this frame, can not influence picture quality ground and extract the aging of some pixels.

Figure 14 shows the example of 4 transistors (4T) image element circuit of suitably having used pixel operation technology according to still another embodiment of the invention.The image element circuit 130 of Figure 14 comprises OLED 132, holding capacitor 134, switching transistor 136 and driving transistors 138.Image element circuit 130 forms the AMOLED display.

The drain terminal of driving transistors 138 is connected to OLED 132, and the source terminal of driving transistors 138 is connected to power lead VSS (for example, ground).A terminal of switching transistor 136 is connected to data line VDATA, and the another terminal of switching transistor 136 is connected to the gate terminal of driving transistors 138.The gate terminal of switching transistor 96 is connected to selection wire SLE[j].A terminal of holding capacitor 134 is connected to the gate terminal of driving transistors 138, and the another terminal of holding capacitor 134 is connected to VSS.

For image element circuit 130 provides sensing network (sensing network) 140.Network 140 can be included in the image element circuit 130.Circuit 140 comprises transistor 142 and 144.

Transistor

142 and 144 is connected in series between the drain terminal and output line VOUT of driving transistors 138.The gate terminal of transistor 142 is connected to selection wire SEL[j+1].The gate terminal of transistor 144 is connected to selection wire SEL[j-1].

Selection wire SEL[k] (k=j-1, j j+1) can be the capable address wire of k that is used for pel array, selection wire SEL[j-1] or SEL[j+1] can be by SEL[j] replace, wherein, as SEL[j-1] and SEL[j+1] when signal is ON, SEL[j] be ON.

Voltage subtraction image element circuit 130 by monitoring output line VOUT aging.In one example, VOUT can be independent of VDATA.In another example, VOUT can be the data line VDATA that is used for physical abutment row (OK).

Figure 15 shows another example of the 4T image element circuit of suitably having used the pixel operation technology relevant with Figure 14.The image element circuit 150 of Figure 15 comprises OLED 152, holding capacitor 154, switching transistor 156 and driving transistors 158.Image element circuit 150 forms the AMOLED display.OLED152 is corresponding to the OLED 132 of Figure 14.Holding capacitor 154 is corresponding to the holding capacitor 134 of Figure 14.

Transistor

156 and 158

transistors

136 and 138 corresponding to Figure 14.

The source terminal of driving transistors 158 is connected to OLED 152, and the drain terminal of driving transistors 158 is connected to power lead VDD.Switching transistor 156 is connected between the gate terminal of data line VDATA and driving transistors 158.A terminal of holding capacitor 154 is connected to the gate terminal of driving transistors 158, and the another terminal of holding capacitor 154 is connected to the source terminal of OLED 152 and driving transistors 158.

For image element circuit 150 provides sensing network 160.Network 160 can be included in the image element circuit 150.Circuit 160 comprises transistor 162 and 164.

Transistor

162 and 164 is connected in series between the source terminal and output line VOUT of driving transistors 158.The gate terminal of transistor 162 is connected to selection wire SEL[j-1].The gate terminal of transistor 164 is connected to selection wire SEL[j+1].

Transistor

162 and 164

transistors

142 and 144 corresponding to Figure 14.

Voltage subtraction image element circuit 150 by monitoring output line VOUT aging.In one example, VOUT can be independent of VDATA.In another example, VOUT can be the data line VDATA that is used for physical abutment row (OK).

Figure 16 A shows the example of the signal waveform of the image element circuit that is applied to Figure 14 and 15 in extracting operation.Figure 16 B shows the example of the signal waveform of the image element circuit that is applied to Figure 14 and 15 in normal running.

Reference 14,15 and Figure 16 A, (i, the extraction operation of the pixel of j) locating comprises first and second extracting

cycles

170 and 172 to be used for the position.In first extracting cycle 170, the gate terminal of driving transistors (138 or Figure 15 of Figure 14 158) is charged to calibration voltage V _CGThis calibration voltage V _CGComprise the ageing predetermination that goes out based on original aging data computation.In second extracting cycle 172, selection wire SEL[i] vanishing, so the grid voltage of driving transistors (138 or Figure 15 of Figure 14 158) is comprised that electric charge injects and the dynamic effect of clock feedthrough influences.In second extracting cycle 172, driving transistors (138 or Figure 15 of Figure 14 158) is setovered it because use by the steady current of VOUT as amplifier.The voltage that occurs on VOUT owing to be applied to the electric current I c on the VOUT is (V _CD+ Δ V _CD).Therefore, the aging of pixel is exaggerated, and changed the voltage of VOUT.Therefore, this method can be extracted indivisible threshold voltage (VT) skew, thereby can realize calibration highly accurately.Variation among the VOUT is monitored.Then, the variation of (one or more) among the VOUT is used to programming data is calibrated.

And by apply current/voltage to OLED in extracting cycle, system can extract the voltage/current of OLED, and system determines the aging action of OLED, calibrates illumination data more accurately with it.

With reference to Figure 14,15 and 16B, (i, the normal running of the pixel of j) locating comprises programming cycle 180 and drive cycle 182 to be used for the position.In programming cycle 180, by use monitoring result's (for example, the variation of VOUT), the gate terminal of driving transistors (138 or Figure 15 of Figure 14 158) is charged to the program voltage V of calibration _CPIn drive cycle 182, selection wire SEL[i] be low, and driving transistors (138 or Figure 15 of Figure 14 158) provides electric current for OLED (142 or Figure 15 of Figure 14 152).

Figure 17 shows the example of the display system of the image element circuit with Figure 14 or 15, and wherein VOUT is independent of VDATA.The display system 1060 of Figure 17 is similar to the display system 1020 of Figure 10.Display system 1060 comprises the pel array with a plurality of pixels 1064 of arranging with the form of row and column.In Figure 17, show 4 pixels 1064.But, the quantity of pixel 1064 can be according to system design variations, and is not limited to 4.Pixel 1064 can be the image element circuit 130 of Figure 14 or the image element circuit 150 of Figure 15.The pel array of Figure 13 is the active matrix light-emitting display, and can be the AMOLED display.

SEL1 (k) (i+1 is to be used to the selection wire of selecting k capable i+2) for k=i-1, i, and corresponding to the SEL[j-1 of Figure 14 and Figure 15], SEL[j] and SEL[j+1].VOUT (1) (1=j j+1) is the output line that is used for the 1st row, and corresponding to the VOUT of Figure 14 and Figure 15.VDATA (1) is the data line that is used for the 1st row, and corresponding to the VDATA of Figure 14 and Figure 15.

Gate drivers 1066 drives SEL (k).Gate drivers 1066 comprises the address driver that is used to SEL (k) that address signal is provided.Data driver 1068 produces programming data, and drives VATA (1).Data driver 1068 comprises the monitor 1070 that is used for driving and monitoring the voltage of VOUT (1).Extraction apparatus piece 1074 is aging based on the last voltage calculating pixel that produces of VOUT (1).VDATA (1) and VOUT (1) are suitably encouraged, to be used for the operation of Figure 16 A and 16B.VDATA (1) is with monitoring that result's (for example, variation of VOUT (1)) calibrates.Monitor that the result can be provided for controller 1072.Data driver 1068, controller 1072, extraction apparatus 1074 or its combination can comprise the storer that is used to store the supervision result.As mentioned above, controller 1072

Control Driver

1066 and 1068 and extraction apparatus 1074 are to drive pixel 1064.

Figure 18 shows the example of the normal and extracting cycle of the pel array that is used to drive Figure 17.In Figure 18, ROWi (i=1,2 ...) wherein each represents i capable, " P " represents programming cycle, and corresponding to 180 of Figure 16 B; " D " represents drive cycle, and corresponding to 182 of Figure 16 B; " E1 " represents first and second extracting cycles, and corresponding to 170 of Figure 16 A; And " E2 " represents second extracting cycle, and corresponding to 172 of Figure 16 A.Extraction can take place in the blanking time process in ending place at each frame.In this time, can extract the aging of some pixels.And, can all be to insert extra frame between some frames of OFF in all pixels.In this frame, can not influence picture quality ground and extract the aging of some pixels.

Figure 19 shows another example of the display system of the image element circuit with Figure 14 or 15, and wherein VDATA is as VOUT.The display system 1080 of Figure 19 is similar to the display system 1040 of Figure 12.Display system 1080 comprises the pel array of a plurality of pixels 1084 of arranging with the form of row and column.In Figure 19, show 4 pixels 1084.But, the quantity of pixel 1084 can be according to system design variations, and is not limited to 4.Pixel 1084 can be the image element circuit 130 of Figure 14 or the image element circuit 150 of Figure 15.The pel array of Figure 19 is the active matrix light-emitting display, and can be the AMOLED display.

In the display system of Figure 19, VDATA is as the data line and the output line that is used to monitor pixel ageing of the 1st row.

Gate drivers 1066 drives SEL (k).Gate driving line 1086 comprises the address driver that is used to SEL (k) that address signal is provided.Data driver 1088 produces programming data, and drives VDATA (1).Data driver 1088 comprises the monitor 1090 that is used for driving and monitoring the voltage of VDATA (1).Extraction apparatus piece 1094 is aging based on the last voltage calculating pixel that produces of VDATA (1).VDATA (1) is suitably encouraged, to be used for the operation of Figure 16 A and 16B.Use and monitor result's (for example, variation of VDATA (1)) calibration VDATA (1).Monitor that the result can be provided for controller 1092.Data driver 1088, controller 1092, extraction apparatus 1094 or its combination can comprise the storer that is used to store the supervision result.As mentioned above, controller 1092

Control Driver

1086 and 1088 and extraction apparatus 1094 are to drive pixel 1084.

Figure 20 shows the example of the normal and extracting cycle of the pel array that is used to drive Figure 19.In Figure 20, ROWi (i=1,2 ...) wherein each represents i capable; " P " represents programming cycle, and corresponding to 180 of Figure 16 B; " D " represents drive cycle and corresponding to 182 of Fig. 6 B; " E1 " represents first extracting cycle, and corresponding to 170 of Figure 16 A; And " E2 " represents second extracting cycle, and corresponding to 172 of Figure 16 A.Extraction can take place in the blanking time in ending place at each frame.In this time, can extract the aging of some pixels.And, can all be to insert extra frame between some frames of OFF in all pixels.In this frame, can not influence picture quality ground and extract the aging of some pixels.

Figure 21 shows the example of the 3T image element circuit of suitably having used pixel operation scheme according to still another embodiment of the invention.The image element circuit 190 of Figure 21 comprises OLED 192, holding capacitor 194, switching transistor 196 and driving transistors 198.Image element circuit 190 forms the AMOLED display.

The drain terminal of driving transistors 198 is connected to OLED 192, and the source terminal of driving transistors 198 is connected to power lead VSS (for example, ground).A terminal of switching transistor 196 is connected to data line VDATA, and the another terminal of switching transistor 196 is connected to the gate terminal of driving transistors 198.The gate terminal of switching transistor 196 is connected to selection wire SEL.A terminal of holding capacitor 194 is connected to the gate terminal of driving transistors 198, and the another terminal of holding capacitor 194 is connected to VSS.

For image element circuit 190 provides sensing transistor 200.Transistor 200 can be included in the image element circuit 190.Transistor 200 is connected between the drain terminal and output line VOUT of driving transistors 198.The gate terminal of transistor 200 is connected to selection wire SEL.

Extract the aging of image element circuit 190 by the voltage that monitors output line VOUT.SEL is shared by switching transistor 196 and transistor 200.

Figure 22 shows another example of 3 transistors (3T) image element circuit of suitably having used the pixel operation technology relevant with Figure 21.The image element circuit 210 of Figure 22 comprises OLED 212, holding capacitor 214, switching transistor 216 and driving transistors 218.OLED 212 is corresponding to the OLED192 of Figure 21.Holding capacitor 214 is corresponding to the holding capacitor 194 of Figure 21.

Transistor

216 and 218

transistors

196 and 198 corresponding to Figure 21.Image element circuit 210 forms the AMOLED display.

The drain terminal of driving transistors 218 is connected to power lead VDD, and the source terminal of driving transistors 218 is connected to OLED 212.Switching transistor 216 is connected between the gate terminal of data line VDATA and driving transistors 218.A terminal of holding capacitor 214 is connected to the gate terminal of driving transistors 218, and the another terminal of holding capacitor 214 is connected to the source terminal and the OLED 212 of driving transistors 218.

For image element circuit 210 provides sensing transistor 220.Transistor 220 can be included in the image element circuit 210.Transistor 220 is connected to output line VOUT with the source terminal and the OLED 212 of driving transistors 218.Transistor 220 is corresponding to the transistor 200 of Figure 21.The gate terminal of transistor 220 is connected to selection wire SEL.

Extract the aging of image element circuit 210 by the voltage that monitors output line VOUT.SEL is shared by switching transistor 216 and transistor 220.

Figure 23 A shows the example of the signal waveform of the image element circuit that is applied to Figure 21 and 22 in extracting operation.Figure 23 B shows the example of the signal waveform of the image element circuit that is applied to Figure 21 and 22 in normal running.

With reference to Figure 21,22 and Figure 23 A, extract operation and comprise extracting cycle 170.In extracting cycle 170, the gate terminal of driving transistors (198 or Figure 22 of Figure 21 218) is charged to calibration voltage V _CGThis calibration voltage V _CGComprise the ageing predetermination that goes out based on original aging data computation.In extracting cycle 230, driving transistors (198 or Figure 22 of Figure 21 218) is setovered it because use by the steady current of VOUT as amplifier.The voltage that produces on VOUT owing to be applied to the electric current I c on the VOUT is (V _CD+ Δ V _CD).Therefore, the aging of pixel is exaggerated, and changed the voltage of VOUT.Therefore, this method can be extracted indivisible threshold voltage (VT) skew, thereby can realize calibration highly accurately.Variation among the VOUT is monitored.Then, (one or more) among the VOUT change the calibration that is used for programming data.

And by apply current/voltage to OLED in extracting cycle, system can extract the voltage/current of OLED and the aging action of definite OLED, and utilizes it to calibrate illumination data more accurately.

With reference to Figure 21,22 and 23B, normal running comprises programming cycle 240 and drive cycle 242.In programming cycle 240, by use monitoring result's (for example, the variation of VOUT), the gate terminal of driving transistors (198 or Figure 22 of Figure 21 218) is charged to the program voltage V of calibration _CPIn drive cycle 242, selection wire SEL is low, and driving transistors (198 or Figure 22 of Figure 21 218) provides electric current for OLED (192 or Figure 22 of Figure 21 212).

Figure 24 shows the example of the display system of the image element circuit with Figure 21 or 22, and wherein VOUT is independent of VDATA.The display system 1100 of Figure 24 comprises the pel array with a plurality of pixels 1104 of arranging with the form of row and column.In Figure 24, show 4 pixels 1104.But, the quantity of pixel 1104 can be according to system design variations, and is not limited to 4.Pixel 1104 can be the image element circuit 190 of Figure 21 or the image element circuit 210 of Figure 22.The pel array of Figure 24 is the active matrix light-emitting display, and can be the AMOLED display.

SEL (k) (k=i is to be used to the selection wire of selecting k capable i+1), and corresponding to the SEL of Figure 21 and Figure 22.VOUT (1) (1=j j+1) is the output line that is used for the 1st row, and corresponding to the VOUT of Figure 21 and Figure 22.VDATA (1) is the data line that is used for the 1st row, and corresponding to the VDATA of Figure 21 and Figure 22.

Gate drivers 1106 drives SEL (k).Gate drivers 1106 comprises the address driver that is used to SEL (k) that address signal is provided.Data driver 1108 produces programming data, and drives VATA (1).Data driver 1108 comprises the monitor 1110 that is used for driving and monitoring the voltage of VOUT (1).Extraction apparatus piece 1114 is aging based on the last voltage calculating pixel that produces of VOUT (1).VDATA (1) and VOUT (1) are suitably encouraged, to be used for the operation of Figure 23 A and 23B.Use and monitor result's (for example, variation of VOUT (1)) calibration VDATA (1).Monitor that the result can be provided for controller 1112.Data driver 1108, controller 1112, extraction apparatus 1114 or its combination can comprise the storer that is used to store the supervision result.As mentioned above, controller 1112

Control Driver

1106 and 1108 and extraction apparatus 1114 are to drive pixel 1104.

Figure 25 A and 25B show two examples of the normal and extracting cycle of the pel array that is used to drive Figure 24.In Figure 25 A and 25B, ROWi (i=1,2 ...) wherein each represents i capable; " P " represents programming cycle, and corresponding to 240 of Figure 23 B; " D " represents drive cycle, and corresponding to 242 of Figure 23 B; " E1 " represents first extracting cycle, and corresponding to 230 of Figure 23 A.In Figure 25 A, can in the blanking time, the ending at each frame extract.In this time, can extract the aging of some pixels.And, can all be to insert extra frame between some frames of OFF in all pixels.In this frame, can not influence picture quality ground and extract the aging of some pixels.In Figure 25 B, parallel the carrying out of extracting and programme.

Figure 26 shows the example of the 3T image element circuit of suitably having used pixel operation technology according to still another embodiment of the invention.The image element circuit 260 of Figure 26 comprises OLED 262, holding capacitor 264, switching transistor 266 and driving transistors 268.Image element circuit 260 forms the AMOLED display.

OLED 262 is corresponding to the OLED 192 of Figure 21.Capacitor 264 is corresponding to the capacitor 194 of Figure 21.

Transistor

264 and 268 corresponds respectively to the

transistor

196 and 198 of Figure 21.The gate terminal of switching transistor 266 is connected to the first selection wire SEL1.

For image element circuit 260 provides sensing transistor 270.Transistor 270 can be included in the image element circuit 260.Transistor 270 is connected between the drain terminal and VDATA of driving transistors 268.The gate terminal of transistor 270 is connected to the second selection wire SEL2.

Voltage by monitoring data line VDATA extracts the aging of image element circuit 260.VDATA is shared and is used for programming and extracts pixel.

Figure 27 shows another example of the 3T image element circuit of suitably having used the pixel operation technology relevant with Figure 26.The image element circuit 280 of Figure 27 comprises OLED 282, holding capacitor 284, switching transistor 286 and driving transistors 288.Image element circuit 280 forms the AMOLED display.

OLED 282 is corresponding to the OLED 212 of Figure 22.Capacitor 284 is corresponding to the capacitor 214 of Figure 22.Transistor 286 and 288 corresponds respectively to the

transistor

216 and 218 of Figure 22.The gate terminal of switching transistor 286 is connected to the first selection wire SEL1.

For image element circuit 280 provides sensing transistor 290.Transistor 290 can be included in the image element circuit 280.Transistor 290 is connected between the source terminal and VDATA of driving transistors 288.Transistor 290 is corresponding to the transistor 270 of Figure 26.The gate terminal of transistor 290 is connected to the second selection wire SEL2.

Voltage subtraction image element circuit 280 by monitoring data line VDATA aging.VDATA is common to programming and extracts pixel ageing.

Figure 28 A shows the example of the signal waveform of the image element circuit that is applied to Figure 26 and 27 in extracting operation.Figure 28 B shows the example of the signal waveform of the image element circuit that is applied to Figure 26 and 27 in normal running.

With reference to Figure 26,27 and Figure 28 A, extract operation and comprise first and second extracting cycles 300 and 302.In first extracting cycle 300, the gate terminal of driving transistors (268 or Figure 27 of Figure 26 288) is charged to calibration voltage V _CGThis calibration voltage V _CGComprise the ageing predetermination that goes out based on original aging data computation.In second extracting cycle 302, driving transistors (268 or Figure 27 of Figure 26 288) is setovered it because use by the steady current of VDATA as amplifier.Therefore, the aging of pixel is exaggerated, and the voltage of VDATA changes accordingly.Therefore, this method can be extracted indivisible voltage threshold (VT) skew, thereby can realize calibration highly accurately.Variation among the VDATA is monitored.Then, the variation of (one or more) among the VDATA is used to programming data is calibrated.

And by apply current/voltage to OLED in extracting cycle, system can extract the voltage/current of OLED, judges the aging action of OLED and uses it to carry out the more accurate calibration of illumination data.

With reference to Figure 26,27 and 28B, normal running comprises programming cycle 310 and drive cycle 312.In programming cycle 310, by use monitoring result's (that is, the variation of VDATA), the gate terminal of driving transistors (268 or Figure 27 of Figure 26 288) is charged to the program voltage V of calibration _CPNext, in drive cycle 312, selection wire SEL1 is low, and driving transistors (268 or Figure 27 of Figure 26 288) provides electric current for OLED (262 or Figure 27 of Figure 26 282).

Figure 29 shows the example of the display system of the image element circuit with Figure 26 or 27.The display system 1120 of Figure 29 comprises the pel array with a plurality of pixels 1124 of arranging with the row and column form.In Figure 29, show 4 pixels 1124.But, the quantity of pixel 1124 can be according to system design variations, and is not limited to 4.Pixel 1024 can be the image element circuit 260 of Figure 26 or the image element circuit 280 of Figure 27.The pel array of Figure 29 is the active matrix light-emitting display, and can be the AMOLED display.

SEL1 (k) (k=i is to be used to first selection wire of selecting k capable i+1), and corresponding to the SEL1 of Figure 26 and Figure 27.SEL2 (k) (k=i is to be used to second selection wire of selecting k capable i+1), and corresponding to the SEL2 of Figure 26 and Figure 27.VDATA (1) (1=j j+1) is the data line that is used for the 1st row, and corresponding to the VDATA of Figure 26 and Figure 27.

Gate drivers 1126 drives SEL1 (k) and SEL2 (k).Gate drivers 1126 comprises the address driver that is used to SEL1 (k) and SEL2 (k) that address signal is provided.Data driver 1128 produces programming data and drives VDATA (1).Data driver 1128 comprises the monitor 1130 that is used for driving and monitoring the voltage of VDATA (1).Extraction apparatus piece 1134 is aging based on the last voltage calculating pixel that produces of VDATA (1).VDATA (1) is suitably encouraged, to be used for the operation of Figure 28 A and 28B.Use and monitor result's (for example, variation of VDATA (1)) calibration VDATA (1).Monitor that the result can be provided for controller 1132.Data driver 1128, controller 1132, extraction apparatus 1134 or its combination can comprise the storer that is used to store the supervision result.As mentioned above, controller 1132

Control Driver

1126 and 1128 and extraction apparatus 1134 are to drive pixel 1124.

Figure 30 illustrates the example of the normal and extracting cycle of the pel array that is used to drive Figure 29.In Figure 30, ROWi (i=1,2 ...) wherein each represents i capable; " P " represents programming cycle, and corresponding to 310 of Figure 28 B; " D " represents drive cycle, and corresponding to 312 of Figure 28 B; " E1 " represents first extracting cycle, and corresponding to 300 of Figure 28 A; And " E2 " represents second extracting cycle, and corresponding to 302 of Figure 28 A.Extraction can take place in the blanking time in ending place at each frame.In this time, can extract the aging of some pixels.And, can all be to insert extra frame between some frames of OFF in all pixels.In this frame, can not influence picture quality ground and extract the aging of some pixels.

According at the embodiments of the invention shown in Fig. 1 to 28B, pixel ageing is extracted, and pixel programming or biased data be calibrated, and this provides operation highly accurately.According to embodiments of the invention, the programming/biasing of flat board is become highly accurate, thereby make error few.Therefore, help realizing being used for the high resolving power large-area flat-plate of display and sensor.

Below use Figure 31 A to 35 to describe in further detail and use the shared data line and the programming and the sensing technique of selection wire.

Figure 31 A and 31B show image element circuit capable at j and that the i row have readout capacity.The pixel of Figure 31 A comprises and is used for driven for emitting lights device (for example, drive circuit 352 OLED) and be used to monitor the sensing circuit (sensing circuit) 356 of the image data (acquisition data) that comes from pixel.Transistor 354 is set with based on selection wire SEL[j] on signal with data line DATA[i] be connected to drive circuit 352.Transistor 358 is set is connected to sense wire Readout[i] with output terminal with monitoring circuit 356.In Figure 31 A, pixel via transistor 354 by data line DATA[i] programming, and image data via transistor 358 by sense wire Readout[i] read back.

Sensing circuit 356 can be sensor, TFT or OLED itself.The system of Figure 31 A uses extra line (be Readout[i]).

In the pixel of Figure 31 B, transistor 358 is connected to data line DATA[i] or adjacent data line, for example DATA[i-1], DATA[i+1].By the first selection wire SEL1[i] select transistor 354, and transistor 358 is by extra selection wire SEL2[i] select.In Figure 31 B, pixel via transistor 354 by data line DATA[i] programming, and image data is read back by identical data line or the data line that is used for adjacent lines via transistor 358.Yet the line number in the panel is generally less than columns, and the system of Figure 31 B uses extra selection wire.

Figure 32 shows the example of the image element circuit of suitably having used pixel operation technology according to still another embodiment of the invention.The image element circuit 370 of Figure 32 is positioned at the capable and i row of j.In Figure 32, data line and sense wire merge and do not add extra selection wire.The image element circuit 370 of Figure 32 comprises the drive circuit 372 that is used for driven for emitting lights device (for example OLED) and is used for the sensing circuit 376 that sensing comes from the image data of pixel.Transistor 374 is set with based on selection wire SEL[i] on signal connect data line DATA[i] to drive circuit 372.As SEL[j] when high, pixel is programmed.For sensing circuit 376 provides sensing network 378.

Pixel electricity, optics or the temperature signal of sensing circuit 376 sensing driver circuit 352.Thereby the pixel ageing of generation is in time determined in the output of sensing circuit 376.Monitoring circuit 376 can be the TFT of sensor, TFT, pixel or the OLED of pixel (for example, 14 of Fig. 1).

In one example, sensing circuit 376 is connected to the data line DATA[i of the residing row of pixel via sensing network 378].In another example, sensing circuit 376 is connected to the data line that is used for one of them adjacent column (for example DATA[i+1] or DATA[i-1]) via sensing network 378.

Sensing network 378 comprises transistor 380 and 382.

Transistor

380 and 382 be connected in series the output terminal of monitor circuit 376 and data line (for example DATA[i], DATA[i-1], DATA[i+1]) between.Selection wire by adjacent lines (for example SEL[i-1], SEL[i+1]) is selected transistor 380.By selection wire SEL[i] select transistor 382, this selection wire is also connected to the gate terminal of transistor 374.

Drive circuit 372, monitor circuit 376 and switch 374,380 and 382 can be used the manufacturings of amorphous silicon, polysilicon, organic semiconductor or CMOS technology.

The configuration of Figure 32 can be used different time schedulings.But, wherein a kind of has been shown among Figure 33.The operating cycle of Figure 33 comprises programming cycle 380, drive cycle 392 and reads back the cycle 394.

With reference to Figure 32 and 33, in programming cycle 390, as SEL[i] when being ON, pass through DATA[i] to pixel programming.In drive cycle 392, SEL[i] become OFF.Handle 394, SEL[i for reading] and an adjacent capable selection wire SEL[i-1] or SEL[i+1] be ON, so, by the DATA[i that links to each other with sensing network 378], DATA[i-1] or DATA[i+1] monitoring data reads back.

Transistor

380 and 382 can exchange at an easy rate and not influence reads processing.

Figure 34 shows another example of the image element circuit of suitably having used the pixel operation technology relevant with Figure 32.The image element circuit 400 of Figure 34 is positioned at the capable i row of j.In Figure 34, data and sense wire merge, and do not add extra selection wire.The image element circuit 400 of Figure 34 comprises OLED (not shown), drive circuit 372 and sensing circuit 376.For sensing circuit 376 provides sensing network 408.Sensing network 408 comprises transistor 410 and 412.

Transistor

410 and 412 is same or similar with the

transistor

380 and 382 of Figure 32 respectively.The gate terminal of transistor 410 is connected to the selection wire SEL[j-1 that is used for (j-1) row].The gate terminal of transistor 412 is connected to the selection wire SEL[j+1 that is used for (j+1) row].As SEL[i] when being high, pixel is programmed.Transistor 412 can be by shared more than one pixel.

In one example, monitoring circuit 376 is connected to the data line DATA[j of the residing row of pixel via sensing network 408].In another example, monitoring circuit 376 is connected to the data line that is used for one of them adjacent column (for example DATA[i-1], DATA[i+1]) via sensing network 408.

Switch

410 and 412 can be made with amorphous silicon, polysilicon, organic semiconductor or CMOS technology.

The configuration of Figure 34 can be used different time schedulings.But, wherein a kind of has been shown among Figure 35.The operating cycle of Figure 35 comprises programming cycle 420, drive cycle 422 and reads back the cycle 424.

With reference to Figure 34 and 35, in programming cycle 420, as SEL[j] when being ON, pixel is passed through DATA[i] programming.In drive cycle 422, SEL[j] become OFF.Handle 424, SEL[j-1 for reading] be ON, so, by the DATA[i that links to each other with sensing network 408], DATA[i-1] or DATA[i+1] monitoring data reads

back.Transistor

410 and 412 can be easy to exchange, does not read processing and do not influence.

Display system with dot structure of Figure 31 and 34 is similar to above-mentioned display system.The data of reading back from sensing network are used for programming data is calibrated.

Technology according to an embodiment of the invention shown in Figure 32 to 40 is shared to be used for image element circuit is carried out the data programmed line and is used to extract the sense wire of pixel ageing data, and can not influence the image element circuit operation and not add extra control signal.The number of signals that links to each other with panel significantly reduces.Thereby the complexity of driver reduces.In specific AMOLED display, this has reduced the implementation cost of peripheral driver, and the collimated beam that has reduced the active matrix light-emitting display is ended the cost of (tourniquet).

Describe the technology of the aperture ratio pixel circuit that is used to strengthen collimation technique in detail with Figure 36 to 38.

Figure 36 shows the example of pel array according to still another embodiment of the invention.The pel array 500 of Figure 36 comprises a plurality of image element circuits 510 of arranging with the form of row and column.In Figure 36, show two pixels 510 of j row.Image element circuit 510 comprises OLED 512, holding capacitor 514, switching transistor 516 and driving transistors 518.OLED 512 is corresponding to the OLED 212 of Figure 22.Holding capacitor 514 is corresponding to the holding capacitor 214 of Figure 22.

Transistor

516 and 518

transistors

216 and 218 corresponding to Figure 22.

The drain terminal of driving transistors 518 is connected to power lead VDD, and source electrode of driving transistors 518 is connected to OLED 512.Switching transistor 516 is connected corresponding data line Data[j] and the gate terminal of driving transistors 518 between.A terminal of holding capacitor 514 is connected to the gate terminal of driving transistors 518, and the another terminal of holding capacitor 514 is connected to the source terminal and the OLED 512 of driving transistors 518.

For pel array 500 provides sensing network 550.Network 550 comprises sensing transistor 534 and is used for the sensing transistor 532 of each pixel.Transistor 532 can be included in the pixel 500.Sensing transistor 534 is connected to the switching transistor 532 that is used for a plurality of pixels 510.In Figure 36, sensing transistor 534 is connected to two switching transistors 532 of two pixels 510 that are used for the j row.

Be used for the position (i, the transistor 532 of the pixel of j) locating 510 is connected to data line DATA[j+1 via transistor 534], and be also connected to position (i, the OLED 512 in the pixel of j) locating 510.Similarly, be used for the position (i-h, the transistor 532 of the pixel of j) locating 510 is connected to data line DATA[j+1 via transistor 534], and be also connected to position (i-h, the OLED 512 in the pixel of j) locating 510.DATA[j+1] be to be used for (j+1) row are carried out the data programmed line.

Selection wire SEL[k by " k " row] select to be used for position (i, the transistor 532 of the pixel of j) locating 510.Selection wire SEL[k ' by k ' row] select to be used for position (i-h, the transistor 532 of the pixel of j) locating 510.Selection wire SEL[t by " t " row] selection sensing transistor 534.Not contact between " i ", " i-h ", " k ", " k ' " and " t ".But, have higher resolution in order to make compact image element circuit, they are preferably continuous.Two transistors 532 are connected to transistor 534 by inner wire (be pilot wire Monitor[j, j+1]).

Pixel 510 in one row is divided into several fragments (each fragment has " h " individual pixel).In the pel array 500 of Figure 36, two pixels in the row are in the fragment.Calibration assembly (for example transistor 534) is shared by these two pixels.

In Figure 36, the pixel of j row is by data line DATA[j] programming, and image data is by for example DATA[j+1] data line of the adjacent column of (or DATA[j-1]) reads back.Because SEL (i) is OFF in programming and leaching process, switching transistor 516 is OFF.Sensing transistor 534 is guaranteed not reading and programming process of conflict.

Figure 37 shows the RGBW structure of the picture element matrix 500 that uses Figure 36.In Figure 37, two pixels form a fragment.In Figure 37, " CSR ", " T1R ", " T2R " and " T3R " they are the assemblies that is used for redness " R " pixel, and corresponding to 514,518,516 and 532 of Figure 36; " CSG ", " T1G ", " T2G " and " T3G " they are the assemblies that is used for green " G " pixel, and corresponding to 514,518,516 and 532 of Figure 36; " CSB ", " T1B ", " T2B " and " T3B " they are the assemblies that is used for blueness " B " pixel, and corresponding to 514,518,516 and 532 of Figure 36; " CSW ", " T1W ", " T2W " and " T3W " they are the assemblies that is used for white " W " pixel, and corresponding to 514,518,516 and 532 of Figure 36.

In Figure 37, " TWB " representative is used to the shared sensing transistor of two pixels of " W " and " B ", and corresponding to the sensing transistor 534 of Figure 36; And " TGR " representative is used to the shared sensing transistor of two pixels of " G " and " R ", and corresponding to the sensing transistor 534 of Figure 36.

The gate terminal of transistor T 3W and T3G is connected to and is used for the capable selection wire SEL[i of i].The gate terminal of transistor T 3B and T3R is connected to and is used for the capable selection wire SEL[i+1 of i].The gate terminal of the gate terminal of sensing transistor TWB and sensing transistor TGR is connected to and is used for the capable selection wire SEL[i of i].

Use SEL[i] come the sensing transistor TWB of two adjacent segment of sensing and TGR to be placed on to use SEL[i] in the segment area of the pixel of programming, reducing the complexity of domain (layout), one of them fragment comprises two pixels of shared identical sensing transistor.

Figure 38 shows the domain of the image element circuit that is used for Figure 37.In Figure 38, " R " is and is used for the red relevant zone of pixel; " G " is and is used for the green relevant zone of pixel; " B " is the zone relevant with being used for blue pixels; " W " is and the relevant zone of pixel that is used for white." TWB " corresponding to the sensing transistor TWB of Figure 37, and is used to the pixel of white and is used for blue pixels share." TGR " corresponding to the sensing transistor TGR of Figure 37, and is used to green pixel and is used for red pixel share.For example, pixel is of a size of 208um * 208um.It demonstrates the application of this circuit for the minimum pixel of high resolution display.

One or more currently preferred embodiments have been described by the mode of example.It will be apparent to those skilled in the art that, can under the situation of the scope of the present invention that does not depart from the claim qualification, make a lot of variations and modification.

Claims

1. display system comprises:

The switching transistor that one or more pixels, each pixel have light-emitting device, are used to drive the driving transistors of described light-emitting device and are used to select described pixel; And

The variation that is used to monitor and extracts described pixel is with the circuit of the programming data of calibrating described pixel.

2. display system according to claim 1, wherein, described circuit comprises sensing network, is used for the path between described light-emitting device and the described driving transistors is connected to pilot wire.

3. display system according to claim 2, wherein, described pilot wire comprises the power lead that is connected to described light-emitting device or described driving transistors directly or indirectly, the output data line that is used to provide the data line of programming data or is connected to described light-emitting device or described driving transistors.

4. display system according to claim 2 wherein, is selected described switching transistor by first selection wire, and wherein, encourages described sensing network by second selection wire.

5. display system according to claim 4, wherein, described second selection wire is described first selection wire.

6. display system according to claim 2, wherein, described sensing network comprises the sensing transistor that is used for described path is connected to described pilot wire.

7. display system according to claim 6 wherein, is selected described switching transistor by selection wire, and wherein, selects described sensing transistor by described selection wire.

8. display system according to claim 2, wherein, described network comprises first sensing transistor and second sensing transistor that is used for described path is connected to described pilot wire.

9. display system according to claim 8 wherein, is selected described switching transistor by selection wire, and wherein, selects described first sensing transistor by second selection wire, and wherein, selects described second sensing transistor by the 3rd selection wire.

10. display system according to claim 1, wherein, described pixel comprises the sensing circuit that is used to monitor described pixel ageing, and wherein, described circuit comprises the sensing network that is used for described sensing circuit is connected to pilot wire.

11. display system according to claim 10, wherein, described sensing network comprises first sensing transistor and second sensing transistor that is used for described monitoring circuit is connected to described pilot wire.

12. display system according to claim 11 wherein, is selected described switching transistor by selection wire, and wherein, selects described first sensing transistor by second selection wire, and wherein, selects described second sensing transistor by the 3rd selection wire.

13. display system according to claim 8, wherein, described first sensing transistor is assigned to each pixel, and wherein, second sense switch be assigned to more than a pixel more than one first sensing transistor.

14. display system according to claim 1, wherein, described one or more pixels form the RGBW pel array.

15. display system according to claim 1, wherein, for described pixel provides line program, the variation that this line program is used to provide programming data and monitors described pixel.

16. display system according to claim 1 wherein, is extracted the aging of described pixel based on the supervision result, and wherein, based on the aging of described pixel programming data is calibrated.

17. display system according to claim 1, wherein, at least a portion of described system is used amorphous silicon, polysilicon, nanometer/miniature crystal silicon, organic semiconductor technology, TFT, NMOS/PMOS technology, CMOS technology, MOSFET and combination manufacturing thereof.

18. a method that is used to drive display system, described display system comprises one or more pixels, and this method may further comprise the steps:

At extracting cycle, to described pixel operation signal be provided, monitor node in the described pixel, based on monitoring that the result extracts the aging of described pixel; And

In programming cycle, come programming data is calibrated based on aging extraction, and provide described programming data to described pixel to described pixel.