CN101442340B - Polynomial interpolation apparatus and transpose apparatus thereof - Google Patents
Polynomial interpolation apparatus and transpose apparatus thereof Download PDFInfo
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Abstract
The invention relates to a polynomial interpolation device and a transposition device thereof in the technical field of signal and information processing. The polynomial interpolation device comprises a first time delay module, a coefficient module, a second time delay module, an adder module and a multiplying/adding module, which are sequentially connected in turn. The transposition device comprises two types, wherein one type is the transposition device obtained by transposing each branching FIR filter in the polynomial interpolation device, while the other type is the transposition device obtained by transposing the whole polynomial interpolation device. The polynomial interpolation device optimizes a Farrow interpolation device of the prior polynomial interpolation device without increasing the number of adders. Compared with the Farrow interpolation device, the polynomial interpolation device has the advantages of little coefficient, easy realization of design of hardware with low power consumption, and the like under the condition of the same interpolation performance.
Description
Technical field
What the present invention relates to is the device of technical field of information processing, and specifically, what relate to is a kind of polynomial interopolation device and transposition device thereof.
Background technology
Digital interpolative promptly between 2 or multiple spot, through control interpolation variable, in the known value that needs of inserting out between points, also can be outside all known points interpolation.Because normally in interpolation between points, so interpolation device also is interpolater.The digital interpolative device has a wide range of applications in fields such as communication, signal processing.This technology can be applied to the sampling clock synchronous (regularly synchronously) in image processing, Video processing, the all-digital receiver, the channel estimation and equalization in OFDM (OFDM) system etc.Digital interpolative is filtering in digital communication and signal processing field.Time domain interpolation to signal can be used for regularly synchronously, and this can equivalence be the phase place rotation of signal in frequency domain; Can be used for carrier synchronization to the signal frequency-domain interpolation, can be in multi-carrier communications systems through the position of digital interpolative in each number of sub-carrier of frequency domain adjustment, the signal frequency-domain interpolation can equivalence be the phase place rotation of signal in time domain.
Design for interpolation device generally includes two key steps, and the one, the obtaining of interpolation device coefficient, the 2nd, realize with hardware circuit according to coefficient.Obtaining of interpolation device coefficient need need realize under following condition usually: physical model, ideal mathematics model, constraints, design criterion, interpolation substrate and interesting areas.With regard to constraints, have usually: time-domain constraints condition, frequency domain constraints.Lagrange constraints is exactly a kind of time-domain constraints condition.With regard to design criterion or cost function, have usually: Minimum Mean Square Error (MMSE), normalization minimum mean-square poor (NMMSE), root Minimum Mean Square Error (RMMSE), peak distortion (P-D) etc.With regard to the interpolation substrate, have usually: polynomial interopolation, trigonometric function interpolation.Polynomial interopolation is also comprised: Gauss interpolation, Legendre's interpolation, Lagrange's interpolation etc.Trigonometric function interpolation comprises: sinusoidal interpolation, cosine interpolation, sine and cosine interpolation etc.Under the restriction of identical criterion, constraint and interesting areas, if these interpolation substrates are infinite dimensional, theoretically, utilize these interpolation substrates can infinite precision ground near desirable Mathematical Modeling, and their performance is of equal value.Yet interpolation device in concrete implementation procedure, can not with infinite dimensional substrate go linear expression it, even therefore be both polynomial interopolation; Even under identical constraints; And interesting areas is identical, as long as the interpolation substrate is different, its performance also possibly be different.When hardware is realized interpolation device, always hope that the complexity of design is more little good more; Total hope reduces hard-wired resource overhead, and cutting down the consumption of energy is beneficial to portable reception.Interpolation device performance under identical exponent number condition based on trigonometric function slightly is superior to the interpolation device based on polynomial interopolation, but realizes the look-up table of necessary design of sine of this interpolation device or cosine function, also need calculate the fourier series of input signal.Therefore, in digital communication system, polynomial interopolation possibly be to realize the most effectively interpolation device of mark time delay interpolation device, because it can reduce the complexity that interpolation device is realized with the Farrow interpolating apparatus.
The Farrow interpolating apparatus is to be proposed by C.W.Farrow in 1988.It can be used to realize that polynomial interopolation, Fig. 4 have provided the sketch map of typical Farrow interpolating apparatus.It is made up of one group (M+1) individual branching filter, and each branch traditional horizontal tap filter of drawing is realized, has comprised 2N tap, and wherein M is the high order power of interpolation device, also is exponent number, and N is the length of interpolation device.The Farrow interpolating apparatus various aspects with signal processing that are widely used in communicating by letter comprise the sampling clock channel estimation and equalization in (regularly synchronously), OFDM (OFDM) system etc. synchronously in the all-digital receiver.On the basis of Farrow; C.K.S.Pun, Y.C.Wu, S.C.Chan; And K.L.Ho; In the article that Signal processing letters (signal processing wall bulletin) in 2003 delivers " On the design and efficient implementation of the Farrow structure " (design with effectively realize Farrow structure), transposition is carried out in the FIR of each branch filtering in the Farrow interpolating apparatus, make the input data to get in the tap quantizer of each filter at synchronization; So that uniformly tap coefficient is carried out cyclic shift, streamline any further hardware.D.Babic in addition; .Vesma; T.Saramaki; And M.Renfor, at Circuits and Systems in 2002, in the paper of delivering on the 2002.ISCAS 2002.IEEE International Symposium on (IEEEE Circuits and Systems international symposium in 2002) " Implementation of the transposed Farrow structure " (realization of Farrow transpose configuration); The Farrow interpolating apparatus has been carried out whole transposition; Except making the input data to get in the tap quantizer of each filter to simplify the hardware at synchronization, can also accomplish the extraction work of data simultaneously, make interpolation device can be operated on the lower speed.
But, because Farrow interpolating apparatus and the coefficient matrix H that size is (M+1) * 2N
M+1,2NCorresponding one by one, always total 2MN+2N of coefficient.When specifically realizing, need consider these all interpolation coefficients simultaneously so with hardware.Above-mentioned two kinds of methods are not all carried out the optimization of essence to the Farrow interpolating apparatus on the number of coefficient.
Summary of the invention
The present invention is directed to the deficiency of prior art; A kind of polynomial interopolation device and transposition device thereof are provided; Under identical interpolation performance condition; Adopt this interpolating apparatus to have coefficient still less, can use hardware resource still less to realize polynomial interopolation, be easy to realize the advantages such as hardware designs of low-power consumption.Apparatus of the present invention can satisfy in image processing, Video processing, all-digital receiver sampling clock synchronously the technical fields such as channel estimating in (regularly synchronously), OFDM (OFDM) system to the demand of optimal polynomial interpolation.
The present invention realizes through following technical scheme:
Polynomial interopolation device involved in the present invention comprises: first time delay module, first coefficient module, second time delay module, adder Module, take advantage of/add module, wherein:
Described first time delay module links to each other respectively with first coefficient module with data inputs, and being one has the capable time delay module of M-1, and except that the time-delay number of first row is the N-1, numbers of all the other each row are 2N-1, and always having size is 2MN-3N-M+1 delay unit; Wherein M is the high order power (exponent number) of interpolation device, and N is the length of interpolation device;
Described first coefficient module links to each other respectively with second time delay module with first time delay module, and being one has the capable coefficient module of M-1, except that the coefficient number of last column is that coefficient number of all the other each row the N all are 2N;
Described second time delay module links to each other with adder Module with coefficient matrix, is a time delay module that N+1 row are arranged, and every row have 2N-1 respectively, 2N-3 ..., the time delay module of 5,3,1,1 delay unit adds up to N
2+ 1 delay unit;
Described adder Module, with second time delay module with take advantage of/add module to link to each other, be an addition module that M row are arranged, except that last row will be done the 2MN-2N+1 sub-addition, all the other row need be done (M-1) (2N-1) sub-addition;
Described taking advantage of/add module, output links to each other with data with interpolation input at interval, adder Module, is the computing unit that a multiplier and adder occur in pairs, and promptly a computing unit comprises a multiplier and an adder, total M computing unit.
In the said apparatus, M-1 the FIR filter that said first time delay module and first coefficient module constitute, and the tap number of first FIR filter is smaller or equal to N, and the tap number of all the other M-2 FIR filters is smaller or equal to 2N-1.
The transposition device of polynomial interopolation device involved in the present invention; Comprise two kinds; A kind of is that each FIR of the branch filter transposition in the polynomial interopolation device is obtained, i.e. polynomial interopolation branch transposition device, and another kind carries out transposition to whole polynomial interopolation device and obtains; Be the whole transposition device of polynomial interopolation, below describe respectively.
Polynomial interopolation of the present invention branch transposition device comprises: second coefficient module, the 3rd time delay module, the 4th time delay module, adder Module, take advantage of/add module, wherein:
Described second coefficient module links to each other respectively with the 3rd time delay module with data inputs, and being one has the second capable coefficient module of M-1, except that the coefficient number of last column is that all the other each capable coefficient number all are 2N the N;
Described the 3rd time delay module; Link to each other respectively with the 4th time delay module with second coefficient module, being one has the capable time delay module of M-1, except that the first capable time-delay number is the N-1; The number of all the other each row is 2N-1, and total total size is a 2MN-3N-M+1 delay unit; Wherein M is the high order power (exponent number) of interpolation device, and N is the length of interpolation device;
Described the 4th time delay module links to each other with adder Module with the 3rd time delay module, is a time delay module that N+1 row are arranged, and every row have 2N-1 respectively, 2N-3 ..., the time delay module of 5,3,1,2 delay unit adds up to N
2+ 2 delay units;
Described adder Module: with the 4th time delay module with take advantage of/add module to link to each other, be an addition module that M row are arranged, except that last row will be done the 2MN-2N+1 sub-addition, all the other row need be done (M-1) (2N-1) sub-addition;
Described taking advantage of/add module, output links to each other with data with interpolation input at interval, adder Module, is the computing unit that a multiplier and adder occur in pairs, and promptly a computing unit comprises a multiplier and an adder, total M computing unit.
The whole transposition device of polynomial interopolation of the present invention comprises: multiplication module, integration tripper module, tertiary system digital-to-analogue piece, adder Module, delay line, wherein:
Described multiplication module links to each other with integration tripper module with input data, input interpolation at interval, is the computation module of a total M multiplication unit;
Described integration tripper module; Link to each other with tertiary system digital-to-analogue piece with multiplication module; Comprise M+1 I&D (integration tripper) unit, each I&D unit adds up (being numerical integration) to the data of input, when surpassing thresholding, just empties the cumulative data in the unit fully;
Described tertiary system digital-to-analogue piece links to each other with adder Module with integration tripper module, is a tertiary system digital-to-analogue piece that the M-1 row are arranged, except that the no more than N of the coefficient number of last row, and all no more than 2N of coefficient number of all the other each row;
Described adder Module: link to each other with delay line with tertiary system digital-to-analogue piece; It is an addition module that the M+1 row are arranged; Remove first row and contain 1 adder, row second from the bottom contain 3 adders, and last row contain outside 2N-1 the adder; All the other each row contain 2N adder, and total adder number is 2MN-2N+3;
Described delay line, output links to each other with data with adder Module, is a delay line that comprises the time-delay of 2N-1 unit.
The span of all coefficients in above-mentioned three kinds of structures is [0.5,0.5].
The interpolation coefficient of apparatus of the present invention is compared with the Farrow interpolating apparatus, and interpolation coefficient (quantizer) number is reduced to 2MN-3N by 2MN+2N.When M=2, the number of coefficient reduces to N from 6N; When M=3, the number of interpolation coefficient reduces to 3N from 8N.Because in actual use, the exponent number M of interpolation device generally can be greater than 3, so apparatus of the present invention can reduce the number of interpolation coefficient effectively, thereby reduce the complexity of polynomial interopolation structure.Like table 1 is the complexity comparison of polynomial interopolation device of the present invention and Farrow interpolating apparatus.
Polynomial interopolation device and polynomial interopolation transposition device among the present invention under the prerequisite that does not increase the multiplier number, are optimized traditional polynomial interopolation structure Farrow interpolating apparatus.Can effectively reduce the coefficient number in the interpolating apparatus; Reduced system complexity accordingly; Thereby in practical application, can effectively reduce cost and energy efficient, with satisfy in image processing, Video processing, all-digital receiver sampling clock synchronously the technical fields such as channel estimating in (regularly synchronously), OFDM (OFDM) system to the polynomial interopolation need for equipment of low complex degree.
The complexity of the various polynomial interopolation devices of table 1 relatively
Description of drawings
Fig. 1 is an embodiment of the invention polynomial interopolation apparatus structure block diagram;
Fig. 2 is an embodiment of the invention polynomial interopolation branch transposition apparatus structure block diagram;
Fig. 3 is the whole transposition apparatus structure of an embodiment of the invention polynomial interopolation block diagram;
Fig. 4 is the Farrow interpolating apparatus;
Fig. 5 is embodiment of the invention polynomial interopolation device (M=2, N=2) fundamental diagram;
Fig. 6 is embodiment of the invention polynomial interopolation branch transposition device (M=2, N=2) fundamental diagram;
Fig. 7 is embodiment of the invention polynomial interopolation transposition device (M=2, N=2) fundamental diagram;
Fig. 8 is an embodiment of the invention interpolating apparatus branch transposition sketch map;
Fig. 9 is the whole transposition sketch map of embodiment of the invention interpolating apparatus.
Embodiment
Below in conjunction with accompanying drawing embodiments of the invention are elaborated: present embodiment provided detailed execution mode and concrete operating process, but protection scope of the present invention is not limited to following embodiment being to implement under the prerequisite with technical scheme of the present invention.
As shown in Figure 4, provided the sketch map of typical Farrow interpolating apparatus.It has (M+1) individual branching filter to constitute by one group, and each branch traditional horizontal tap filter of drawing realizes, the delay line that to comprise a length be 2N-1, contains the coefficient sets of 2N tap coefficient, and the adder group that contains 2N adder.
Polynomial interopolation device I as shown in Figure 1, that present embodiment is related, its input comprises that data are imported and interpolation is imported at interval; Data at first are input in first time delay module 1001; Getting into first coefficient module 1002 again through the data after the time-delay amplifies; Be input to then in second time delay module 1003 through time-delay; Be input to again adder Module 1004 add with or subtraction, be input to then and take advantage of/add module 1005 and interpolation to import at interval to carry out multiply-add operation, export the data after the required interpolation at last.
The practical implementation step of polynomial interopolation device I is following:
The first step: the polynomial interopolation device I that this embodiment as shown in Figure 1 is related; Data at first are input in first time delay module 1001; 1001 link to each other respectively with first coefficient module with data inputs, and being one has the capable time delay module of M-1, except that the first capable time-delay number is the N-1; The number of all the other each row is 2N-1, and data output to first coefficient module 1002 through the delay unit of every row respectively then;
Second step: each row coefficient in first coefficient module 1002 is corresponding with each line delay unit in first time delay module 1001,, outputs to then in second time delay module 1003 through 1002 amplifications of first coefficient module from 1001 data exported;
The 3rd step: second time delay module 1003 is the time delay modules that N+1 row are arranged, and every row have 2N-1 respectively, 2N-3 ... The time delay module of 5,3,1,1 delay unit; 1002 output by row output to 1003,1003 by row input is delayed time, output to adder Module 1004 again;
The 4th step: adder Module 1004 has the addition module of M row, and except that last row will be done the 2MN-2N+1 sub-addition, all the other row need be made (M-1) (2N-1) sub-addition device; From 1003 output data by the row be input to again adder Module 1004 add with or subtraction, output to then and take advantage of/add module 1005;
The 5th step: take advantage of/add module 1005 to comprise M multiplier and M adder, multiplier and adder occur in pairs; The data of 1004 outputs are progressively made at interval M time multiply-add operation with the interpolation of input, are the data after the exportable required interpolation at last.
As shown in Figure 2; The transposition device I of polynomial interopolation branch that present embodiment is related; It is a thought of having used for reference interpolation device branching filter transposition; Be that each FIR of the branch filter transposition in the polynomial interopolation device is obtained, described each branch's FIR filter is to be made up of M-1 the FIR filter that first time delay module in the polynomial interopolation device and second coefficient module constitute, each FIR of the branch filter in the polynomial interopolation device is carried out transposition after; As shown in Figure 8, can obtain second coefficient module and the 3rd time delay module in the present embodiment.
The transposition device I of polynomial interopolation branch, its input comprises that data are imported and interpolation is imported at interval; Data at first are input in second coefficient module 2001; Get into time-delay in the 3rd time delay module 2002 again through the data after the amplification of second coefficient module; Be input to then in the 4th time delay module 2003 again through time-delay; Be input to again adder Module 2004 add with or subtraction, be input to then and take advantage of/add module 2005 and interpolation to import at interval to carry out multiply-add operation, export the data after the required interpolation at last.
The practical implementation step of the transposition device I of polynomial interopolation branch is following:
The first step: the transposition device I of polynomial interopolation branch that this embodiment as shown in Figure 2 is related; Data at first are input in second coefficient module 2001; 2001 link to each other respectively with the 3rd time delay module 2002 with data inputs, and it is second coefficient module that the M-1 row coefficient is arranged; Data are exaggerated after 2001;
Second step: each the line delay unit in the 3rd time delay module 2002 is corresponding with each row coefficient in second coefficient module 2001; Except that the first capable time-delay number is the N-1; The number of all the other each row is 2N-1; From 2001 output data by the 3rd capable time delay module 2002 of the M-1 that passed through, output to then in the 4th time delay module 2003;
The 3rd step: the 4th time delay module 2003 is the time delay modules that N+1 row are arranged, and every row have 2N-1 respectively, 2N-3 ..., the time delay module of 5,3,1,2 delay unit, 2002 output is input to 2003 by row and delays time, and outputs to adder Module 2004 again;
The 4th step: adder Module 2004 has the addition module of M row, and except that last row will be done the 2MN-2N+1 sub-addition, all the other row need be made (M-1) (2N-1) sub-addition device; From 2003 output data by the row be input to again adder Module 2004 add with or subtraction, output to then and take advantage of/add module 2005;
The 5th step: take advantage of/add module 2005 to comprise M multiplier and M adder, multiplier and adder occur in pairs; The data of 2004 outputs are divided M time with the interpolation of input at interval, progressively make multiply-add operation, are the data after the exportable required interpolation at last.
The whole transposition device of polynomial interopolation II as shown in Figure 3, that present embodiment is related, it is the thought of having used for reference the whole transposition of interpolation device, whole polynomial interopolation device is carried out transposition obtain, and is as shown in Figure 9.
The whole transposition device of polynomial interopolation II, its input comprises the data input, interpolation is imported at interval and overflow the control input; Data and interpolation at first are input in the multiplication module 3001 at interval and do multiplying; Be input to then in the integration tripper module (I&D module) 3002; Overflow the control input simultaneously and produce switching signal, the data that control integration tripper module 3002 calculates output to tertiary system digital-to-analogue piece 3003, through the amplification of tertiary system digital-to-analogue piece 3003; Be input to again adder Module 3004 add with or subtraction, send into the data of exporting again behind the delay line 3005 after the required interpolation then.
The practical implementation step of the whole transposition device of polynomial interopolation II is following:
The first step: the whole transposition device of the polynomial interopolation II that present embodiment as shown in Figure 3 is related.Data at first are input in the multiplication module 3001, and 3001 is the multiplication module that M multiplication unit arranged; It with data inputs, interpolation is imported at interval links to each other respectively with integration tripper 3002, the input data in 3001 with the interpolation of input at interval mu multiply each other step by step, obtain mu from zero degree power to M power respectively with import the long-pending v that data multiply each other
0, v
1...., v
M
Second step: the v
0, v
1...., v
MBe input in the integration tripper 3002 and add up respectively, integration tripper 3002 contains M+1 I&D unit; When overflowing, produce the gating control signal through overflowing control input signals, output to again in the tertiary system digital-to-analogue piece 3003; After data output to 3003, empty the data after the adding up in 3002, operation restarts to add up;
The 3rd step: the data that control integration tripper module 3002 calculates are passed through the amplification of quantizer units in the tertiary system digital-to-analogue piece in row and separately by the data that row output to 3003,3003 inputs of tertiary system digital-to-analogue piece in 3003, output to adder Module 3004 again;
The 4th step: be input to adder Module 3004 from the data of 3003 outputs; 3004 is the addition modules that the M+1 row are arranged, and removes first row and contains 1 adder, and row second from the bottom contain 3 adders; Last row contain outside 2N-1 the adder, and all the other each row contain 2N adder; The data of input by row (2N is capable) do to add with or subtraction, output to delay line 3005 then;
The 5th step: delay line 3005 comprises the 2N-1 delay unit, is input to delay line from 3004 output 2N line data by row and delays time respectively, is the data after the exportable required interpolation at last.
Application example: in communication system commonly used based on single carrier, ATSC system for example, the adjustment of sampling clock need be through going out to be positioned at accordingly the data value at optimum sampling point place to the interpolation of data that receives.If adopt four sampled values, the exponent number of so corresponding multinomial interpolation device is 2, and length is 2.At this moment, can adjust sampling point position by present embodiment polynomial interpolation device.
The concrete application implementation step of polynomial interopolation device I is following:
The first step: the polynomial interopolation device I (M=2 that this embodiment as shown in Figure 5 is related; N=2); Data at first are input in first time delay module 5001; 5001 link to each other respectively with first coefficient module with data inputs, and 5001 have only 1 delay unit, and data output to first coefficient module 5002 through this delay unit;
Second step: have only a row coefficient in first coefficient module 5002; And have only two coefficients; These two coefficients are corresponding with delay unit in the time delay module 5001, amplify through first coefficient module 5002 from the data of 5001 outputs, output to then in second time delay module 5003;
The 3rd step: second time delay module 5003 is the time delay modules that 3 row are arranged, and every row have the time delay module of 3,1,1 delay unit respectively, and 5002 output outputs to 5003,5003 by row and by row input delayed time and to output to adder Module 5004 again;
The 4th step: adder Module 5004 has the addition module of 3 row, and except that last row will be done 5 sub-additions, all the other row need be done 3 sub-additions; From 5003 output data by the row be input to adder Module 5004 add with or subtraction, output to then and take advantage of/add module 5005;
The 5th step: take advantage of/add module 5005 to comprise 2 multipliers and 2 adders, multiplier and adder occur in pairs; The data of 5004 outputs are progressively made at interval 2 times multiply-add operation with the interpolation of input, are the data after the exportable required interpolation at last.
The concrete application implementation step of the transposition device I of polynomial interopolation branch is following:
The first step: the polynomial interopolation transposition device I (M=2 that this embodiment as shown in Figure 6 is related; N=2); Data at first are input in second coefficient module 6001; 6001 link to each other respectively with the 3rd time delay module 6002 with data inputs, and it is second coefficient module that 1 row coefficient is arranged, and has only 2 coefficients altogether; Data are exaggerated after 6001;
Second step: have only the time-delay of unit in the 3rd time delay module 6002, and corresponding, by passing through 6002 unit time-delay, output to then in the 4th time delay module 6003 from the data of 6001 outputs with two coefficients in second coefficient module 6001;
The 3rd step: the 4th time delay module 6003 is the time delay modules that 3 row are arranged, and every row have the time delay module of 3,1,2 delay units respectively, and 6002 output is input to 6003 by row and delays time, and outputs to adder Module 6004 again;
The 4th step: adder Module 6004 is the modules that 2 row adders are arranged, and except that last row will be done 5 sub-additions, first row need be made 3 sub-addition devices; From 6003 output data by the row be input to again adder Module 6004 add with or subtraction, output to then and take advantage of/add module 6005;
The 5th step: take advantage of/add module 6005 to comprise 2 multipliers and 2 adders, multiplier and adder occur in pairs; The data of 6004 outputs are divided 2 times with the interpolation of input at interval, progressively make multiply-add operation, are the data after the exportable required interpolation at last.
It is following that the tool of the whole transposition device of polynomial interopolation II is used the body implementation step:
The first step: the related polynomial interopolation transposition device II of present embodiment as shown in Figure 7 (M=2, N=2).Data at first are input in the multiplication module 7001, and 7001 is the multiplication module that 2 multiplication units are arranged; It with data inputs, interpolation is imported at interval links to each other respectively with integration tripper 7002, the input data in 7001 with the interpolation of input at interval mu multiply each other step by step, obtain mu from zero degree power to 2 time power respectively with import the long-pending v that data multiply each other
0, v
1, v
2
Second step: the v
0, v
1, v
2Be input in the integration tripper 7002 and add up respectively, integration tripper 7002 contains 3 I&D unit; When overflowing, produce the gating control signal through overflowing control input signals, output to again in the tertiary system digital-to-analogue piece 7003; After data output to 7003, empty the data after the adding up in 7002, operation restarts to add up;
The 3rd step: the data that control integration tripper module 7002 calculates output to tertiary system digital-to-analogue piece 7003 by row; The data of 7003 inputs are passed through the amplification of quantizer units in the tertiary system digital-to-analogue piece in row and separately in 7003, output to again adder Module (by among Fig. 7 all add/subtraction forms);
The 4th step: be input to adder Module from the data of 7003 outputs, adder Module is an addition module that 3 row are arranged, and first row contain 1 adder, and row second from the bottom contain 3 adders, and last row contain 3 adders; The data of input by row (4 row) do to add with or subtraction, output to delay line (three units time-delays by among Fig. 7 are formed) then;
The 5th step: delay line comprises 3 o'clock unit, exports 4 line data from adder Module and is input to delay line and delays time respectively by row, is the data after the exportable required interpolation at last.
Table 2 is at M=2, and during N=2, the complexity of various polynomial interopolation devices relatively
Through the comparison in the table 2; With three kinds of polynomial interopolation devices among the present invention; That is: during the interpolation functions of the whole transposition device of polynomial interopolation device I, the transposition device I of polynomial interopolation branch and polynomial interopolation II sampling deviation compensation in realizing the ATSC receiver; Can significantly reduce the number of quantizer in the interpolating apparatus (interpolation coefficient), reduce the complexity of polynomial interopolation device effectively, and can effectively shorten the construction cycle of hardware designs.And three kinds of optimization means of the present invention not with the performance loss of interpolation device as cost.
Can find out from three kinds of devices that above-mentioned instance is given; If when being applied to realize the interpolation functions of sampling deviation compensation in the ATSC receiver; Can effectively reduce the quantizer number in the interpolation device, reduce the hardware complexity of realizing, shorten the hardware designs cycle.Simultaneously; The application of this device will be not limited to the interpolation functions of the compensation of sampling deviation in the ATSC receiver, but can fully satisfy in image processing, Video processing, all-digital receiver sampling clock synchronously each technical fields such as channel estimating in (regularly synchronously), OFDM (OFDM) system to the demand of optimal polynomial interpolation.
Claims (6)
1. polynomial interopolation device is characterized in that comprising: first time delay module, first coefficient module, second time delay module, adder Module, take advantage of/add module, wherein:
Described first time delay module; Link to each other respectively with first coefficient module with the data input, being one has the capable time delay module of M-1, except that the first capable time-delay number is the N-1; The number of all the other each row is 2N-1; Total total size is a 2MN-3N-M+1 delay unit, and wherein M is that the high order power of interpolation device is exponent number, and N is the length of interpolation device;
Described first coefficient module links to each other respectively with second time delay module with first time delay module, and being one has the capable coefficient module of M-1, except that the coefficient number of last column is that coefficient number of all the other each row the N all are 2N;
Described second time delay module links to each other with adder Module with coefficient matrix, is a time delay module that N+1 row are arranged, and every row have 2N-1 respectively, 2N-3 ..., the time delay module of 5,3,1,1 delay unit adds up to N
2+ 1 delay unit;
Described adder Module, with second time delay module with take advantage of/add module to link to each other, be an addition module that M row are arranged, except that last row were done the 2MN-2N+1 sub-addition, all the other row were done (M-1) (2N-1) sub-addition;
Described taking advantage of/add module, output links to each other with data with interpolation input at interval, adder Module, is the computing unit that a multiplier and adder occur in pairs, and promptly a computing unit comprises a multiplier and an adder, total M computing unit;
M-1 the FIR filter that said first time delay module and first coefficient module constitute, and the tap number of first FIR filter is smaller or equal to N, and the tap number of all the other M-2 FIR filters is smaller or equal to 2N-1.
2. polynomial interopolation device according to claim 1 is characterized in that, the span of all coefficients is [0.5,0.5].
3. the polynomial interopolation branch transposition device to the described polynomial interopolation device of claim 1 is characterized in that, comprising: second coefficient module, the 3rd time delay module, the 4th time delay module, adder Module, take advantage of/add module, wherein:
Described second coefficient module links to each other respectively with the 3rd time delay module with data inputs, and being one has the capable coefficient module of M-1, except that the coefficient number of last column is that all the other each capable coefficient number all are 2N the N;
Described the 3rd time delay module; Link to each other respectively with the 4th time delay module with second coefficient module, being one has the capable time delay module of M-1, except that the first capable time-delay number is the N-1; The number of all the other each row is 2N-1, and total total size is a 2MN-3N-M+1 delay unit; Wherein M is that the high order power of interpolation device is exponent number, and N is the length of interpolation device;
Described the 4th time delay module links to each other with adder Module with the 3rd time delay module, is a time delay module that N+1 row are arranged, and every row have 2N-1 respectively, 2N-3 ..., the time delay module of 5,3,1,2 delay unit adds up to N
2+ 2 delay units;
Described adder Module, with the 4th time delay module with take advantage of/add module to link to each other, be an addition module that M row are arranged, except that last row will be done the 2MN-2N+1 sub-addition, all the other row were done (M-1) (2N-1) sub-addition;
Described taking advantage of/add module, output links to each other with data with interpolation input at interval, adder Module, is the computing unit that a multiplier and adder occur in pairs, and promptly a computing unit comprises a multiplier and an adder, total M computing unit.
4. polynomial interopolation according to claim 3 branch transposition device is characterized in that the span of all coefficients is [0.5,0.5].
5. the whole transposition device of the polynomial interopolation to the described polynomial interopolation device of claim 1 is characterized in that, comprising: multiplication module, integration tripper module, tertiary system digital-to-analogue piece, adder Module, delay line, wherein:
Described multiplication module links to each other with integration tripper module with input data, input interpolation at interval, is the computation module of a total M multiplication unit;
Described integration tripper module; Link to each other with tertiary system digital-to-analogue piece with multiplication module; Comprise M+1 integration tripper unit, it is numerical integration that each integration tripper unit adds up to the data of importing, and when surpassing thresholding, just empties the cumulative data in the unit fully;
Described tertiary system digital-to-analogue piece links to each other with adder Module with integration tripper module, is a coefficient module that M-1 row are arranged, except that the coefficient number of last row smaller or equal to the N, coefficient number of all the other each row all are less than or equal to 2N;
Described adder Module; Linking to each other with delay line with tertiary system digital-to-analogue piece, is an addition module that the M+1 row are arranged, and removes first row and contains 1 adder; Row second from the bottom contain 3 adders; Last row contain outside 2N-1 the adder, and all the other each row contain 2N adder, and total adder number is 2MN-2N+3;
Described delay line, output links to each other with data with adder Module, is a delay line that comprises the time-delay of 2N-1 unit.
6. the whole transposition device of polynomial interopolation according to claim 5 is characterized in that the span of all coefficients is [0.5,0.5].
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