CN101431487B - Low voltage differential signal transmitter - Google Patents
Low voltage differential signal transmitter Download PDFInfo
- Publication number
- CN101431487B CN101431487B CN 200710186003 CN200710186003A CN101431487B CN 101431487 B CN101431487 B CN 101431487B CN 200710186003 CN200710186003 CN 200710186003 CN 200710186003 A CN200710186003 A CN 200710186003A CN 101431487 B CN101431487 B CN 101431487B
- Authority
- CN
- China
- Prior art keywords
- signal
- data
- circuit
- npn
- differential signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Dc Digital Transmission (AREA)
Abstract
A low voltage differential signal conveyer receives a data signal, a data inversion signal and multiple logic signals. The differential signal conveyer comprises a first-step differential signal transmission circuit and a second-step differential signal transmission circuit. The first-step differential signal transmission circuit receives data signal and data inversion signal and possesses a first output terminal and a second output terminal. The second-step differential signal transmission circuit is controlled by multiple logic signal and possesses a third output terminal and a fourth output terminal separately coupling with the first output terminal and the second output terminal to produce a needed pre-emphasizing signal ; the second-step differential signal transmission circuit is controlled under a closed state when a pre-emphasizing signal is not needed producing.
Description
Technical field
The present invention relates to a kind of Low Voltage Differential Signal (LVDS) transmitter, and particularly relate to a kind of low voltage differential signal transmitter with pre-emphasis (pre-emphasis).
Background technology
Digital signal data generally is to transmit with binary data-signal, and it for example has two voltage levels, represents 0 or 1 data.From the waveform of signal, it is to transmit 0/1 serial data with the signal that high level and low level change.
Yet because circuit has the effect of resistance and electric capacity formation RC, causing rising edge (rising side) and falling edge (falling side) is not the variation that presents ladder, the mistake that more therefore causes data to be judged.Fig. 1 shows the phenomenon sketch map of RC late effect.Consult Fig. 1,, after a desirable pulse signal input, be sent to other end output back output with simple RC circuit 100.The low level of the pulse signal of input is represented 0 data, and high level is represented 1 data.The pulse signal of output is owing to the effect of RC circuit, and its rising edge all has delay with decline, possibly cause differentiating the mistake of data.For head it off, conventional art proposes the signal processing mechanism of pre-emphasis (pre-emphasis).
Fig. 2 shows traditional pre-emphasis schematic diagram of mechanism.Consult Fig. 2, data-signal 102 has two level, is rising edge by low level to the position of high level, is falling edge by high level to low level position in addition.Effect for fear of the RC delay; For example, pre-emphasis signal 104 is produced at the rising edge of correspondence and the place of falling edge, and pre-emphasis signal 104 is added data-signal 102; So can make at the speeding up of rising edge and falling edge, avoid the interpretation mistake of data.For example shown in the right figure of Fig. 2, to produce pre-emphasis signal 110, can data-signal 106 be done and postpone to obtain a data delay signal 108, again with the relation generation pre-emphasis signal 110 of this inhibit signal and data-signal.
Traditional signal transfer mechanism is then described.Fig. 3 shows the circuit diagram of traditional low voltage differential signal transmitter.Consult Fig. 3, traditional low voltage differential signal transmitter has two identical circuit paths 120,122 to be connected in parallel.Circuit paths 120 comprises P transistor npn npn and N transistor npn npn, connects by an output OUTP.Two transistorized grids are connected to an input negative supply VINN jointly.Circuit paths 122 also comprises P transistor npn npn and N transistor npn npn, connects by an output OUTN.Two transistorized grids are connected to an input positive supply VINP jointly.Two output OUTN, OUTP are connected in the two ends of a load 128. Circuit paths 120 and 122 is to be connected two current sources 124, between 126, to be driven, and operated in a low-voltage source V by bias voltage BP, BN respectively
DDAnd between the ground voltage.Mainly be to control in the operation through the reverser between two output OUTN, the OUTP (inverter-type switch).The electric current of current source is to be spilt out or spilt out by OUTN by the OUTP end, produces needed differential voltage value via ohmic load 128 more at last.Wherein, BP and BN are the bias voltages of current source, are responsible for the Control current sizes values.
Traditional low voltage differential signal transmitter of Fig. 3 does not have the function of pre-emphasis.Yet for example file such as No. the 6288581st, 6281715,6977534, United States Patent (USP) is also incorporated the circuit of pre-emphasis into.Even so, traditional low voltage differential signal transmitter still has further improved place.The dealer still continues to research and develop the different circuits design, to promote operation usefulness.
Summary of the invention
The present invention provides a kind of low voltage differential signal transmitter and transmission method, and except the function of pre-emphasis is arranged, the design of circuit can reduce the power consumption degree at least.
The present invention proposes a kind of low voltage differential signal transmitter, receives a data-signal, a data inversion signal, and a plurality of logical signal.Differential signal transmitter comprises one first step differential signal circuit, receives this data-signal and this data inversion signal, has one first output and one second output; One second step differential signal circuit; Receive the control of these a plurality of logical signals; And have one the 3rd output and one the 4th output, couple with this first output and this second output respectively, to produce a desired pre-emphasis signal; And when need not to produce the pre-emphasis signal, this second step differential signal circuit is controlled in a closed condition; One delay circuit; Receive an original data signal and a clock signal; And this original data signal is postponed this data inversion signal that the back produces this data-signal and this data-signal, more again this data-signal is postponed the time after a delayed data inversion signal of output one delayed data signal and this delayed data signal; And a pulse generator, receive this data-signal, this data inversion signal, this delayed data signal and this delayed data inversion signal, according to logic rules of setting, export this a plurality of logical signals.
According to an embodiment, in described low voltage differential signal transmitter, when for example said data-signal did not have level to change, the second step differential signal circuit of being controlled by a plurality of logical signals was to be in closed condition.
According to an embodiment; In described low voltage differential signal transmitter; For example delay circuit comprises one first trigger and one second trigger, and first trigger receives initial data and clock signal, outputting data signals and data inversion signal; Second trigger receives data-signal and clock signal, output delay data-signal and delayed data inversion signal.
According to an embodiment; In described low voltage differential signal transmitter; For example pulse generator comprises one first circuit and a second circuit, first circuit receive data-signal and delayed data signal with produce a plurality of logical signals its two, second circuit receive data inversion signal and delayed data inversion signal with produce a plurality of logical signals other its two; Wherein, first circuit has identical logical operation relation with second circuit.
According to an embodiment; In described low voltage differential signal transmitter; For example control the second step differential signal circuit, give a high level data signal and a low level digital signal respectively to produce a positive pre-emphasis signal and a negative pre-emphasis signal by a plurality of logical signals.
According to an embodiment; In described low voltage differential signal transmitter; For example the first step differential signal circuit comprises one the one P transistor npn npn, one the one N transistor npn npn, one the 2nd P transistor npn npn and one the 2nd N transistor npn npn; The one P transistor npn npn is connected into one first path with a N transistor npn npn and two grids are connected to receive data-signal; The 2nd P transistor npn npn is connected into one second path with the 2nd N transistor npn npn and two grids are connected with the reception data inversion signal, and first path is parallelly connected with second path.
According to an embodiment; In described low voltage differential signal transmitter; For example the second step differential signal circuit comprises one the one P transistor npn npn, one the one N transistor npn npn, one the 2nd P transistor npn npn and one the 2nd N transistor npn npn; The one P transistor npn npn is connected in the 3rd exit point and constitutes one first path of connecting with a N transistor npn npn; The 2nd P transistor npn npn is connected in the 4th exit point and constitutes one second path of connecting with the 2nd N transistor npn npn, and first path is parallelly connected with second path, and four transistorized four grids are accepted the control of a plurality of logical signals respectively.
According to an embodiment; In described low voltage differential signal transmitter, for example data-signal is represented with A, and data inversion signal is represented with AN; The delayed data signal of data-signal A is represented with B; The inversion signal of delayed data signal B representes with BN, and a plurality of logical signals have four logical signals to represent to be connected respectively to the grid of a P transistor npn npn, a N transistor npn npn, the 2nd P transistor npn npn and the 2nd N transistor npn npn with a, b, c, d, and negative current output is with-I
MExpression, positive current are exported with I
MExpression, pre-emphasis negative current output is with-I
M-I
NExpression, the pre-emphasis positive current is exported with I
M+ I
NExpression, electric current I
NBe to be provided by the second step differential signal circuit, the second step differential signal circuit cooperates the input of data-signal A and data inversion signal AN, to carry out a logic true value table and to export as follows:
The present invention provides a kind of low voltage differential signal transmitter again, to transmit a data-signal.Differential signal transmitter comprises a control signal generation circuit, one first step differential signal circuit, one second step differential signal circuit.It is one not have variable condition with a level of inspection data-signal that control signal generation circuit receives data-signal; And if the time decision of changing is a propradation or a decline state, wherein, corresponding three kinds of states are exported three kinds of control signals respectively.The first step differential signal circuit receives data-signal and data inversion signal, and one first output and one second output are arranged.The second step differential signal circuit; Receive the control of four logical signals; And one the 3rd output and one the 4th output are arranged, couple with first output and second output respectively, produce a desired pre-emphasis signal with correspondence according to three kinds of control signals; And when when not having variable condition, the second step differential signal circuit is controlled in a closed condition.
According to an embodiment; In described low voltage differential signal transmitter, for example control signal generation circuit comprises a delay circuit, after earlier data-signal being postponed again with the level ratio of present data; Learn one of three kinds of states, to control the mode of operation of the second step differential signal circuit.
According to an embodiment, in described low voltage differential signal transmitter, for example the pulse duration of pre-emphasis signal is the one-period time width of a clock.
The present invention also provides a kind of low voltage differential signal transmission method, to transmit a data-signal.Method for transmitting signals comprises provides one first step differential signal circuit, produces a data-signal; One second step differential signal circuit is provided, couples, produce a pre-emphasis signal with a rising edge and a falling edge to data-signal with the first step differential signal circuit.Again, method for transmitting signals also comprises provides a control signal generation circuit, produces a plurality of control signals, to control the second step differential signal circuit to produce the pre-emphasis signal.And, when the level at data-signal does not change, the second step differential signal circuit is controlled in a closed condition.
For let above and other objects of the present invention, feature and advantage can be more obviously understandable, hereinafter is special lifts preferred embodiment, and conjunction with figs., elaborates as follows.
Description of drawings
Fig. 1 shows the phenomenon sketch map of RC late effect.
Fig. 2 shows traditional pre-emphasis schematic diagram of mechanism.
Fig. 3 shows the circuit diagram of traditional low voltage differential signal transmitter.
Fig. 4 shows according to the embodiment of the invention, the circuit diagram of low voltage differential signal transmitter.
Fig. 5 shows according to one embodiment of the invention, the sketch map of delay circuit 250.
Fig. 6 shows according to one embodiment of the invention, the pulse generator circuit diagram.
Fig. 7 shows according to one embodiment of the invention, another kind of pulse generator circuit diagram.
Fig. 8 shows according to one embodiment of the invention, utilizes the sequential chart and the truth table of the circuit transmissioning signal of Fig. 4.
Fig. 9 shows according to another embodiment of the present invention, utilizes the sequential chart of the circuit transmissioning signal of Fig. 4.
The reference numeral explanation
The 100:RC circuit
102: data-signal
104: the pre-emphasis signal
106: data-signal
108: data delay signal
110: the pre-emphasis signal
120,122: circuit paths
124,126: current source
128,212: load
150: main level LVDS transmission circuit
160: less important level LVDS transmission circuit
200,202: circuit paths
204,206,222,224: current source
208: the common-mode voltage detection module
210: the common-mode voltage error amplifier
214,216,218,220: transistor
250: delay circuit
250a, 250b: trigger
252: pulse generator
254,264: impulse circuit
256,258,260,262: transistor
266,268: inverter
270: or gate
272: with gate.
Embodiment
Low voltage differential signal transmitter of the present invention is the low voltage differential signal transmitter that has pre-emphasis; Except that comprising main level (primary stage) Low Voltage Differential Signal transmission circuit, again by the Low Voltage Differential Signal transmission circuit that increases a less important level (secondary stage) with and control circuit.When the defeated signal of tendency to develop changed, output current is many again one extra electric current except the electric current that main level is provided, and reached the effect of pre-emphasis by this.But when the defeated signal of tendency to develop did not change, output current was for only there being the electric current of main level, and the electric current of less important level can be closed the waste that does not have electric current because of transistor switch, has therefore improved the efficient of electric current.Below lift some embodiment as explanation of the present invention, but the present invention is not subject to the embodiment that lifts.
In order to realize above-mentioned mechanism, for example that tendency to develop is defeated signal produces inhibit signal and inversion signal thereof with trigger, again with these signal input pulse generators to produce the purpose of control signal to reach pre-emphasis and can not waste electric current of less important level.
Fig. 4 shows according to the embodiment of the invention, the circuit diagram of low voltage differential signal transmitter.Low voltage differential signal transmitter comprises 150, one less important grades of LVDS transmission circuits 160 of one main grade of LVDS transmission circuit, and a control signal generation circuit 250+252.
Consult Fig. 4, main level LVDS transmission circuit 150 for example comprises the circuit paths 200 and circuit paths 202 of symmetry.Circuit paths 200 is connected with a N transistor npn npn by a P transistor npn npn, and tie point is as an exit point OUTP.The grid of two-transistor connects to receive a data-signal AN jointly.Circuit paths 202 also is to be connected with a N transistor npn npn by a P transistor npn npn, and tie point is as another exit point OUTN.The grid of two-transistor connects to receive a data-signal A jointly.Anti-phase data signal AN is the inversion signal of data-signal A.Circuit paths 200 is with circuit paths 202 parallelly connected formation one current steering circuits (current steering circuit) and be connected two current sources 204, between 206.Current source 204 is by BP signal driving and generating electric current I
M, the level of its corresponding data signal.One common-mode voltage detection module (common mode voltage sense module) 208 is connected two exit point OUTP, OUTN produces a common mode error voltage Vs.A common-mode error voltage Vs and a reference voltage Vcm produce drive signal by a common-mode voltage error amplifier (common mode voltage error amplifier) 210 and give current source 206.
The generation of data-signal A and anti-phase data signal AN, and other required control signal for example are to produce by control signal generation circuit 250+252, and the back has more detailed description.
Less important level LVDS transmission circuit 160 of the present invention and main level LVDS transmission circuit 150 can be to data-signal to produce the effect of pre-emphasis.The basic circuit of less important level LVDS transmission circuit 160 is for example identical haply with main level LVDS transmission circuit 150, but control mode is different.Less important level LVDS transmission circuit 160 for example comprises by the circuit paths of two symmetries forms a current steering unit.One circuit paths for example is made up of a P transistor npn npn 214 institute of connecting with a N transistor npn npn 216, and tie point is connected with exit point OUTN.The grid of two-transistor is accepted the control of control signal a and b respectively.Another circuit paths also is made up of a P transistor npn npn 218 institute of connecting with a N transistor npn npn 220, and tie point is connected with exit point OUTP.
Other two current sources 222,224 are in order to produce the pre-emphasis electric current I that increases in advance
N, superposition is in the electric current I of data-signal
MOn.By between exit point OUTP and the exit point OUTN load 212 being arranged, the electric current I out that the is produced load 212 of can flowing through produces the level of needed data-signal.
Below continue description control circuit and pre-emphasis signal generator system.An original data signal DATA and an operating clock CLK can be input to a delay circuit 250 earlier.Each signal period of data-signal has a level to represent one data.Data-signal is represented the input of a serial data on time shaft.The variation of last bit data and back one digit number certificate possibly be four kinds of situations of 10,01,00 or 11.Data delay circuit 250 mainly is will data-signal be done a delay; Data with the cycle before allowing are done comparison with the data in present cycle; Which kind of state with the variation of learning data level is, it has three kinds of states basically: changed to high level (1), changed to low level (0) and not variation of level by high level (1) by low level (0).The situation that level does not have to change can be again to maintain high level (11) or maintain low level (00).Therefore, also can be subdivided into four kinds of states 01,10,11 and 00.
Cooperate above-mentioned mechanism, delay circuit 250 corresponding original data signal DATA produce the data inversion signal AN of data-signal A and its anti-phase.After suitably postponing, produce the delayed data inversion signal BN of delayed data signal B and its anti-phase in addition.In addition, pulse generator 252 produces four control signal a, b, c, d according to signal A, B, AN, the BN of input, controls the Push And Release of four transistors 214,216,218,220 respectively.Because the output of less important level LVDS transmission circuit 160 is to link together with main level LVDS transmission circuit 150, the pre-emphasis electric current I that is therefore produced by less important level LVDS transmission circuit 160
NMeeting and electric current I
MSuperposition.Less important level LVDS transmission circuit 160 need not produce the pre-emphasis electric current I
NThe time, can be controlled in closed condition.
According to one embodiment of the invention, in order control less important grade of LVDS transmission circuit, ought need the pre-emphasis signal with its unlatching Cai make, in the time of need not the pre-emphasis signal it to be closed, it needs number control signal.Cooperate the circuit of Fig. 4, it need produce four control signal a, b, c, d, can be described as the transistor switch that logical signal is controlled less important level LVDS transmission circuit 160 again.
The logic true value table (truth table) that produces and output (Iout) is as follows:
| A | B | AN | BN | a | b | | d | Output | |
| 0 0 1 1 | 0 1 0 1 | 1 1 0 0 | 1 0 1 0 | 1 0 1 1 | 0 0 1 0 | 1 1 0 1 | 0 1 0 0 | -I M -I M-I N I M+I N I M |
Wherein ,-I
MThe representative data low level, I
MThe representative data high level ,-I
M-I
NRepresent the data low level behind the pre-emphasis, I
M+ I
NRepresent the data high level behind the pre-emphasis.The circuit arrangement that the present invention proposes when A is identical with B, data I
MOnly, therefore need less important level LVDS transmission circuit 160 to cut out in good time by control signal a, b, c, d by 150 outputs of main level LVDS transmission circuit.When for example A is identical with B, a=1, b=0.In Fig. 4, because the P transistor npn npn is to be closed by high level, the N transistor npn npn is to be closed by low level, and signal a and b close transistor 214,216.Again, the transistor symmetric relation among Fig. 4 also can be kept P transistor npn npn and the exchange of N transistor npn npn, and its operation mechanism is constant.
Yet Fig. 6 is not unique design of reaching pulse generator 252.Fig. 7 shows according to one embodiment of the invention, another kind of pulse generator circuit diagram.Consult Fig. 7, two impulse circuits 254,264 also can be by 266,268, one of two inverters or 270 and one of gates (OR gate) and gate (AND gate) 272.Again, two impulse circuits 254,264 also can be reached by circuit inequality.Below lift the sequential relationship between some instance explanation signals.Fig. 8 shows according to one embodiment of the invention, utilizes the sequential chart and the truth table of the circuit transmissioning signal of Fig. 4.Consult Fig. 8, initial data DATA is the data that will transmit, for example 010011010.Clock CLK is used for producing data-signal A and delayed data signal B.In this embodiment, cycle data for example is a clock cycle.The electric current I of plus or minus
MBe to provide by main level LVDS transmission circuit 150.The electric current I of plus or minus
NBe to provide by less important level LVDS transmission circuit 160.In 00 and 11 data order, second data can not produce electric current I
N, the power consumption that therefore can save less important level LVDS transmission circuit 160 at least.
Fig. 9 shows according to another embodiment of the present invention, utilizes the sequential chart of the circuit transmissioning signal of Fig. 4.Consult Fig. 9, the content of initial data DATA for example also is 010011010, but the clock cycle of clock signal clk for example is the half the of signal period, so also can shorten the time width of pre-emphasis signal.
The present invention incorporates suitable controlling mechanism into, can only when data change, just produce the pre-emphasis signal.When changing, data need not produce the pre-emphasis signal.
Though the present invention discloses as above with preferred embodiment; Right its is not in order to limit the present invention; Anyly have the knack of this art; Send out in spirit and the scope not breaking away from the present invention, when can doing a little change and retouching, so protection scope of the present invention ought be looked the claim person of defining of the present invention and is as the criterion.
Claims (11)
1. a low voltage differential signal transmitter receives a data-signal, a data inversion signal, and a plurality of logical signal, and this differential signal transmitter comprises:
One first step differential signal circuit receives this data-signal and this data inversion signal, has one first output and one second output;
One second step differential signal circuit; Receive the control of these a plurality of logical signals; And have one the 3rd output and this first output couples, one the 4th output and this second output couple, to produce a desired pre-emphasis signal; And when need not to produce the pre-emphasis signal, this second step differential signal circuit is controlled in a closed condition;
One delay circuit; Receive an original data signal and a clock signal; And this original data signal is postponed this data inversion signal that the back produces this data-signal and this data-signal, more again this data-signal is postponed the time after a delayed data inversion signal of output one delayed data signal and this delayed data signal; And
One pulse generator receives this data-signal, this data inversion signal, this delayed data signal and this delayed data inversion signal, according to logic rules of setting, exports this a plurality of logical signals,
Wherein, This second step differential signal circuit comprises one the one P transistor npn npn, one the one N transistor npn npn, one the 2nd P transistor npn npn and one the 2nd N transistor npn npn; The one P transistor npn npn is connected in the 3rd output and constitutes one first path of connecting with a N transistor npn npn; The 2nd P transistor npn npn is connected in the 4th output and constitutes one second path of connecting with the 2nd N transistor npn npn, and this first path is parallelly connected with this second path, and wherein these a plurality of logical signals are that four logical signals are represented with a, b, c, d; A is connected to the grid of a P transistor npn npn; B is connected to the grid of a N transistor npn npn, and c is connected to the grid of the 2nd P transistor npn npn, and d is connected to the grid of the 2nd N transistor npn npn.
2. low voltage differential signal transmitter as claimed in claim 1, wherein, when this data-signal did not have level to change, this second step differential signal circuit of being controlled by these a plurality of logical signals was in this closed condition.
3. low voltage differential signal transmitter as claimed in claim 1; Wherein, This delay circuit comprises one first trigger and one second trigger, and this first trigger receives this original data signal and this clock signal, exports this data-signal and this data inversion signal; This second trigger receives this data-signal and this clock signal, exports this delayed data signal and this delayed data inversion signal.
4. low voltage differential signal transmitter as claimed in claim 1; Wherein, This pulse generator comprises one first circuit and a second circuit, this first circuit receive this data-signal and this delayed data signal with produce these a plurality of logical signals its two, this second circuit receive this data inversion signal and this delayed data inversion signal with produce these a plurality of logical signals other its two; Wherein, this first circuit has identical logical operation relation with this second circuit.
5. low voltage differential signal transmitter as claimed in claim 1; Wherein, By these a plurality of these second step differential signal circuits of logical signal control; To produce a positive pre-emphasis signal and a negative pre-emphasis signal, wherein this positive pre-emphasis signal is given a high level data signal, and this negative pre-emphasis signal is given a low level digital signal.
6. low voltage differential signal transmitter as claimed in claim 1; Wherein, This first step differential signal circuit comprises one the 3rd P transistor npn npn, one the 3rd N transistor npn npn, one the 4th P transistor npn npn and one the 4th N transistor npn npn; The 3rd P transistor npn npn is connected into Third Road footpath with the 3rd N transistor npn npn and two grids are connected to receive this data-signal; The 4th P transistor npn npn and the 4th N transistor npn npn are connected into one the 4th path and two grids and are connected receiving this data inversion signal, and this Third Road footpath is parallelly connected with the 4th path.
7. low voltage differential signal transmitter as claimed in claim 1, wherein, this first path and this second path are to be connected in parallel between two current sources.
8. low voltage differential signal transmitter as claimed in claim 1 also comprises a circuit, checks whether the level of this data-signal changes, and when not having level to change, closes this second step differential signal circuit.
9. low voltage differential signal transmitter as claimed in claim 1, wherein, this data-signal is represented with A; This data inversion signal is represented with AN; The delayed data signal of this data-signal A representes with B, and the inversion signal of this delayed data signal B representes with BN, and negative current output is with-I
MExpression, positive current are exported with I
MExpression, pre-emphasis negative current output is with-I
M-I
NExpression, the pre-emphasis positive current is exported with I
M+ I
NExpression, electric current I
NBe to provide, cooperate the input of this data-signal A and this data inversion signal AN by this second step differential signal circuit, to carry out a logic true value table and to export as follows:
10. low voltage differential signal transmitter as claimed in claim 9; Wherein, This data-signal A, this data inversion signal AN, this delayed data signal B and this delay inversion signal BN are by a delay circuit, produce after receiving an original data signal and a clock signal.
11. low voltage differential signal transmitter as claimed in claim 10; Wherein, These four logical signal a, b, c, d are by a pulse generator, produce according to this data-signal A, this data inversion signal AN, this delayed data signal B and this state that postpones inversion signal BN.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710186003 CN101431487B (en) | 2007-11-09 | 2007-11-09 | Low voltage differential signal transmitter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710186003 CN101431487B (en) | 2007-11-09 | 2007-11-09 | Low voltage differential signal transmitter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101431487A CN101431487A (en) | 2009-05-13 |
| CN101431487B true CN101431487B (en) | 2012-12-19 |
Family
ID=40646658
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200710186003 Expired - Fee Related CN101431487B (en) | 2007-11-09 | 2007-11-09 | Low voltage differential signal transmitter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101431487B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105991122B (en) * | 2015-02-11 | 2019-03-12 | 联咏科技股份有限公司 | Double mode serial transmission device and its mode switching method |
| CN106656150A (en) * | 2015-10-28 | 2017-05-10 | 北京华大九天软件有限公司 | Drive circuit used for LVDS sending end |
| CN109741491B (en) * | 2018-12-18 | 2021-05-18 | 深圳市铁证科技有限公司 | Vena digitalis face lock master control module |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6288581B1 (en) * | 2001-01-05 | 2001-09-11 | Pericom Semiconductor Corp. | Low-voltage differential-signalling output buffer with pre-emphasis |
| US6977534B2 (en) * | 2002-12-23 | 2005-12-20 | Alcatel | Low voltage differential signaling [LVDS] driver with pre-emphasis |
-
2007
- 2007-11-09 CN CN 200710186003 patent/CN101431487B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6288581B1 (en) * | 2001-01-05 | 2001-09-11 | Pericom Semiconductor Corp. | Low-voltage differential-signalling output buffer with pre-emphasis |
| US6977534B2 (en) * | 2002-12-23 | 2005-12-20 | Alcatel | Low voltage differential signaling [LVDS] driver with pre-emphasis |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101431487A (en) | 2009-05-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7579874B2 (en) | Low voltage differential signaling transmitter and transmitting method | |
| JP5906960B2 (en) | Semiconductor integrated circuit, signal transmission circuit, signal transmission system, and signal transmission method | |
| US7362127B2 (en) | Driver circuit | |
| CN107800654A (en) | The line driver device of feedthrough electric capacity and feed forward equalization with merging | |
| CN101431487B (en) | Low voltage differential signal transmitter | |
| CN109565278A (en) | The impedance of voltage mode driver and swing-scanning control | |
| CN108766493A (en) | A kind of adjustable WLUD applied to SRAM reads and writes auxiliary circuit | |
| EP1286470B1 (en) | Input/output interface and semiconductor integrated circuit having input/output interface | |
| WO2002009281A2 (en) | 5-ary receiver utilizing common mode insensitive differential offset comparator | |
| CN101146069A (en) | Differential signal drive circuit applicable to low-work voltage | |
| US8575961B2 (en) | Multi-valued driver circuit | |
| CN117762847A (en) | LVDS receiving circuit | |
| US8452001B1 (en) | Class A-B line driver for gigabit Ethernet | |
| US7196550B1 (en) | Complementary CMOS driver circuit with de-skew control | |
| US9094003B2 (en) | Buffering circuit, semiconductor device having the same, and methods thereof | |
| CN106849915A (en) | A kind of programmable clock phase-shift circuit | |
| CN113098495B (en) | Digital circuit comprising a gate circuit | |
| TWI599173B (en) | Low Voltage Differential Signaling Transmitter and Receiver | |
| CN110798198A (en) | Data latch circuit and pulse signal generator thereof | |
| US9537469B2 (en) | CMOS level shifter with reduced high voltage transistor count | |
| US7176724B1 (en) | High speed chip-to-chip communication links | |
| EP2062148B1 (en) | Static pulsed bus circuit and method having dynamic power supply rail selection | |
| CN113271085B (en) | Ring oscillator and method thereof | |
| CN214315230U (en) | Fully-differential high-speed logic conversion circuit, chip and laser radar | |
| Su et al. | LVDS transmitter with optimized high power-efficiency 8: 1 MUX |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20121219 Termination date: 20131109 |