CN101431028A - Enhancement type back grid zinc oxide nano wire field effect transistor and method for producing the same - Google Patents

Enhancement type back grid zinc oxide nano wire field effect transistor and method for producing the same Download PDF

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Publication number
CN101431028A
CN101431028A CN 200810227461 CN200810227461A CN101431028A CN 101431028 A CN101431028 A CN 101431028A CN 200810227461 CN200810227461 CN 200810227461 CN 200810227461 A CN200810227461 A CN 200810227461A CN 101431028 A CN101431028 A CN 101431028A
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substrate
zinc oxide
preparation
nano wire
oxide nanowire
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CN101431028B (en
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徐静波
张海英
黎明
付晓君
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Semiconductor Manufacturing International Shanghai Corp
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Institute of Microelectronics of CAS
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Abstract

The invention relates to an enhanced back-gate zinc oxide nanowire field-effect transistor and a preparation method thereof. The method comprises the following steps: growing gate oxygen medium SiO2 on the front surface of a P+-Si substrate; forming back-gate electrodes on the back surface of the P+-Si substrate; forming a position mark on the front surface of the P+-Si substrate; transferring and depositing a zinc oxide nanowire on the front surface of the P+-Si substrate; positioning the zinc oxide nanowire on the front surface of the P+-Si substrate; producing a source electrode and a drain electrode on the front surface of the P+-Si substrate; and carrying out annealing treatment. The method for preparing the enhanced back-gate zinc oxide nanowire field-effect transistor achieves the enhanced back-gate zinc oxide nanowire field-effect transistor with threshold voltage higher than 0V.

Description

Enhancement type back grid zinc oxide nano wire field effect transistor and preparation method thereof
Technical field
The present invention relates to compound semiconductor materials and devices field, especially relate to enhancement type back grid zinc oxide nano wire field effect transistor and preparation method thereof.
Background technology
ZnO is the Multifunction compound semiconductor materials of a kind of II-VI family direct band gap, is called as third generation semiconductor material with wide forbidden band.ZnO crystal is a wurtzite structure, and energy gap is about 3.37eV, and exciton bind energy is about 60meV.ZnO possesses characteristics such as semiconductor, photoelectricity, piezoelectricity, thermoelectricity, air-sensitive and electrically conducting transparent, at numerous areas such as sensing, sound, light, electricity wide potential using value is arranged.
In recent years, the research to ZnO material and device is subjected to extensive concern.Research range has contained growth and characteristic and ZnO transducer, transparency electrode, piezo-resistance, solar cell window, surface acoustic wave device, detector and the light-emitting diode preparation of devices and the research aspects such as (Light-emitting Diodes, abbreviation LED) of materials such as ZnO body monocrystalline, film, quantum wire, quantum dot.At present, form the growth that several different methods is used for the ZnO material, and developed the ZnO device and the transducer of some kinds, but the growth of P type ZnO material, and problems such as the preparation of ZnO nano-device and application still need deeply and systematic research.
ZnO has nanostructure and the abundantest material of characteristic at present, and the nanostructure that has realized comprises nano wire, nano belt, nano-rings, nano-comb, nanotube or the like.Wherein, one-dimensional nano line is owing to the granular of material, and specific area increases, and has the not available skin effect of conventional body material, small-size effect, quantum effect and macro quanta tunnel effect, and crystal mass is better, and the transport performance of charge carrier is more superior.One-dimensional nano line not only can be realized basic nanoscale components and parts (as laser, transducer, field-effect transistor, light-emitting diode, logic, spin electric device and quantum computer etc.), and can also be used for connecting various nano-devices, be expected on single nano wire, to realize having electronics, photon and the spin information processing device of sophisticated functions.
ZnO nano-wire field effect transistor (Nanowire Field-Effect Transistor, abbreviation NWFET) has become one of focus of international research.The ZnO one-dimensional nano line can form metal-oxide semiconductor fieldeffect transistor (Metal-Oxide-SemiconductorField-Effect Transistor, abbreviation MOSFET) as raceway groove with grid oxygen and grid metal.Because the electric property of ZnO nano wire changes with the change of forming gas in the surrounding atmosphere, such as unadulterated ZnO reproducibility, oxidizing gas is had superior sensitiveness, therefore can detect and quantitative test corresponding gas.This makes ZnO one-dimensional nano line field-effect transistor can be used for gas, humidity and chemical sensor, photoelectricity and ultraviolet detector, memory applications such as (Memory).Especially can survey toxic gas (as CO, NH3 etc.),, can detect the composition and the concentration of gas by the mutual conductance variation of field-effect transistor.Compare with conventional SnO2 gas sensor, it is little to have size based on the gas sensor of ZnO nano-wire field effect transistor, and cost is low, advantage such as can reuse.
In sum, the development of ZnO nano-wire field effect transistor has important research and using value aspect nanoelectronics and the novel nano transducer, will play important impetus to development and national economy.
Because intrinsic ZnO is N type semiconductor, and the ZnO NW FET that makes mostly is depletion device, restricted the development of enhancement type ZnO NW FET.
Summary of the invention
In order to overcome the ZnO nano-material in the limitation that realizes based on the enhancement type back grid zinc oxide nano wire field effect transistor application facet, the present invention provides a kind of enhancement type back grid zinc oxide nano wire field effect transistor and preparation method thereof on the basis of depletion type back gate zinc oxide nanowire field effect transistor manufacture craft.
A kind of enhancement type back grid zinc oxide nano wire field effect transistor preparation method, comprising: at the front of P+-Si substrate growth grid oxygen medium SiO 2The back side at the P+-Si substrate forms back-gate electrode; Front at the P+-Si substrate forms telltale mark; Finish the transfer and the deposit of zinc oxide nanowire in the front of P+-Si substrate; Finish the location of nano wire in the front of P+-Si substrate; Front at the P+-Si substrate makes source-drain electrode; Annealing in process.
A kind of enhancement type back grid zinc oxide nano wire field effect transistor, comprising: grid oxygen medium SiO 2, grow in the substrate face of P+-Si device; Back-gate electrode is formed at the substrate back of P+-Si device by evaporated metal; Telltale mark is formed at the substrate face of P+-Si device; Zinc oxide nanowire is positioned over the substrate face of P+-Si device; Source-drain electrode is formed at the substrate face of described P+-Si device; On the above-mentioned technology basis, carry out annealing in process again, make script less than zero threshold voltage that lies prostrate, positive excursion forms the threshold voltage that lies prostrate greater than zero.
Enhancement type back grid zinc oxide nano wire field effect transistor provided by the invention and preparation method thereof has been realized the enhancement type back grid ZnO NW FET of threshold voltage greater than zero volt.
Description of drawings
Fig. 1 is a kind of enhancement type back grid of the present invention ZnO NW FET preparation method's schematic flow sheet;
The transfer characteristic curve of the ZnO NW FET device among Fig. 2 Fig. 1 after the annealing in process;
Fig. 3 is the structural representation of a kind of enhancement type back grid of the present invention ZnO NW FET.
Embodiment
Fig. 1 is a kind of enhancement type back grid zinc oxide nano wire field effect transistor preparation method's of the present invention schematic flow sheet.This preparation method may further comprise the steps:
Step 1, at the front of P+-Si substrate growth grid oxygen medium SiO 2Utilize PECVD (plasma enhanced chemical vapor deposition) at the front of P+-Si substrate growth grid oxygen medium SiO 2, finish the making of the grid oxygen medium of back of the body grid ZnO nano-wire field effect transistor.
Step 2, form back-gate electrode at the back side of P+-Si substrate.At the back side of P+-Si substrate evaporated metal, form back-gate electrode.
Step 3, form telltale mark in the front of P+-Si substrate.Carry out photoetching telltale mark figure, evaporated metal, stripping metal in the front of P+-Si substrate successively, the cross telltale mark of the periodic arrangement of formation rule is for follow-up nano wire positioning process provides cross telltale mark.
Step 4, finish the transfer and the deposit of zinc oxide nanowire in the front of P+-Si substrate.The zinc-oxide nano wire material is soaked in the isopropyl acetone solution, adopts the ultrasonotomography technology, nano wire is come off from the growth substrates surface, be suspended in isopropyl acetone solution; And the isopropyl acetone drips of solution that will contain zinc oxide nanowire is finished the transfer and the deposit of zinc oxide nanowire in the front of P+-Si substrate.
Step 5, the location of finishing nano wire in the front of P+-Si substrate.Under high-power microscope, observe zinc oxide nanowire, utilize cross telltale mark, the accurate position of zinc oxide nanowire is provided for the subsequent optical carving technology.
Step 6, make source-drain electrode in the front of P+-Si substrate.Photolithographic source drain electrode figure, evaporated metal, stripping metal form source-drain electrode in the front of P+-Si substrate successively.
Step 7, annealing in process.Under 600 ℃, annealing 2min makes the threshold voltage forward of ZnO NW FET move, and realizes the enhancement type back grid ZnO NW FET greater than zero volt.Aforementioned technical process is carried out in order, after the front at the P+-Si substrate makes source-drain electrode, whole wafer (wafer) is annealed, and its purpose is to make the device threshold voltage positive excursion.
Among the enhancement type back grid ZnO NW FET preparation method of the present invention, after the source-drain electrode of ZnO NW FET is made, also need carry out annealing in process makes the threshold voltage of ZnO NW FET device move to forward, realization is greater than the enhancement mode threshold voltage of zero volt, thereby acquisition enhancement type back grid ZnO NW is FET.Fig. 2 is the transfer characteristic curve of the ZnO NW FET device after the annealing in process among Fig. 1, and it characterizes the source-drain current change curve of ZnONW FET device under different gate voltage effects.Simultaneously, the threshold voltage of ZnO NW FET device also thus curve obtain, as can be seen from Figure 2, as gate voltage Vgs during less than 0V, source-drain current Ids is minimum, after gate voltage Vgs is greater than 0V, source-drain current Ids increases gradually, and the threshold voltage of device is an enhancement mode as can be known.
Fig. 3 is the structural representation of a kind of enhancement type back grid of the present invention ZnO NW FET.Enhancement type back grid ZnO NW FET comprises:
Grid oxygen medium SiO 2, grow in the front of P+-Si substrate;
Back-gate electrode is formed at the back side of P+-Si substrate by evaporated metal;
Telltale mark (not shown among Fig. 3) is formed at the front of P+-Si substrate;
The ZnO nano wire according to described telltale mark, is formed at the front of P+-Si substrate;
Source-drain electrode (being respectively source electrode, drain electrode among Fig. 3) is formed at the front of described P+-Si substrate.
On the above-mentioned technology basis, carry out annealing in process again, make script less than zero threshold voltage that lies prostrate, positive excursion forms the threshold voltage that lies prostrate greater than zero.Enhancement type back grid ZnO NW FET among this embodiment can adopt above-mentioned enhancement type back grid ZnO NW FET preparation method to obtain.
Enhancement type back grid ZnO NW FET preparation method provided by the invention has realized the enhancement type back grid ZnO NW FET of threshold voltage greater than zero volt.
It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.

Claims (10)

1, a kind of enhancement type back grid zinc oxide nano wire field effect transistor preparation method is characterized in that, comprising:
At the front of P+-Si substrate growth grid oxygen medium SiO 2
The back side at the P+-Si substrate forms back-gate electrode;
Front at the P+-Si substrate forms telltale mark;
Finish the transfer and the deposit of zinc oxide nanowire in the front of P+-Si substrate;
Finish the location of nano wire in the front of P+-Si substrate;
Front at the P+-Si substrate makes source-drain electrode;
Annealing in process.
2, preparation method according to claim 1 is characterized in that, and is described at the front of P+-Si substrate growth grid oxygen medium SiO 2For:
Utilize PECVD at the front of P+-Si substrate growth grid oxygen medium SiO 2
3, preparation method according to claim 1 is characterized in that, the described back side at the P+-Si substrate forms back-gate electrode and is:
Evaporated metal is passed through at the back side at the P+-Si substrate, forms back-gate electrode.
4, preparation method according to claim 1 is characterized in that, described front at the P+-Si substrate forms telltale mark and is:
Carry out photoetching telltale mark figure, evaporated metal, stripping metal in the front of P+-Si substrate successively, the cross telltale mark of the periodic arrangement of formation rule.
5, preparation method according to claim 1 is characterized in that, transfer and deposit that zinc oxide nanowire is finished in described front at the P+-Si substrate comprise:
The zinc-oxide nano wire material is soaked in the isopropyl acetone solution, adopts the ultrasonotomography technology, nano wire is come off from the growth substrates surface, be suspended in isopropyl acetone solution;
And the isopropyl acetone drips of solution that will contain zinc oxide nanowire is finished the transfer and the deposit of zinc oxide nanowire in the front of P+-Si substrate.
6, preparation method according to claim 1 is characterized in that, the location that nano wire is finished in described front at the P+-Si substrate comprises:
Under high-power microscope, observe zinc oxide nanowire, utilize cross telltale mark, the accurate position of zinc oxide nanowire is provided for the subsequent optical carving technology.
7, preparation method according to claim 1 is characterized in that, described front at the P+-Si substrate makes source-drain electrode and is: photolithographic source drain electrode figure, evaporated metal, stripping metal successively form source-drain electrode.
8, preparation method according to claim 1 is characterized in that, described annealing in process is: carry out annealing in process at 600 ℃.
9, preparation method according to claim 8 is characterized in that, the time of described annealing in process is 2 minutes.
10, a kind of enhancement type back grid zinc oxide nano wire field effect transistor is characterized in that, makes according to the arbitrary described preparation method of claim 1-9, comprising:
Grid oxygen medium SiO 2, grow in the substrate face of P+-Si device;
Back-gate electrode is formed at the substrate back of P+-Si device by evaporated metal;
Telltale mark is formed at the substrate face of P+-Si device;
Zinc oxide nanowire is positioned over the substrate face of P+-Si device;
Source-drain electrode is formed at the substrate face of described P+-Si device;
On the above-mentioned technology basis, carry out annealing in process again, make script less than zero threshold voltage that lies prostrate, positive excursion forms the threshold voltage that lies prostrate greater than zero.
CN 200810227461 2008-11-25 2008-11-25 Enhancement type back grid zinc oxide nano wire field effect transistor and method for producing the same Expired - Fee Related CN101431028B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102214577A (en) * 2010-04-09 2011-10-12 中国科学院微电子研究所 Method for manufacturing nano switch
CN107331618A (en) * 2012-12-18 2017-11-07 英特尔公司 Using orienting the vertical nanowire transistor raceway groove of self assembly and the patterning of grid

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102214577A (en) * 2010-04-09 2011-10-12 中国科学院微电子研究所 Method for manufacturing nano switch
CN107331618A (en) * 2012-12-18 2017-11-07 英特尔公司 Using orienting the vertical nanowire transistor raceway groove of self assembly and the patterning of grid
CN107331618B (en) * 2012-12-18 2020-11-27 英特尔公司 Patterning of vertical nanowire transistor channels and gates with directed self-assembly

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