CN101409546A - MOS tube switch capacitance integrator circuit - Google Patents
MOS tube switch capacitance integrator circuit Download PDFInfo
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- CN101409546A CN101409546A CNA2008102316747A CN200810231674A CN101409546A CN 101409546 A CN101409546 A CN 101409546A CN A2008102316747 A CNA2008102316747 A CN A2008102316747A CN 200810231674 A CN200810231674 A CN 200810231674A CN 101409546 A CN101409546 A CN 101409546A
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Abstract
The invention discloses a MOS tube switching capacitor integral circuit; P-typed MOS tubes M1, M2, M3 and M4 form a Cascode current mirror structure, the source electrode of the M3 is connected with a power supply, the grid electrode of the M3 is connected with the grid electrode of the M2, the drain electrode of the M3 is connected with the source electrode of the M4; the gird electrode of the M4 is connected with the grid electrode of the M1, the drain electrode of the M4 is connected with the output terminal of a reference current source Iref; the source electrode of the M2 is connected with the power supply; the drain electrode of the M2 is connected with the source electrode of the M1; the drain electrode of the M1 is connected with the output terminal; the substrates of the P-typed MOS tubes M1, M2, M3 and M4 are all connected with the power supply, the two terminals of a switch K are respectively connected with the grid electrode of the M1 and the grid electrode of the M4, or the two terminals of the switch K are respectively connected with the grid electrode of the M3 and the drain electrode of the M4. The circuit greatly improves the output precision, can be used as either a linear DAC or a non-linear DAC in the premise of changing the circuit structure and can realize any conversion precision, and can be used for either voltage driving or current driving.
Description
Technical field
The invention belongs to electronic technology field, relate to a kind of metal-oxide-semiconductor switch capacitance integrator circuit.
Background technology
The error that the integral restrictor of existing switch capacitance integrator circuit causes mainly is present in the following aspects: the first, the influence of parasitic capacitance; The second, the influence of the conducting resistance of metal-oxide-semiconductor, the improvement method has: select the bigger metal-oxide-semiconductor switch of breadth length ratio for use, or adopt cmos switch; Three, clock feedthrough and sampling spike, the improvement method has: adopt the smaller metal-oxide-semiconductor of breadth length ratio, to reduce overlap capacitance; Four, electric charge injects problem, and the improvement method has: connect a virtual metal-oxide-semiconductor at output node, or adopt cmos switch, or adopt the non-overlapping clock control switch, or adopt the integrator of full difference structure, the electric charge injection influence of two inputs is offseted.
But, no matter be to adopt above-mentioned which kind of method, can only reduce the influence that metal-oxide-semiconductor switch error is brought to a certain extent, and can not fundamentally go to solve it, this mainly be because the residing determining positions of switch integral voltage to be subjected to the influence of above-mentioned several respects.
Summary of the invention
The purpose of this invention is to provide a kind of metal-oxide-semiconductor switch capacitance integrator circuit, solved the error that the integral restrictor that exists in the prior art causes, cause the affected problem of non-ideal characteristic of metal-oxide-semiconductor switch.
The technical solution adopted in the present invention is, a kind of metal-oxide-semiconductor switch capacitance integrator circuit, P type metal-oxide-semiconductor M1, M2, M3, M4 form the Cascode current-mirror structure, the source electrode of M3 links to each other with power supply, the grid of M3 links to each other with the grid of M2, the drain electrode of M3 links to each other with the source electrode of M4, and the grid of M3 links to each other with the drain electrode of M4; The drain electrode of M4 and reference current source l
RefOutput link to each other; The source electrode of M2 links to each other with power supply, and link to each other with the source electrode of the M1 drain electrode of M1 of the drain electrode of M2 links to each other with output; The substrate of P type metal-oxide-semiconductor M1, M2, M3, M4 all is connected with power supply, and the two ends of K switch 1 link to each other with the grid of M1 and the grid of M4 respectively.
Another technical scheme of the present invention is, a kind of metal-oxide-semiconductor switch capacitance integrator circuit, P type metal-oxide-semiconductor M1, M2, M3 and M4 form the Cascode current-mirror structure together, and the source electrode of M3 links to each other with power supply, the grid of M3 links to each other with the grid of M2, and the drain electrode of M3 links to each other with the source electrode of M4; The grid of M4 links to each other with the grid of M1, the drain electrode of M4 and reference current source l
RefOutput link to each other; The source electrode of M2 links to each other with power supply, and the drain electrode of M2 links to each other with the source electrode of M1; The drain electrode of M1 connects output; The substrate of P type metal-oxide-semiconductor M1, M2, M3, M4 all is connected with power supply, and the two ends of K switch 3 are connected with the grid of M3 and the drain electrode of M4 respectively.
The invention has the beneficial effects as follows, changed the residing position of switch in the conventional MOS tube switch capacitance integrator circuit, switch is transferred in the middle of the current mirror,, just can fundamentally be eliminated the various influences that the non-ideal characteristic of metal-oxide-semiconductor switch brings as long as the parameter of switch pipe appropriately is set.
Description of drawings
Fig. 1 is the voltage cut-out integrating circuit figure of prior art;
Fig. 2 is existing Cascode current-mirror structure schematic diagram;
Fig. 3 is existing metal-oxide-semiconductor switch capacitance integrator circuit schematic diagram;
Fig. 4 is the schematic diagram of switch capacitance integrator circuit embodiment 1 of the present invention;
Fig. 5 is the schematic diagram of switch capacitance integrator circuit embodiment 2 of the present invention;
Fig. 6 is the post-layout simulation results exhibit comparison diagram of three kinds of circuit structures among Fig. 3,4,5;
Fig. 7 is three kinds of peak current schematic diagrames that mode switch causes among Fig. 3,4,5, wherein curve chart is the mode simulation result schematic diagram of Fig. 4 embodiment 1 among a, b is the existing mode simulation result schematic diagram among Fig. 3, and c is the mode simulation result schematic diagram of Fig. 5 embodiment 2.
Embodiment
The present invention is described in detail below in conjunction with the drawings and specific embodiments.
Fig. 1 is prior art voltage cut-out integrating circuit figure.C
IntIt is integrating capacitor.The error that the integral restrictor of this type circuit causes mainly is present in the following aspects:
The first, the influence of parasitic capacitance.Because integrating capacitor upper/lower electrode and substrate exist certain parasitic capacitance C
P1And C
P2, according to the difference of distance, C
P1Be generally (1%～5%) C, and C
P2Be generally 20%C.As seen a typical integrated circuit model is made up of 3 electric capacity.Because C
P2Two ends are ground connection, and influence can be ignored, and has only C
P1With C
1Be in parallel.
The second, the influence of the conducting resistance of metal-oxide-semiconductor.Since metal-oxide-semiconductor switch and non-ideal switches, the resistance non-zero during conducting, and it and integrating capacitor form the RC loop, can influence discharging and recharging the time of electric capacity, if conducting resistance will cause system to set up problems such as incomplete too greatly.In addition, conducting resistance still is the function of VG, therefore can cause certain nonlinearity erron to system.Improvement method: select the bigger metal-oxide-semiconductor switch of breadth length ratio for use, or adopt cmos switch.
Three, clock feedthrough and sampling spike.The grid source of MOS device and the grid leak utmost point exist parasitic overlap capacitance.As switch conduction (V
GBe high level) time, C
IntOriginally should be charged to V
In, but overlap capacitance can be coupled to C with the clock low level
IntOn.Can get error voltage by relation among the figure:
Another interference that clock feedthrough causes is exactly to occur due to voltage spikes in the sampling process.Because it is very fast that the clock of switch changes, fast-changing V
GOverlap capacitance by metal-oxide-semiconductor is coupled to drain electrode and source electrode.According to formula i=CdU/dt, will produce very big electric current in a short period of time, flow through electric capacity and switch (resistance) of this electric current will produce due to voltage spikes.These due to voltage spikes will run up to output by integrator, influence the precision of integrator.Improvement method: can adopt the smaller metal-oxide-semiconductor of breadth length ratio, to reduce overlap capacitance.
Four, electric charge injects problem.When the metal-oxide-semiconductor conducting, will accumulate the electric charge of some in the inversion layer under the grid oxygen, and when metal-oxide-semiconductor ended, electric charge stored in the raceway groove will flow out from the source electrode and the drain electrode of metal-oxide-semiconductor, this phenomenon is called " channel charge injection ".The channel charge that flows out can be stored on the capacitor, and condenser voltage is produced certain error.The bound-time that is injected into impedance that what of electric charge of source electrode and drain electrode leak with the source and current potential, clock all has relation.
Figure 2 shows that existing Cascode current-mirror structure schematic diagram.Among the figure
V
X＝V
b-V
GS3＝V
ov1 V
Y＝V
b-V
GS4＝V
ov2 (2)
Advance V when M3 is saturated
b-V
T3≤ V
IN=V
GS1(3)
When M1 is saturated, V
IN-V
T1=V
GS1-V
T1≤ V
X=V
b-V
GS3(4)
By (3), (4): V
GS3+ (V
GS1-V
T1)≤V
b≤ V
GS1+ V
T3(5)
During low voltage operating: V
b=V
GS3+ (V
GS1-V
T1)=V
GS4+ (V
GS2-V
T2) (6)
The drain-source voltage of M1, M2 equates that the current gain systematic error is 0.The output minimum voltage:
V
OUT(min)＝V
DS2+V
DS4≈2V
ov (7)
Therefore, the error that exists integral restrictor to cause in the existing Cascode current mirroring circuit causes the non-ideal characteristic of metal-oxide-semiconductor switch to be affected.
Fig. 3 is existing metal-oxide-semiconductor switch capacitance integrator circuit schematic diagram, the structure of this circuit comprises the Cascode current-mirror structure that P type metal-oxide-semiconductor M1, M2, M3 form, the source electrode of M3 links to each other with power supply, and the grid of M3 links to each other with the grid of M2 and the drain electrode of M4 simultaneously, and the drain electrode of M3 links to each other with the source electrode of M4; The grid of M4 links to each other with the grid of M1, the drain electrode of M4 and reference current source l
RefOutput link to each other; The source electrode of M2 links to each other with power supply, and the drain electrode of M2 links to each other with the source electrode of M1, and the drain electrode of M1 links to each other with output by K switch 2; The substrate of P type metal-oxide-semiconductor M1, M2, M3, M4 all is connected with power supply.Similar in this circuit with the structural principle of Fig. 1 and Fig. 2, therefore still there is aforesaid a series of deficiency, still do not overcome the error problem that the integral restrictor that exists in the available circuit causes.
Fig. 4 is the schematic diagram of switching circuit embodiment 1 of the present invention, comprise the Cascode current-mirror structure that P type metal-oxide-semiconductor M1, M2, M3, M4 form, the source electrode of M3 links to each other with power supply, and the grid of M3 links to each other with the grid of M2, the drain electrode of M3 links to each other with the source electrode of M4, and the grid of M3 links to each other with the drain electrode of M4; The grid of M4 links to each other with K switch 1 one ends, the drain electrode of M4 and reference current source l
RefOutput link to each other; The source electrode of M2 links to each other with power supply, and the drain electrode of M2 links to each other with the source electrode of M1; The grid of M1 links to each other with the other end of K switch 1, and the drain electrode of M1 links to each other with output; The substrate of P type metal-oxide-semiconductor M1, M2, M3, M4 all is connected with power supply.The switching circuit of present embodiment 1 is compared with the existing integrating circuit of Fig. 3, and K switch 1 is arranged between M1 and the M4.
Fig. 5 is the schematic diagram of switching circuit embodiment 2 of the present invention, comprise the Cascode current-mirror structure that P type metal-oxide-semiconductor M1, M2, M3 and M4 form together, the two ends of K switch 3 are connected with M4 with M3 respectively, the source electrode of M3 links to each other with power supply, the grid of M3 with also link to each other when the grid of M2 links to each other with an end of K switch 3, link to each other with the source electrode of the M4 grid of M4 of the drain electrode of M3 links to each other the drain electrode of M4 and reference current source l with the grid of M1
RefOutput also link to each other when linking to each other with the other end of K switch 3; The source electrode of M2 links to each other with power supply, and the drain electrode of M2 links to each other with the source electrode of M1; The drain electrode of M1 connects output; The substrate of P type metal-oxide-semiconductor M1, M2, M3, M4 all is connected with power supply.The switching circuit of present embodiment 2 is compared with the existing integrating circuit of Fig. 3, and K switch 3 is arranged between M3 and the M4.
If the embodiment circuit of the present invention in Fig. 4 and Fig. 5 as current drives, can directly link to each other with load, if as driven, the drain electrode of M1 connects integrating capacitor.In the present invention, with the voltage driving mode be its operation principle of example explanation.Fig. 4 and Fig. 5 use the constant current charge integral way.Reason is that charge to electric capacity in the working voltage source, integral voltage
It is the nonlinear function of the t time of integration; Use current source to the electric capacity charge integrate, its
It is the linear function of time t.In Fig. 3, the error that metal-oxide-semiconductor K switch 2 is brought is as several aspects of above being narrated.And Fig. 4 and Fig. 5 be placed on switch in the middle of the current mirror, significantly overcome the various influences that switch brings in Fig. 3 mode.
The switch of Fig. 4 embodiment 1 of the present invention is located in the middle of the current mirror, and when switch was in conducting state, the output current of current mirror was by metal-oxide-semiconductor M2 and M3 decision,
Though the clock feedthrough of K1 switch and channel charge inject the grid voltage that can change M1,, as long as the grid voltage V of M1
GSatisfy V
DD+ V
GS3-| V
T4|≤V
G≤ V
DD+ V
GS3+ | V
T3|+V
GS4, output current I
OutJust constant.But its current constant is constant will be at output voltage less than V
DD-| V
DS2+ V
DS1|.
The operation principle of Fig. 5 embodiment 2 of the present invention and Fig. 4 embodiment 1 basically identical, slightly different is, when switch conduction, 1 needs of embodiment give the raceway groove of M1 existing iunjected charge, and embodiment 2 needs to give the raceway groove while iunjected charge of M1, M2, therefore the circuit opening speed of embodiment 2 is relatively slow, but this is a kind of fixed delay, can remedy by supplementary circuitry.
Fig. 6 is the post-layout simulation results exhibit comparison diagram of three kinds of circuit structures among Fig. 3, Fig. 4, Fig. 5.As seen from Figure 6, the integral voltage of above-mentioned three kinds of modes is linear growth well, just in switch conduction moment, the C curve of Fig. 3 mode shows, accumulated certain electric charge owing to clock feed-through effect on the integrating capacitor, make that integral voltage can not be since 0, cause its actual measured value can be than theoretical value height; And Fig. 4 embodiment 1 mode a curve display, owing to overcome the influence of switching noise, it can well be since 0 linear growth; Fig. 5 embodiment 2 mode b curve display, though also overcome the influence of switching noise, need to give earlier the raceway groove iunjected charge of two pipes, make it to form current path, therefore opening speed is slower relatively, cause its actual measured value can be lower than theoretical value.
Fig. 7 is the peak current schematic diagram that the integral restrictor of three kinds of modes among switch conduction above-mentioned Fig. 3 of moment, Fig. 4, Fig. 5 causes separately, and curve chart is the simulation result of the existing mode among Fig. 3 among Fig. 7 b, and its peak current is up to 40uA; And curve chart is the mode of Fig. 4 embodiment 1 among Fig. 7 a, and the curve chart of Fig. 7 c is the mode of Fig. 5 embodiment 2, all has only 2uA.
Existing current switch network configuration, in switch motion, the clock feedthrough of metal-oxide-semiconductor switch and raceway groove injection can cause the variation of image current, voltage, and then cause the variation of voltage on the integrating capacitor usually.And switching network of the present invention can overcome the various influences that the metal-oxide-semiconductor switch brings, and integrating capacitor is not subjected to the influence of switch motion, and integral voltage is consistent, and this result is consistent with theory analysis.
Application example 1: the drive circuit of spatial light modulator.The feature of spatial light modulator is: nonlinear reflection spectral line, ultrafast response device speed, lower power consumption and less area.At a high speed, letter is little, high-resolution, and the output voltage of full swing is the prerequisite key property of spatial light modulator drive circuit.And switched-capacitor circuit structure of the present invention can satisfy these performances fully, after adopting switch capacitance integrator circuit of the present invention, the drive circuit area of the pixel cell of spatial light modulator only is 60um*60um, and response speed is 50KHz, and the modulation gray scale can reach 256 grades.
Application example 2:OLED drive circuit belongs to the current drives mode, by regulating the time of the charging current on the OLED, realizes different brightness.The present invention also is the constant current charge mode, when being applied to the OLED driving, only needing to replace with OLED to integrating capacitor and gets final product, and by regulating the switch on the current mirror, controls the time of charging current.
When switch capacitance integrator circuit of the present invention uses as digital to analog converter, to compare with traditional current mode, voltage-type, charge type DAC, it has following advantage: at first, it both can realize linear transformation, also can realize non-linear conversion.Secondly, on conversion accuracy, it can be realized than current mode, voltage-type, precision that the charge type digital to analog converter is higher.Current mode, voltage-type, charge type digital to analog converter are along with the improve of precision, and structure becomes increasingly complex, and power consumption is increasing, so difficultly realize high-precision conversion.And switch capacitance integrator circuit of the present invention need not change circuit structure, as long as the pulse duration of by-pass cock control signal just realizes high-precision digital-to-analogue conversion.Three, because switched-capacitor circuit structure of the present invention need not change circuit structure, just can realize the digital-to-analogue conversion of arbitrary accuracy, so it have bigger versatility and range of application.Four, switched-capacitor circuit of the present invention has overcome the various influences that switching tube brings, and is more suitable in high-precision system.
When switch capacitance integrator circuit of the present invention used as drive circuit, this circuit had very strong flexibility, removed integrating capacitor and can be used for current drives, added integrating capacitor, can be used for driven, during as current drives, can directly link to each other with load; If during as driven, the drain electrode of M1 connects integrating capacitor; The structure of current mirror is not limited to the Cascode structure, and any current gain systematic error is that 0 structure all can; The thought of utilization pulse width control, the conducting of control switch and shutoff, thus realize different integral voltage values.Switch capacitance integrator circuit of the present invention is simple in structure, and area is little, and speed is fast, and the precision height has bigger versatility and range of application.
Claims (2)
1, a kind of metal-oxide-semiconductor switch capacitance integrator circuit, P type metal-oxide-semiconductor M1, M2, M3, M4 form the Cascode current-mirror structure, and the source electrode of M3 links to each other with power supply, and the grid of M3 links to each other with the grid of M2, the drain electrode of M3 links to each other with the source electrode of M4, and the grid of M3 links to each other with the drain electrode of M4; The drain electrode of M4 and reference current source l
RefOutput link to each other; The source electrode of M2 links to each other with power supply, and link to each other with the source electrode of the M1 drain electrode of M1 of the drain electrode of M2 links to each other with output; The substrate of P type metal-oxide-semiconductor M1, M2, M3, M4 all is connected with power supply, it is characterized in that: the two ends of K switch 1 link to each other with the grid of M1 and the grid of M4 respectively.
2, a kind of metal-oxide-semiconductor switch capacitance integrator circuit, P type metal-oxide-semiconductor M1, M2, M3 and M4 form the Cascode current-mirror structure together, and the source electrode of M3 links to each other with power supply, and the grid of M3 links to each other with the grid of M2, and the drain electrode of M3 links to each other with the source electrode of M4; The grid of M4 links to each other with the grid of M1, the drain electrode of M4 and reference current source l
RefOutput link to each other; The source electrode of M2 links to each other with power supply, and the drain electrode of M2 links to each other with the source electrode of M1; The drain electrode of M1 connects output; The substrate of P type metal-oxide-semiconductor M1, M2, M3, M4 all is connected with power supply, it is characterized in that: the two ends of K switch 3 are connected with the grid of M3 and the drain electrode of M4 respectively.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008102316747A CN101409546A (en) | 2008-10-10 | 2008-10-10 | MOS tube switch capacitance integrator circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008102316747A CN101409546A (en) | 2008-10-10 | 2008-10-10 | MOS tube switch capacitance integrator circuit |
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| CN101409546A true CN101409546A (en) | 2009-04-15 |
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| CNA2008102316747A Pending CN101409546A (en) | 2008-10-10 | 2008-10-10 | MOS tube switch capacitance integrator circuit |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102377421A (en) * | 2010-07-30 | 2012-03-14 | 安森美半导体贸易公司 | Switched capacitor circuit |
| CN106027025A (en) * | 2016-06-21 | 2016-10-12 | 中国科学院上海高等研究院 | Switch capacitor integrator circuit for eliminating offset voltage |
| CN107907704A (en) * | 2017-12-14 | 2018-04-13 | 杭州百隆电子有限公司 | Tachometric survey drive circuit and method |
| CN111474412A (en) * | 2020-04-24 | 2020-07-31 | 上海艾为电子技术股份有限公司 | Capacitance detection circuit and capacitance detection method |
| CN113110692A (en) * | 2021-04-21 | 2021-07-13 | 西安交通大学 | Current mirror circuit |
-
2008
- 2008-10-10 CN CNA2008102316747A patent/CN101409546A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102377421A (en) * | 2010-07-30 | 2012-03-14 | 安森美半导体贸易公司 | Switched capacitor circuit |
| CN102377421B (en) * | 2010-07-30 | 2015-02-04 | 半导体元件工业有限责任公司 | Switched capacitor circuit |
| CN106027025A (en) * | 2016-06-21 | 2016-10-12 | 中国科学院上海高等研究院 | Switch capacitor integrator circuit for eliminating offset voltage |
| CN106027025B (en) * | 2016-06-21 | 2019-04-23 | 中国科学院上海高等研究院 | A kind of switched-capacitor integrator circuit for eliminating offset voltage |
| CN107907704A (en) * | 2017-12-14 | 2018-04-13 | 杭州百隆电子有限公司 | Tachometric survey drive circuit and method |
| CN107907704B (en) * | 2017-12-14 | 2024-02-02 | 杭州百隆电子有限公司 | Rotation speed measurement driving circuit and method |
| CN111474412A (en) * | 2020-04-24 | 2020-07-31 | 上海艾为电子技术股份有限公司 | Capacitance detection circuit and capacitance detection method |
| CN113110692A (en) * | 2021-04-21 | 2021-07-13 | 西安交通大学 | Current mirror circuit |
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Open date: 20090415 |