CN101404841B - Parallel LED driving method and system based on three-dimensional display - Google Patents
Parallel LED driving method and system based on three-dimensional display Download PDFInfo
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Abstract
The invention discloses a parallel LED drive method based on three-dimensional display and a system thereof. A whole LED screen is divided into M rows*N lists of sub-screens; each sub-screen includes I rows*j lists of color LED pipes; each sub-screen is corresponding with one drive circuit; and images on every sub-screen are all displayed in parallel. Every drive circuit sends a list of image signals in the sub-screen to a list of LEDs on the sub-screen to ensure that a list of LEDs are displayed at the same time; and the display of the images of the whole sub-screen is realized by scanning different lists in sequence. A PC machine is connected with a PCI-E bridge, an electro-optic conversion module, a photoelectric conversion module, a main control field programmable gate array, a distribution field programmable gate array, an LED drive chip and an LED screen orderly. The distribution field programmable gate array is connected with a multi-path gating apparatus module, a high power apparatus module and the LED screen. The invention realizes the high speed transmission, storage, processing and display of mass data, improves the refresh rate of the image greatly as well as the brightness and resolution of the screen.
Description
Technical field
The invention belongs to the body three-dimensional display, LED display type of drive field.Be specifically related to a kind of parallel LED driving method and system based on three-dimensional display.
Background technology
Three-dimensional display particularly real space dimension display technologies is the Display Technique that people dream of always.
The body three-dimensional display is a kind ofly can carry out the technology that image information is reproduced in a true three-dimension space that really have width, height and a degree of depth, also claims the space to load (space-filling) and shows.It encourages the material that is positioned at transparent demonstration volume by suitable mode, utilizes generation, absorption or the scattering of visible radiation and forms voxel.After the material in many orientation in the volume all is energized, just can form the 3-D view that constitutes by many dispersion voxels, float in the material world that the true three-dimension space is the observer place, it similarly is a real three-dimensional object, can satisfy nearly all physiology and psychological depth cueing automatically, can many people, multi-angle, simultaneously, bore hole observes, and need not any visual equipment that helps, and meets human natural physiologic habit aspect visual observation and depth perception.
The LED screen display is as the important way of body three-dimensional display, and the drives mode of its LED and common LED screen drive and be as different as light from darkness.LED screen driver circuit in the three-dimensional display has the volume of transmitted data of super large, ultrafast refresh rate, parallel characteristics such as transfer of data.And since existing LED chip for driving and relevant drive circuit all make towards two-dimentional LED screen design, these all can't satisfy the requirement of parameters in the three-dimensional display, therefore, use existing LED chip for driving and relevant circuit to realize the parameter request of LED driving screen in the three-dimensional display, just the driven in series mode that adopts in the current LED screen must be changed, and a kind of LED type of drive of high degree of parallelism completely newly must be designed.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art, a kind of parallel LED driving method and system based on three-dimensional display is provided.
Parallel LED driving method based on three-dimensional display comprises the steps:
1) the whole LED screen resolve into M capable * a N row sub-screen, each sub-screen all contain i capable * a j row color LED pipe, all corresponding drive circuit of each sub-screen, the image of each sub-screen is parallel simultaneously to be shown;
2) each drive circuit is sent to the row picture signal in the sub-screen on the row of one on the sub-screen LED simultaneously, and a row LED is shown simultaneously, and the image of whole sub-screen shows that the scanning successively by different lines realizes;
3) image of each sub-screen demonstration is bianry image, and gray scale image is realized by the sequential stack of bianry image;
4) the demonstration time of each row LED is 1/[R * F * (2
x-1) * j] second, wherein R be motor speed (revolutions per second), F is the screen institute's updated images number that rotates a circle, x is the gray scale figure place of each image, the demonstration time of each sub-screen is 1/[R * F * (2
x-1)] second;
5) three-dimensional body that will show is divided equally rule by angle and radially cut out F cross section, each cross section is as the piece image of LED display, each image be cut into M capable * N row number of sub images, the data of each subimage are delivered to the corresponding LED drive circuit respectively.
Based on the PC in the parallel LED drive system of three-dimensional display successively with the PCI-E bridge, group is touched in the electric light conversion, opto-electronic conversion is touched group, the master control field programmable gate array, the distribution field programmable gate array, the LED chip for driving, the LED screen is connected, the distribution field programmable gate array successively with multi channel selecting device module, the high power device module, the LED screen is connected, the LED sub-screen is as circuit board 1, the LED chip for driving, multi channel selecting device module, the high power device module is as circuit board 2, the distribution field programmable logic array is as circuit board 3, and the master control field programmable logic array is as circuit board 4.
Described circuit board 1 is connected with circuit board 2, circuit board 3 successively, and circuit board 1, circuit board 2 and circuit board 3 are formed a driver module, the circuit board of whole system comprise M capable * a N row driver module, driver module is connected with circuit board 4.
It is capable that the arrangement mode of LED sub-screen is that three-color LED is arranged as horizontal i, vertically the j row.
The LED sub-screen is divided into that to contain Y capable, a plurality of submodules of Z row LED, and wherein i is the integral multiple of Y, j is the integral multiple of Z.
The internal module annexation of master control field programmable gate array is: master control FPGA is connected with power supply device, master control FPGA is connected with parallel data receiving interface, a plurality of parallel data transmission interface, a plurality of parallel instruction transmission interface, 16bit parallel port, configuration device, download cable plug respectively, the 16bit parallel port is connected with data storage, and the download cable plug is connected with configuration device.The master control field programmable gate array is connected with a plurality of distribution field programmable gate arrays, controls a plurality of distribution field programmable gate arrays simultaneously.
The internal module annexation of distribution field programmable gate array is: distribution FPGA is connected with power supply device, parallel data receiving interface, parallel instruction receiving interface, a plurality of parallel data transmission interface, a plurality of parallel instruction transmission interface, 16bit parallel port, configuration device, download cable plug, the 16bit parallel port is connected with data storage, and the download cable plug is connected with configuration device.The distribution field programmable gate array is connected with a plurality of LED chip for driving, controls a plurality of LED chip for driving simultaneously.
Each output of LED chip for driving is connected with the anode of the homochromy LED of delegation, and the different outputs of each LED chip for driving are connected with the anode of the LED of the different rows of same color.
The internal module annexation of high power device module is: CEM4953 chip the 1st pin is connected with power vd D, the 2nd pin is connected with an end of the 1st resistance, the 3rd pin is connected with power vd D, the 4th pin is connected with an end of the 2nd resistance, and the 5th pin is connected with the 6th pin, and the 6th pin is connected with an end of the 3rd resistance, the other end of the 3rd resistance is connected with ground, the 7th pin is connected with an end of the 4th resistance, and the other end of the 4th resistance is connected with ground, and the 8th pin is connected with the 7th pin.
Each output of high power device module is connected with the negative electrode of a row LED, and the different outputs of each high power device module are connected with the negative electrode of the LED of different lines.
The beneficial effect that the present invention compared with prior art has:
1) high-speed transfer of realization mass data, storage is handled and demonstration.
2) multiple row LED light simultaneously by column scan, compare with conventional serial driving LED Circuits System, greatly improved the refresh rate of every width of cloth image, increased LED lighting the time in a display cycle, improve image and change frequency, it is big to satisfy three-dimensional display voxel amount, shows that tangent plane is many, the requirement that refreshing frequency is fast.
3) adopt three-color LED as display pixel, drive between the three-color LED can be adjusted the white balance of display screen easily.
4) can adopt the method for interpolation on the basis of existing screen, to improve screen resolution.
5) adopt a plurality of high power device modules, the brightness that has improved the LED screen greatly.
When 6) the LED screen is as the two-dimensional display curtain, greatly improved sophistication, resolution and the refreshing frequency of screen.
Description of drawings
Fig. 1 is the structural representation of parallel LED drive system of the adaptation mass data high-speed transfer of three-dimensional display;
Fig. 2 is a led drive circuit structural representation of the present invention;
Fig. 3 is the annexation end view of drive circuit board of the present invention;
Fig. 4 is the annexation front view of drive circuit board of the present invention;
Fig. 5 is a sub-screen LED line of pixels array structure schematic diagram of the present invention;
Fig. 6 is a sub-screen neutron Module Division schematic diagram of the present invention;
Fig. 7 is a master control FPGA modular circuit block diagram of the present invention;
Fig. 8 is that the present invention distributes FPGA modular circuit block diagram;
Fig. 9 is the block diagram that concerns that drives among the present invention between the LED chip for driving of monochromatic LED and the LED;
Figure 10 is that the high power device in the design example of the present invention is touched the inner annexation figure of group;
Figure 11 concerns block diagram between high power device module and the LED among the present invention;
Figure 12 be in the design example of the present invention by distribution FPGA through LED chip for driving circuit diagram to LED;
Figure 13 be in the design example of the present invention by distribution FPGA through multi channel selecting device circuit diagram to high power device.
Embodiment
Parallel LED driving method based on three-dimensional display comprises the steps:
1) the whole LED screen resolve into M capable * a N row sub-screen, each sub-screen all contain i capable * a j row color LED pipe, all corresponding drive circuit of each sub-screen, the image of each sub-screen is parallel simultaneously to be shown;
2) each drive circuit is sent to the row picture signal in the sub-screen on the row of one on the sub-screen LED simultaneously, and a row LED is shown simultaneously, and the image of whole sub-screen shows that the scanning successively by different lines realizes;
3) image of each sub-screen demonstration is bianry image, and gray scale image is realized by the sequential stack of bianry image;
4) the demonstration time of each row LED is 1/[R * F * (2
x-1) * j] second, wherein R be motor speed (revolutions per second), F is the screen institute's updated images number that rotates a circle, x is the gray scale figure place of each image, the demonstration time of each sub-screen is 1/[R * F * (2
x-1)] second;
5) three-dimensional body that will show is divided equally rule by angle and radially cut out F cross section, each cross section is as the piece image of LED display, each image be cut into M capable * N row number of sub images, the data of each subimage are delivered to the corresponding LED drive circuit respectively.
As shown in Figure 1, PC in the parallel LED drive system of the adaptation mass data high-speed transfer of three-dimensional display touches with the conversion of PCI-E bridge, electric light that group, opto-electronic conversion are touched group, master control field programmable gate array, distributed field programmable gate array successively, LED chip for driving, LED screen are connected, and distributes field programmable gate array and is connected with multi channel selecting device module, high power device module, LED screen successively.
The three-dimensional scenic uncorrected data of handling well is stored in the PC, PC transmits data wherein out by the PCI-E bridge when needing the three-dimensional display data, become light signal by electrooptic conversion module after data are handled and transmit in optical fiber in the PCI-E bridge, data-signal is through being reduced to the signal of telecommunication by light signal after the electric light conversion module and being read and store by master control FPGA.After the transfer of data through a two field picture, master control FPGA handles the data of having stored and distributes, and parallel transmission is distributed FPGA to each.Each distribution FPGA is from master control FPGA reading of data and store.After the instruction of receiving master control FPGA, the data that distribution FPGA will store are handled and are distributed, and parallel transmission is given each coupled LED chip for driving.The LED chip for driving that links to each other with the LED negative electrode is reading displayed data and idsplay order from distribution FPGA, produces high-low level at each output according to data command.Four I/O ports of distribution FPGA are connected with four output gating ends of multi channel selecting device, and the output that multichannel is selected to translate device is connected with the Enable Pin of high power device, and the high power device output links to each other with the anode of LED.
From PC to the opto-electronic conversion module is the data high-speed hop.Begin to LED screen circuit to realizing the supper-fast parallel part of lighting of LED screen among the present invention from the master control field programmable gate array, being red font part among Fig. 1, is the core that the present invention realizes the parallel LED drive circuit system design that realization mass data high-speed transfer shows in the three-dimensional display.
Because the circuit element numbers of poles is many in the three-dimensional display drive system, can't hold all circuit elements in the circuit board consistent with the LED screen size, therefore, the method that adopts the polylith circuit board to separate among the present invention solves the problem of circuit board space deficiency.As shown in Figure 2, with the LED sub-screen as circuit board 1, the LED chip for driving, multi channel selecting device module, high power device module be as circuit board 2, the distribution field programmable logic array is as circuit board 3, the master control field programmable logic array is as circuit board 4.The row's of employing pin or flexible cord are connected between the circuit board.Master control FPGA is connected with distribution FPGA, LED chip for driving, LED screen successively.Distribution FPGA is connected with multi channel selecting device module, high power device module, LED screen successively.Circuit board 1, circuit board 2, circuit board 3 is formed a driver module.
As Fig. 3, shown in Figure 4, the whole LED screen divider be M capable * a N row LED sub-screen, each LED sub-screen comprises a driver module, all driver modules all are connected with circuit board 4.Because the numbers of poles of LED pixel is many in the display screen, and the driving force of drive circuit is limited.Can adopt the parallel mode of a plurality of sub-screens to solve this problem, whole screen is divided into M * N sub-screen.Adopting RGB three looks integrated great power LED in the practical operation of the present invention is RF-W2S198TS-A27 type LED, screen is long: height=5:4, the screen parameter of design: 320 row * 256 row * three looks, LED Rotation screen rotating speed is that per second 15 changes, the three-dimensional display number of voxels reaches 6.29 thousand ten thousand.Each filtergram vegetarian refreshments adopts 2bit data to show its gray scale on the screen, and the gray scale of 2bit by 3 independently display surface finish.The present invention is divided into 20 sub-screens of 4 row, 5 row to the whole LED screen, and promptly to contain LED64 capable for each sub-screen, 64 row.
As shown in Figure 5, it is capable that the arrangement mode of LED sub-screen is that three-color LED is arranged as horizontal i, vertically the j row.It is capable that the whole LED sub-screen contains LED pixel i, and j row, LED carry out the address according to residing position and demarcate.LED as fifth line the 6th row is LED65.
As shown in Figure 6, the LED sub-screen is divided into that to contain Y capable, a plurality of submodules of Z row LED.Each sub-screen is divided into 4 submodules again among the present invention, and promptly per 16 row * 64 row are as the control unit submodule of a minimum.Each submodule obtains simultaneously under the control of FPGA, the storage data, and light LED simultaneously.With respect to common serial LED drive pattern, the driving method among the present invention has improved 80 times with the degree of parallelism of data.
As shown in Figure 7, the internal module annexation of master control field programmable gate array is: master control FPGA is connected with power supply device, master control FPGA is connected with parallel data receiving interface, a plurality of parallel data transmission interface, a plurality of parallel instruction transmission interface, 16bit parallel port, configuration device, download cable plug respectively, the 16bit parallel port is connected with data storage, and the download cable plug is connected with configuration device.
The present invention programmes to configuring chip by download cable.Configuring chip through programming is programmed to master control FPGA.Master control FPGA by parallel data grabbing card from electric light modulus of conversion group of received video data, when receiving data the data that receive are stored in the data storage by the parallel port of 16bit, when the data volume in the data storage reaches a frame, data in the data storage are read in master control FPGA by the 16bit parallel port handle distribution, treated data are transferred to corresponding distribution FPGA by the parallel data transmission interface, give distribution FPGA by the instruction of parallel instruction transmission interface transmitting and receiving data simultaneously.Master control FPGA is by a plurality of parallel data transmission interfaces and a plurality of distribution FPGA of instruction transmission interface control.
As shown in Figure 8, the internal module annexation of distribution field programmable gate array is: distribution FPGA is connected with power supply device, parallel data receiving interface, parallel instruction receiving interface, a plurality of parallel data transmission interface, a plurality of parallel instruction transmission interface, 16bit parallel port, configuration device, download cable plug, the 16bit parallel port is connected with data storage, and the download cable plug is connected with configuration device.
The present invention programmes to configuring chip by download cable.Configuring chip through programming is programmed to distribution FPGA.Distribution FPGA receives the Data Receiving instruction of sending from master control FPGA by the parallel instruction receiving interface, receive video data by parallel data grabbing card from master control FPGA then, when receiving data the data that receive are stored in the data storage by the parallel port of 16bit, when the data volume in the data storage reaches a frame, data in the data storage are read in distribution FPGA and data are handled distribution by the 16bit parallel port, treated data are transferred to corresponding LED chip for driving by the parallel data transmission interface, give the LED chip for driving by the instruction of parallel instruction transmission interface transmitting and receiving data and video data simultaneously.Distribution FPGA selects by the path of parallel instruction transmission interface control multi channel selecting control device.Distribution FPGA controls a plurality of LED chip for driving and 1 multi channel selecting control device by a plurality of parallel data transmission interfaces and instruction transmission interface.To contain LED64 capable for each sub-screen among the present invention, 64 row, and the data traffic of calculating each sub-screen is 3,000,000 bit, contains 3 distribution FPGA in the drive circuit of each sub-screen.
Be illustrated in figure 9 as among the present invention the block diagram that concerns between the LED chip for driving that drives monochromatic LED and the LED.The LED that adopts among the present invention is RGB three looks integrated LED.Each LED chip for driving is the LED of a kind of color of control separately, and each LED needs 3 LED chip for driving to control.Red LED is connected with an output pin of same LED chip for driving as every row.Each LED chip for driving can be controlled the data of the capable homochromy LED of n, and wherein n is the output pin number of the LED chip for driving that adopted.Each parallel submodule 16 row LED lights by row in the present invention, and the time that every row LED once lights is: 1/ (15 change * 512 * 4 gray scales expresses * 16 row)=2ms, the time that a sub-picture is lighted is 1/ (512 * 15 * 4)=32ms.According to the LED chip for driving of the multiple current main-stream of above parameter comparison, select the TLC5924 of TI company among the present invention as led driver.TLC5924 is the single channel input, the led driver spare of 16 passages output.Link to each other with the same a kind of color among the RGB of 16 LED of delegation in output pin of TLC5924 and certain submodule, 16 output pins of same TLC5924 connect the LED with a kind of color.Be that per 16 row * 16 row LED need 3 TLC5924, then each submodule needs 3 * 4=12 TLC5924, and whole sub-screen needs 12 * 4=48 TLC5924 as led driver spare.
As shown in figure 10 for being to concern block diagram between high power device module and the LED among the present invention.The power that adopts a plurality of high power devices to solve LED One's name is legion and each LED as the current source of driving LED among the present invention all brings the problem of the serious load of system more greatly.A path of each high power device links to each other with the anode of a row LED.Break-make by control high power device output channel realizes that the column selection of LED is logical.According to LED current characteristics and sub-screen parameter, adopt among the present invention to have two passages, the CEM4953 of every channels drive ability 4.9A is as current driving apparatus, according to the number of its driving force and the definite power tube that uses of LED size of current.The anode of 64 three-color LEDs of each CEM4953 passage and a row links to each other in the present invention.When every look LED electric current was 20mA, the electric current that the passage of single CEM4953 passes through was 20 * 3 * 64=3.84A.
As shown in figure 11, the internal module annexation of high power device module is: CEM4953 chip the 1st pin is connected with power vd D, the 2nd pin is connected with an end of the 1st resistance R 1, the 3rd pin is connected with power vd D, the 4th pin is connected with an end of the 2nd resistance R 2, the 5th pin is connected with the 6th pin, the 6th pin is connected with an end of the 3rd resistance R 3, the other end of the 3rd resistance R 3 is connected with ground, the 7th pin is connected with an end of the 4th resistance R 4, the other end of the 4th resistance R 4 is connected with ground, and the 8th pin is connected with the 7th pin.Control the break-make of the 8th pin by the level of controlling the 2nd pin, control the break-make of the 5th pin by the level of controlling the 4th pin.
Because LED scanning duty ratio is 1/16 among the present invention, therefore need the decoder of one 16 road gating to control the gating of LED, adopt SNSN74HC154 as gating device.Distribution FPGA is connected with 4 output channel strobe pin of SNSN74HC154, each output of SNSN74HC154 is connected with the passage Enable Pin of high power device CEM4953, distribution FPGA selects the output of different SNSN74HC154 by 4 gating signals, promptly select the path that enables of different high power device CEM4963, the row LED that the LED of selection different lines lights as current time.
Main components and parts kind of the circuit part of each sub-screen correspondence and quantity are among the present invention: three distribution FPGA, a SNSN74HC154,48 TLC5924,32 CEM4953.
As shown in figure 12 in the design example of the present invention by distribution FPGA through the circuit connection diagram of LED chip for driving to LED.The control pin of TLC5924 is connected with distribution FPGA.Arrange the BLANK control pin of 45 pin of distribution FPGA through programming as TLC5924, link to each other with the crus secunda of all TLC5924 in the sub-screen, whether control all TLC5924 works, when BLANK control pin output low level, all TLC5924 quit work, when it was high level, TLC5924 was in the state that can light LED.46 pin of distribution FPGA are as the XLAT control pin of TLC5924, link to each other with the tripod of TLC5924 in the sub-screen, when XLAT control pin output high level, TLC5924 receives data and also writes register, when it was low level, TLC5924 got up the data latching of accepting.47 pin of distribution FPGA link to each other with the 4th pin of all TLC5924 in the sub-screen as the SCLK control pin of TLC5924, unified clock signal are provided for all TLC5924.48 pin of distribution FPGA are as the MODE control pin of TLC5924, link to each other with the 30th pin of all TLC5924 in the sub-screen, when the MODE control end is high level, thereby, TLC5924 adjusts the white balance that gray scale that output current control LED lights is adjusted screen thereby accepting data, when it was low level, TLC5924 was distributed the FPGA Control work in normal condition.49 pin of distribution FPGA are to 64 pin, and 16 pins link to each other with the 5th pin of 16 TLC5924 in the sub-screen respectively as data output end altogether, be respectively 16 TLC5924 video data is provided.
The 1st, 9,14,19 of TLC5924,24 pin are earth terminal, and the 32nd pin is for connecing power end.Its 31 pin links to each other the other end ground connection of controlling resistance for control output current end with an end of controlling resistance.One section of the 6th pin and an electric capacity links to each other another termination power of this electric capacity.All the other pins are the driving path that links to each other with LED.Link to each other with the negative electrode of current submodule respectively with the LED of delegation.Each TLC5924 controls a kind of LED of color, and all outputs link to each other with 16 homochromy LED, make the transmission of data, handles and the distribution simplification, reduces the workload of IC device; Simultaneously, TLC5924 has gray scale and adjusts function, by distribution FPGA the data of the MODE end of each TLC5924 is write and controls the LED that links to each other with TLC5924, thereby realize the purpose of adjustment white balance.The pin 6,7,8 of TLC5924r is respectively as the 1st, 2, the driving path of 3 row red LED, and the 6th pin links to each other with the negative electrode of RA1 and RB1, and the 7th pin links to each other with the negative electrode of RA2 and RB2, and the 8th pin links to each other with the negative electrode of RA3 and RB3.All drive passage and want to be connected with the negative electrode of all homochromy LED of delegation in the side circuit with one.Same TLC5924g and TLC5924b adopt same connected mode with green, and blue LED connects.
That the LED in the design example of the present invention adopts is three looks integrated LED, and the LED of three kinds of colors has same anode.The anode of one row LED all links to each other and is connected on the path of CEM4953a, and this path provides electric current for the LED of respective column.As shown in figure 11, the 1st pin of CEM4953a is connected with power vd D, the 2nd pin is connected with an end of the 1st resistance R 1, and the 3rd pin is connected with power vd D, and the 4th pin is connected with an end of the 2nd resistance R 2, the 5th pin is connected with the 6th pin, the 6th pin is connected with an end of the 3rd resistance R 3, and the other end of the 3rd resistance R 3 is connected with ground, and the 7th pin is connected with an end of the 4th resistance R 4, the other end of the 4th resistance R 4 is connected with ground, and the 8th pin is connected with the 7th pin.
As shown in figure 13 in the design example of the present invention by distribution FPGA through the circuit connection diagram of multi channel selecting device to high power device.The 24th, 25,26,27 four pins of distribution FPGA are as the logical control end of lighting of control LED column selection, and 23,22,21,20 pin with 4-16 gate SN74HC154 link to each other respectively.The 28th pin of distribution FPGA links to each other with 19 pin of SN74HC154 as the control end whether control SN74HC154 works.The 18th, the 12 pin ground connection of SNSN74HC154,24 pin connect power supply.Except that the 12nd pin, totally 16 pins conducts of the 1st to the 17th pin is linked to each other with the path Enable Pin of CEM4953 by 16 paths of gating.As shown in Figure 9, the 1st pin of SN74HC154 links to each other with the 2nd pin of CEM4953a, the 8th pin of control CEM4953a, current channel as first row, the 2nd pin of SN74HC154 links to each other with the 4th pin of CEM4953a, and the 5th pin of control CEM4953a is as the current channel of secondary series; By that analogy.FPGA provides 4 control signals by distribution, its output is carried out 16 select 1 circuit control.As the output Y1 of SNSN74HC154 by gating the time, CEM4953a the 8th pin that links to each other with Y1 enables, and then the respective column LED that is connected with CEM4953a the 8th pin is lighted.When the output Y1 of SNSN74HC154 time Y15 gating successively, 16 row LED of LED screen realize that column scans light.Because each sub-screen is divided into four submodules, the data parallel transmission between the submodule.The output pin of each decoder is connected with the control pin of 4 power tube CEM4953, and the control pin of the LED power tube of X row links to each other in X output pin and the control submodule.Synchronization has 4 row LED to light simultaneously in the sub-screen.16 output pins enable successively according to programmed order, can realize lighting by row of LED.
In the submodule, 16 row LED light in turn, and the duty ratio that every row LED lights is 1/16, and the respective column of each submodule is lighted simultaneously, light time quantum through 16, and all pixels of whole sub-screen are lighted once.Owing to be parallel the existence between each sub-screen, therefore, synchronization, whole screen have 20 sub-screens * 4 submodules * 64 row LED * RGB, three looks=15360 look LED.
The BLANK of TLC5924, XLAT, the output control pin of SCLK and the public FPGA of MODE control end.The SIN input of each TLC5924 takies the output control pin of a FPGA separately.Consider the driving force of the single pin of distribution FPGA, in the design example of the present invention in the sub-screen TLC5924 be divided into three groups of RGB according to the color of its driving LED, every group BLANK, XLAT, SCLK and MODE control pin all link to each other with the same pin of distribution FPGA.The data input pin SIN of TLC5924 provides different control signals by distribution FPGA.Because TLC5924 is the driving element of serial input, realize that in order to make the LED screen gray scale shows, adopt the image that replaces the many GTGs of a width of cloth with several single gray level images among the present invention.The gray scale of each pixel monochrome is 2bit among the present invention, then adopts 3 width of cloth list image gray to express the gray scale of 2bit, as 3 bright graphical representations of gray scale 11 usefulness; 2 bright images of 10 usefulness, the dark graphical representation of a width of cloth, 1 bright image of 01 usefulness and the dark graphical representation of 2 width of cloth; The dark graphical representation of 00 usefulness, 3 width of cloth.If adopt other gray scale, then according to gray value being carried out corresponding one by one the demonstration with upper type.
The circuit of design example of the present invention connects signal as Figure 12, shown in 13, realizes that LED screen multiple row is parallel, lights by column scan.
Adopting LED type of drive of the present invention, can perform to the performance of existing led driver spare ultimate attainmently, considerably beyond the performance that present employed LED type of drive can reach, is at present, the type of drive of unique adaptation three-dimensional display LED screen.
LED screen type of drive among the present invention is the high-speed parallel type of drive that adapts to the three-dimensional LED screen, it is equally applicable to the demonstration of two-dimentional LED screen, compare with the current LED driving method that generally uses, type of drive among the present invention can tens of times, it drives speed and screen refresh rate the raising of hundreds of times, make the LED display curtain can show bigger resolution, finer and smoother picture.For the present invention, the performance parameter of the LED chip for driving that is adopted is only the bottleneck of LED screen display speed, along with improving constantly of employing chip for driving driving force, the driving force of the type of drive among the present invention and actuating speed are along with improving constantly.
Claims (1)
1. the parallel LED driving method based on three-dimensional display is characterized in that comprising the steps:
1) the whole LED screen resolve into M capable * a N row sub-screen, each sub-screen all contain i capable * a j row color LED pipe, all corresponding drive circuit of each sub-screen, the image of each sub-screen is parallel simultaneously to be shown;
2) each drive circuit is sent to the row picture signal in the sub-screen on the row of one on the sub-screen LED simultaneously, and a row LED is shown simultaneously, and the image of whole sub-screen shows that the scanning successively by different lines realizes;
3) image of each sub-screen demonstration is bianry image, and gray scale image is realized by the sequential stack of bianry image;
4) the demonstration time of each row LED is 1/[R * F * (2
x-1) * j] second, wherein R is a motor speed, and F is the screen institute's updated images number that rotates a circle, and x is the gray scale figure place of each image, and the demonstration time of each sub-screen is 1/[R * F * (2
x-1)] second;
5) three-dimensional body that will show is divided equally rule by angle and radially cut out F cross section, each cross section is as the piece image of LED display, each image be cut into M capable * N row number of sub images, the data of each subimage are delivered to the corresponding LED drive circuit respectively.
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| JP2011100068A (en) * | 2009-11-09 | 2011-05-19 | Sanyo Electric Co Ltd | Display driving circuit and display driving system |
| JP5479854B2 (en) * | 2009-11-09 | 2014-04-23 | 三洋電機株式会社 | Display drive circuit and display drive system |
| CN101783914B (en) * | 2010-01-12 | 2011-08-31 | 利亚德光电股份有限公司 | Mainboard device of display board circuit of LED (Light Emitting Diode) panel TV set |
| CN202332225U (en) * | 2011-11-28 | 2012-07-11 | 郑州中原显示技术有限公司 | 3D (Three-dimensional) LED (Light Emitting Diode) display system |
| CN102663978A (en) * | 2012-05-18 | 2012-09-12 | 华东师范大学 | Swept volume three-dimensional display device |
| DE102017105377A1 (en) * | 2016-03-17 | 2017-09-21 | Jtekt Corporation | Control console for machine tools and machine tool management system |
| CN108281108A (en) * | 2018-03-19 | 2018-07-13 | 南京信息工程大学 | A kind of all-colour LED array drive device based on FPGA |
| CN109448599B (en) * | 2018-11-27 | 2019-10-15 | 黑龙江大学 | A kind of aerial virtually sand table system and methods of exhibiting |
| CN112562558B (en) * | 2019-09-10 | 2023-01-13 | 京东方科技集团股份有限公司 | Display device, driving method thereof and driving device thereof |
| US11798510B2 (en) | 2019-09-11 | 2023-10-24 | Beijing Boe Optoelectronics Technology Co., Ltd. | Display apparatus and driving method thereof |
| CN110910794B (en) * | 2019-11-28 | 2024-05-17 | 中国科学院苏州生物医学工程技术研究所 | Multi-motor three-dimensional display device based on cascade topology |
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| CN101162560A (en) * | 2006-10-11 | 2008-04-16 | 梁忱 | Three-dimensional LED display apparatus |
| CN101217022A (en) * | 2008-01-04 | 2008-07-09 | 深圳市奥拓电子有限公司 | A LED display screen display calibration system and calibration method |
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| CN101162560A (en) * | 2006-10-11 | 2008-04-16 | 梁忱 | Three-dimensional LED display apparatus |
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