CN101385151A - Lateral power transistor with self-biasing electrodes - Google Patents
Lateral power transistor with self-biasing electrodes Download PDFInfo
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- CN101385151A CN101385151A CN200780005748.9A CN200780005748A CN101385151A CN 101385151 A CN101385151 A CN 101385151A CN 200780005748 A CN200780005748 A CN 200780005748A CN 101385151 A CN101385151 A CN 101385151A
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Abstract
A semiconductor power transistor includes a drift region of a first conductivity type and a well region of a second conductivity type in the drift region such that the well region and the drift region form a pn junction therebetween. A first highly doped silicon region of the first conductivity type is in the well region, and a second highly doped silicon region is in the drift region. The second highly doped silicon region is laterally spaced from the well region such that upon biasing the transistor in a conducting state, a current flows laterally between first and second highly doped silicon regions through the drift region. Each of a plurality of trenches extending into the drift region perpendicular to the current flow includes a dielectric layer lining at least a portion of the trench sidewalls and at least one conductive electrode.
Description
The cross reference of related application
The application requires the U.S. Provisional Application the 60/774th of submitting on February 16th, 2006, the rights and interests of No. 900, and it is openly incorporated into this by quoting as proof.
The U. S. application the 10/269th of submitting on October 3rd, 2002, No. 126 and the U. S. application the 10/951st submitted to September 26 in 2004, be also incorporated into this by quoting as proof No. 259.
Background technology
The application relates to semiconductor power device, more specifically, relates to the lateral power with the automatic bias electrode being integrated into wherein.Fig. 1 illustrates the viewgraph of cross-section of traditional (Silicon-on-insulator) MOSFET lateral 100.Extend on highly doped N-type district 102 light dope N-type drift region 104.By spaced P type tagma 106, N-type lightly doped drain (LDD) district of horizontal expansion and highly doped N-type drain region 114, be all formed in drift region 104.In tagma 106, form highly doped N-type source region 110, and in tagma 106, form heavy body (heavybody) district 108.Grid 118 extends on the surface in tagma 106, and the 110He LDD district, source region 112 that partly overlaps.Grid 118 is by gate insulator 116 and the region insulation below it.The part in the tagma under grid 118 106 forms MOSFET channel region 120 directly.
During operation, when descending in working order MOSFET 100 to be bias voltage, electric current laterally flows to drain region 114 by 112Cong source region, 120He LDD district, channel region 110.As most conventional MOS FET, the improvement in performance of (Silicon-on-insulator) MOSFET lateral 100 is limited to the competition object of the higher blocking ability of realization and lower conducting resistance (Rdson).Although LDD district 112 produces improved Rdson, this improvement is limited to transistorized blocking ability.The degree of depth that for example doping content in ，LDD district 112 and LDD district can extend is all strictly limited to breakdown voltage transistor.
These are also present in the obstruction of improvement in performance in the lateral power of other types, for example, and transversal I GBT, horizontal pn diode and lateral direction schottky diode.Therefore, exist for the demand of technology that can improve thus blocking ability, conducting resistance and other performance parameters of multiclass lateral power.
Summary of the invention
According to embodiments of the invention, semiconductor power transistor comprises the drift region of the first conductivity type and the well region of the second conductivity type in this drift region, makes to form pn between well region and drift region and ties.The first highly doped silicon area (silicon region) of the first conductivity type is in well region, and the second highly doped silicon area is in drift region.The second highly doped silicon area and well region laterally separate, once make, under conduction state, bias voltage is added to transistor, electric current just laterally flows between the first highly doped silicon area and the second highly doped silicon area by drift region.Each groove that extends to a plurality of grooves in drift region perpendicular to electric current includes dielectric layer and at least one conductive electrode that covers at least a portion that is lining in trenched side-wall.
According to another embodiment of the present invention, semiconductor diode comprises the drift region of the first conductivity type and the anode region of the second conductivity type in this drift region, makes to form pn between anode region and drift region and ties.The first highly doped silicon area of the first conductivity type is in drift region, and laterally separate with anode region, once make, under conduction state, bias voltage is added to semiconducter power diode, electric current just laterally flows between anode region and the first highly doped silicon area by drift region.Each groove that extends to a plurality of grooves in drift region perpendicular to electric current comprises dielectric layer and at least one conductive electrode that covers at least a portion that is lining in trenched side-wall.
According to another embodiment of the present invention, Schottky diode comprises the drift region of the first conductivity type and the light dope silicon area of the first conductivity type in this drift region.Conductor layer extends and contacts with this light dope silicon area on light dope silicon area, with between form Schottky contacts.Highly doped silicon area and the light dope silicon area of the first conductivity type in drift region laterally separate, once make, under conduction state, bias voltage is added to Schottky diode, electric current just laterally flows between light dope silicon area and highly doped silicon area by drift region.Each groove that extends to a plurality of grooves in drift region perpendicular to electric current comprises dielectric layer and at least one conductive electrode that covers at least a portion that is lining in trenched side-wall.
According to another embodiment of the present invention, as got off, form semiconductor transistor.In drift region, form well region, with between form pn knot.Drift region is the first conductivity type, and well region is the second conductivity type.In well region, form the first highly doped silicon area of the first conductivity type.In drift region, form the second highly doped silicon area.The second highly doped silicon area and well region laterally separate, once make, under conduction state, bias voltage is added to semiconductor transistor, electric current just laterally flows between the first highly doped silicon area and the second highly doped silicon area by drift region.Formation is perpendicular to a plurality of grooves in drift region that extend to of electric current.The dielectric layer of at least a portion that is lining in trenched side-wall is covered in formation.In each groove, form at least one conductive electrode.
According to another embodiment of the present invention, as got off, form semiconductor diode.In drift region, form anode region, with between form pn knot.Drift region is the first conductivity type, and anode region is the second conductivity type.In drift region, form the first highly doped silicon area of the first conductivity type.In the first highly doped silicon area and anode region, laterally separate, once make, under conduction state, bias voltage is added to semiconducter power diode, electric current just laterally flows between anode region and the first highly doped silicon area by drift region.
According to another embodiment of the present invention, as got off, form Schottky diode.In the drift region of the first conductivity type, form the light dope silicon area of the first conductivity type.Be formed on light dope silicon area the conductor layer that extends and contact with this light dope silicon area, with between form Schottky contacts.In drift region, form the highly doped silicon area of the first conductivity type.Highly doped silicon area and light dope silicon area laterally separate, once make, under conduction state, bias voltage is added to Schottky diode, electric current just laterally flows between light dope silicon area and highly doped silicon area by drift region.Formation is perpendicular to a plurality of grooves in drift region that extend to of electric current.The dielectric layer of at least a portion that is lining in trenched side-wall is covered in formation.In each groove, form at least one conductive electrode.
Accompanying drawing explanation
Fig. 1 illustrates the viewgraph of cross-section of the simplification of traditional (Silicon-on-insulator) MOSFET lateral 100;
Fig. 2 and Fig. 3 illustrate the viewgraph of cross-section of the simplification of the (Silicon-on-insulator) MOSFET lateral structure according to an exemplary embodiment of the present invention with two different automatic bias electrode structures that are integrated into wherein;
Fig. 4 and Fig. 5 are the simulation results that the Electric Field Distribution in the drift region of conventional MOS FET in Fig. 1 and the exemplary MOSFET embodiment shown in Fig. 3 is shown respectively;
Fig. 6 to Figure 16 illustrates the isometric view of simplification that is integrated into the multiple lateral power structure of automatic bias electrode structure wherein according to having of other exemplary embodiment of the present invention; And
Figure 17 A to Figure 17 C illustrates according to the top layout views of three representative configuration of the automatic bias electrode of the embodiment of the present invention.
Embodiment
According to the present invention, automatic bias electrode is integrated in multiple lateral power, thereby changes Electric Field Distribution in the barrier layer of these devices to improve the blocking ability of the device that the doping content on barrier layer is identical.Alternatively, for identical blocking ability, automatic bias electrode is realized and in barrier layer, is used higher doping content, improves thus conducting resistance and the power consumption of device.
Fig. 2 illustrates the viewgraph of cross-section of the simplification of planar gate (planar-gate) (Silicon-on-insulator) MOSFET lateral 200 according to an exemplary embodiment of the present invention with automatic bias electrode.Extend on highly doped N type semiconductor district 202 light dope N-type drift region 204.In one embodiment, drift region 204 and the high doping semiconductor district 202 below it are all epitaxial loayers.In another embodiment, drift region 204 is that epitaxial loayer ，Er high doping semiconductor district 202 is N+ substrates.In another embodiment, by dopant being injected and advancing high-doped zone 202 to form drift region 204, wherein, this high-doped zone self can be epitaxial loayer or substrate.
The existence of dielectric layer 226 has advantageously been eliminated the doping of electrode 224 has been carried out to the demand of carefully controlling, otherwise it guarantees charge balance by needs.Similarly, at electrode 224, comprise in the embodiment of doped silicon, dielectric layer 226 prevents that dopant in doped silicon is to outdiffusion.
As follows according to the method for the manufacture MOSFET 200 of the embodiment of the present invention.Use conventional art on drift region 204, to form gate dielectric 216 and gate electrode 218.Use tradition to shelter (masking) and inject/advance (drive-in) technology and 204 form 210, drain region 214,206, source region, tagma and heavy tagma 208 in drift region.Notice, source region 210 and tagma 208 are self-aligned to the edge of gate electrode 218.By known technology, form unshowned a plurality of metal level (for example, source metal level and leakage metal level) and dielectric layer.By tradition, shelter and etch techniques forms groove 222 in drift region 204.Then, form dielectric layer 226 and be lining in trenched side-wall and bottom to cover.In one embodiment, dielectric layer 226 has 100
-500
scope in thickness.Determine a doping content that factor is drift region 204 in the thickness of dielectric layer 226.For the drift region with higher-doped concentration, can use thinner dielectric layer 226.
Next, deposition dark etching polysilicon layer, thus with the embedding groove 222 of polysilicon, there is the end face with adjacent platforms surface co-planar.Make a little the polysilicon in each groove recessed, thereby expose along a plurality of parts of the dielectric layer 226 of upper trenched side-wall.A plurality of parts of the layer 226 exposing are the parts that are removed, thereby expose the drift region 204 along upper trenched side-wall.Carry out the second polysilicon deposition and dark etching, with the top of embedding each groove, make thus polysilicon electrode electrical short in each groove to drift region.
Depend on manufacturing technology, for the restriction of the materials of a plurality of layers and other processing and design, can carry out the treatment step that forms automatic bias electrode at the place of a plurality of stages processing.For example,, if electrode 224 comprises polysilicon, so can the initial stage in processing carry out the step that forms trenched electrodes because polysilicon can withstand high temperature.Yet, if electrode 224 comprises metal, need in the processing of manufacture after a while after carrying out high-temperature process, carry out the step that is used to form trenched electrodes.
Fig. 3 illustrates the optional automatic bias electrode structure/technique that according to the present invention another exemplary embodiment is integrated with MOSFET 300.In Fig. 3, the electrode 324 in groove 322 is along the bottom section 328 of groove 322 rather than along electrically contacting as the top of the groove in MOSFET 200 and drift region 304.Except the treatment step that the formation trenched electrodes structure with next describing is associated, the manufacturing process that is used to form MOSFET 300 is similar to the manufacture process for above-mentioned MOSFET 200.
Use tradition to shelter and in drift region 304, form groove 322 with etch techniques.Although further extension groove 322 is to be terminated in high-doped zone 302, because therefore the more low-doped automatic bias electrode 324 that contributes to of drift region 304 stops groove 322 more favourable in drift region 304.This will describe below in more detail.Next, with conventional art, form and cover the dielectric layer 326 that is lining in trenched side-wall and bottom.Next, the directional etch of dielectric layer 326 is only removed the horizontal-extending portion of dielectric layer 326.Therefore drift region 304 becomes exposure along the bottom section 328 of groove 322.Formation, such as the conductive electrode of in-situ doped (in-situdoped) (P type) polysilicon, then, is recessed into groove 322.Next, on electrode 324, form another dielectric layer with closed groove 322.Therefore, electrode 328 electrically contacts along 328Yu drift region, channel bottom region 304.
Between P type electrode 224 in MOSFET 200 and N-type drift region 204 and MOSFET 300 in P type electrode 324 and N-type drift region 304 between be electrically connected to and cause electrode 224 and 324 self-bias to be pressed onto the voltage that is greater than zero.In one embodiment, put upside down the doping polarity in the All Ranges in MOSFET 200 and 300, form thus P channel mosfet.In this embodiment, being electrically connected between P type drift region and N-type channel electrode causes electrode self-bias to be pressed onto minus voltage.
As shown by the simulation result in Fig. 4 and Fig. 5, automatic bias electrode is used for changing the electric field in drift region.Fig. 4 illustrates the Electric Field Distribution in the drift region 104 of the conventional MOS FET 100 in Fig. 1.As can be seen, electric field reaches peak value near the curvature in tagma 106, then, to drain region, reduces gradually, forms thus triangle area below electric field curve.Fig. 5 illustrates the Electric Field Distribution in the drift region 304 of the MOSFET 300 in Fig. 3.As can be seen, except the peak value of the curvature in tagma 306, by two automatic bias electrodes 324, introduce two extra peak values.Therefore, increased the area of electric field curve below, it has increased again transistorized puncture voltage.As indicated in Fig. 4 and Fig. 5, for 5 * 10
15/ cm
3identical drift region doping content, puncture voltage is brought up to the 125V of MOSFET 300 from the 75V of the MOSFET 100 of prior art.This equals in 66% improvement in puncture voltage.
Fig. 6 illustrates according to the isometric view of the simplification of the MOSFET 600 of the embodiment of the present invention, peels off therein a plurality of layers to appear region below.MOSFET 600, except a few features further describing below, is similar to MOSFET 300.The isometric view of Fig. 6 illustrates one of many possible placement pattern of automatic bias electrode in drift region 604.As can be seen, with the general layout of interlocking, arrange automatic bias electrode, but those skilled in the art it is also envisioned that many other structures.In one embodiment, the position of electrode and number depend on the doping content of drift region 604 to a certain extent.The doping content of drift region 604 is higher, in drift region, can place more electrodes, and therefore obtains higher puncture voltage.Similarly, the number of electrode can be limited to the current density requirements of device.
In optional embodiment, will be similar to conventional MOS FET 100 112 LDD districts, Zhong LDD district and be incorporated in MOSFET 600.This LDD district will have than the higher doping content in drift region 604 that forms therein GaiLDD district, if therefore need to; allow the automatic bias electrode of more number to be more included in drift region.LDD district has reduced significantly the conducting resistance of device and has increased puncture voltage together with the number of increased automatic bias electrode.
Fig. 6 also show electrically contact source region 610 and heavy tagma 608 source conductor 632 (for example, comprise metal) and the drain conductor 634 that electrically contacts drain region 614 is (for example, comprise metal), and by source conductor 632, grid 618 and drain conductor 634 dielectric layer 630 insulated from each other.As shown, channel electrode 624 terminates in the upper surface place of drift region 604, makes the complete coated electrode 624 of dielectric layer 630.In another embodiment, the electrode 324 that electrode 624 is similar in MOSFET 300 is recessed in its corresponding groove.
Another difference between MOSFET 600 and 300 is that, in MOSFET 600, trenched electrodes 624 runs through drift region 604 completely, and terminates in more low-doped silicon area 602.This causes electrode 624 with more low-doped silicon area 602 rather than drift region 604 contacts.This is favourable, be by the lower doped region 602 (as the doped drift region 604 with higher contrasts) of contact, electrode 624 can automatic bias and do not obtain the electromotive force (in the situation that the higher doped silicon region of electrode contact will obtain this electromotive force) of silicon area.
Fig. 7 illustrates the isometric view of the simplification of the lateral insulated gate bipolar transistor (IGBT) 700 according to an exemplary embodiment of the present invention with integrated automatic bias electrode.Extend on light dope N-type district 702 N-type drift region 704.In one embodiment, drift region 704 and light doping section 702 are all epitaxial loayers.In another embodiment, drift region 704 is epitaxial loayers, and light doping section 702 is N-substrates.In another embodiment, by dopant being injected and being advanced to light doping section 702 to form 704， light doping section, drift region self can be epitaxial loayer or substrate.
Groove 722 runs through drift region 704, and terminates in silicon area 702.Insulating barrier 726 covers the bottom of the sidewall rather than the groove that are lining in groove.Embedding each groove 722 of conductive electrode 724 also electrically contacts silicon area 702 along the bottom section 728 of groove.In one embodiment, the conductibility of conductive electrode 724 is contrary with the conductibility of silicon area 702, and therefore supposes the N-type conductibility of silicon area 702, and the conductivity of conductive electrode is P type.In another embodiment, conductive electrode 724 comprises silicon or the metal of highly doped P type polysilicon or doping.
For example, although the difference in needs consideration operation (, hole current and electronic current all contribute to the electric current conduction in IGBT), but relate to the many considerations relevant with previous embodiment (for example, the placement of electrode and the frequency doping content to drift region) and be applied to equally IGBT700.
Fig. 8 illustrates the isometric view of the simplification of the transverse diode 800 with integrated automatic bias electrode of another exemplary embodiment according to the present invention.Extend on light dope N-type district 802 N-type drift region 804.As in previous embodiment, silicon area 802 can be epitaxial loayer or substrate, and drift region 804 can be epitaxial loayer, maybe can form by dopant being injected and being advanced to silicon area 802.
In drift region 804, form p type anode district 806 and highly doped N-type (N+) district 814.As shown, anode region 806 and N+ district 814 separate transverse to each other.Plate conductor layer 832 (for example, comprising metal) electrically contacts anode region 806, and cathode conductor layer 834 (for example, comprising metal) electrically contacts N+ district 814.Dielectric layer 830 make plate conductor layer 832 and cathode conductor layer 834 insulated from each other.Trenched electrodes 824 have with Fig. 6 and Fig. 7 in the similar structure of structure, therefore and be not described.As in previous embodiment, for identical drift region doping content, automatic bias electrode 824 is used for improving the blocking ability of diode 800.
Fig. 9 illustrates the isometric view of the simplification of the lateral direction schottky diode 900 with integrated automatic bias electrode of another exemplary embodiment according to the present invention.The structure of lateral direction schottky diode 900 is similar to diode 800 to a great extent, yet, replace forming shallow light dope N-type district 906 in 806， drift region, p type anode district 904.Plate conductor 932 (for example, comprising Schottky barrier metal) forms the Schottky contacts in Yu QianNXing district 906.In a distortion, form shallow p type island region and replace N-type district 906, thus, plate conductor 932 forms the Schottky contacts with p type island region.As in previous embodiment, for identical drift region doping content, automatic bias electrode 924 is used for improving the blocking ability of Schottky diode 900.
Figure 10 illustrates the isometric view of simplification of the distortion of (Silicon-on-insulator) MOSFET lateral 600, and drain plug (drain plug) 1034 (for example, comprising metal) in depth extends in drift region 1004 therein.In one embodiment, drain plug 1034 extends to and the approximately uniform degree of depth of electrode trenches 1022.The advantage of this embodiment is that drain plug (drain plug) 1034, for expanding (spread) by the electric current of drift region 1004, further reduces the conducting resistance of MOSFET thus.This is combined and has reduced significantly transistorized conducting resistance and power consumption with automatic bias electrode.
Figure 11 illustrates the isometric view of simplification of the distortion of (Silicon-on-insulator) MOSFET lateral 1000, removes therein outside drain plug 1134, and the highly doped N-type drain region 1114 that surrounds this drain plug 1134 is incorporated in this structure.Drain region 1114 further reduces the resistance of transistor current path, and reduces the contact resistance of drain plug.By forming groove, then before for example, carrying out embedding groove by drain plug (, metal), carry out two pass (two-pass) angle of N-type impurity and inject to form drain region 1114.
Figure 12 at the high conductive plunger 1234 in the collector terminal place of IGBT 1200 (for example illustrates according to the present invention another exemplary embodiment, metal) and the execution mode of optional highly doped P type collector region 1214, itself and IGBT 700 are similar on aspect other of structure.Figure 13 at the high conductive plunger 1334 in the cathode terminal place of transverse diode 1300 (for example illustrates according to the present invention another exemplary embodiment, metal) and the execution mode in highly doped N-type district 1214, the transverse diode 800 in itself and Fig. 8 is similar on aspect other of structure.。As in embodiment above, connector 1334 and N+ district 1314 contribute to improve the conducting resistance of diode.Also in Schottky diode 900 to realize high conductive plunger with the similar fashion shown in Figure 130 0.
Fig. 6 to Figure 13 is illustrated in for example, higher-doped N-shaped layer (for example, the layer 604 in Fig. 6) on more low-doped N-shaped layer (, the layer 602 in Fig. 6).In a distortion of these structures, on highly doped substrate, be epitaxially formed each layer in these two layers.In another distortion, higher-doped N-shaped layer is epitaxial loayer, and more low-doped N-shaped layer below can be substrate.In another distortion, by N-shaped dopant is injected and is advanced to the N-shaped layer that light dope N-shaped layer forms higher-doped, this light dope N-shaped layer self can be epitaxial loayer or the substrate extending on substrate.
Figure 14 illustrates the execution mode that uses silicon-on-insulator (SOI) technology or buried dielectric (burieddielectric) technology automatic bias electrode in MOSFET 1400.As shown, for example, except forming outside this structure on dielectric layer 1440 (, comprising oxide), MOSFET 1400 is similar to the MOSFET in Fig. 6.In one embodiment, silicon area 1402 and 1404 is the epitaxial loayers that are sequentially formed on dielectric layer 1440.In another embodiment, by dopant being injected and being advanced to the silicon area 1402 being epitaxially formed, form drift region 1404.In the situation that dielectric layer 1440 is buried dielectric, traditional Semiconductor substrate (not shown) is positioned under dielectric layer 1440.Other lateral powers (comprising transversal I GBT, transverse diode and lateral direction schottky diode) of realizing disclosure in this article by SOT or buried dielectric are for considering that those skilled in the art of the present disclosure is apparent.
Figure 15 illustrates the distortion of the MOSFET of Figure 14, wherein, has eliminated the light dope silicon area 1402 in MOSFET1400, makes electrode 1424 terminate in drift region 1504 and electrically contacts this drift region.Figure 16 illustrates another distortion, wherein, MOSFET 1600 is formed in the individual layer of silicon 1604.To be similar to the mode of the embodiment shown in Figure 15 and Figure 16, to realize other transversal devices with integrated automatic bias electrode will be apparent for considering those skilled in the art of the present disclosure.
Figure 17 A to Figure 17 C illustrates the top layout views of three representative configuration of automatic bias electrode.In Figure 17 A, each electrode 1724A insulate by dielectric layer 1726A and drift region 1704A.With with Fig. 6 to Figure 16 in structure similarly staggered general layout carry out the electrode in Pareto diagram 17A.In Figure 17 B, a large amount of electrode 1724B are placed in dielectric well (dielectric well) 1726B that follows extension.Figure 17 C also illustrates the electrode 1724C that follows arrangement, but each electrode insulate partly by dielectric layer 1726C and drift region 1704C.Although the electrode in Figure 17 A to Figure 17 C is square, they can have alternatively such as circle, hexagon and oval-shaped many other shapes.
Notice, can JiangLDD district in the similar mode of above-mentioned mode with about Fig. 6, be incorporated in a plurality of embodiment of disclosing herein one or more.Similarly, although Fig. 6 to Figure 16 illustrates the upper surface place that trenched electrodes terminates in drift region, but in other embodiment of the transversal device in Fig. 6 to Figure 16, the electrode 324 in trenched electrodes and MOSFET 300 is recessed in its corresponding groove similarly.
Multiple lateral direction power MOSFET and the IGBT embodiment with the describing that illustrate in this article have planar gate structure, yet, have such as the U.S. Patent application the 10/269th of submitting on October 3rd, 2002, in the (Silicon-on-insulator) MOSFET lateral of the trench gate structure of those disclosed in No. 126 (it is openly incorporated into this by quoting as proof) and IGBT, realizing automatic bias electrode for considering that those skilled in the art of the present disclosure are apparent.Similarly, have such as the U.S. Patent application the 10/951st of submitting on September 26th, 2004, in the (Silicon-on-insulator) MOSFET lateral of dhield grid (shielded gate) structure of those disclosed in No. 259 (it is openly incorporated into this by quoting as proof) and IGBT, realizing automatic bias electrode will be apparent for considering those skilled in the art of the present disclosure.
Although the detailed description for various embodiments of the present invention is provided above, many optional, the modification of these embodiment, combination and equivalent are all possible.For example, although the exemplary lateral power device embodiment in Fig. 6 to Figure 16 is incorporated to automatic bias electrode, it makes to contact with adjacent silicon area along the bottom of electrode, but revise the embodiment of these lateral powers or it is significantly out of shape, making electrode will be apparent along the adjacent silicon area of its top (being similar to shown in Fig. 2) contact concerning considering those skilled in the art of the present disclosure.Similarly, should be appreciated that it is only all exemplary object that being used for of providing in this article described sizes, doping content and different semiconductor layer or all material type of insulating barrier, is not intended to restriction.For example, can be reversed in doping polarity and the automatic bias electrode of the multiple silicon area in embodiment described herein, to obtain the device of the opposite polarity type of specific embodiment.For these and other reasons, therefore, description above will not be regarded as limitation of the scope of the invention, and scope of the present invention is limited by appended claim.
Claims (54)
1. a semiconductor transistor, comprising:
The drift region of the first conductivity type;
The well region of the second conductivity type in described drift region, forms pn knot between described well region and described drift region;
The first highly doped silicon area of described the first conductivity type in described well region;
The second highly doped silicon area in described drift region, described the second highly doped silicon area and described well region are laterally isolated, once make under conduction state, bias voltage to be added to described semiconductor transistor, electric current laterally flows between the first highly doped silicon area and the second highly doped silicon area by described drift region; And
Perpendicular to a plurality of grooves in the described drift region of extending to of described electric current, each groove all has dielectric layer and at least one conductive electrode that covers at least a portion that is lining in described trenched side-wall.
2. semiconductor transistor according to claim 1, wherein, each conductive electrode electrically contacts described drift region along the upper side wall of each groove.
3. semiconductor transistor according to claim 2, wherein, extend on the 3rd silicon area of described the first conductivity type described drift region, and described the 3rd silicon area has the doping content higher than described drift region.
4. semiconductor transistor according to claim 1, wherein, each conductive electrode contacts described drift region along the bottom electrical of each groove.
5. semiconductor transistor according to claim 1, wherein, extend on the 3rd silicon area described drift region, described the 3rd silicon area has the doping content lower than the doping content of described drift region, wherein, described a plurality of groove runs through described drift region and ends in described the 3rd silicon area, and the described conductive electrode in each groove contacts described the 3rd silicon area along the bottom electrical of each groove.
6. semiconductor transistor according to claim 5, wherein, described the 3rd silicon area extends on dielectric layer.
7. semiconductor transistor according to claim 1, wherein, extend on dielectric layer described drift region.
8. semiconductor transistor according to claim 1, wherein, each conductive electrode is all second conductivity types.
9. semiconductor transistor according to claim 5, also be included in the described first conductivity type LDD district of extending in the top of the described drift region between described well region and described the second highly doped silicon area, described LDD district has the doping content higher than described drift region.
10. semiconductor transistor according to claim 1, wherein, described a plurality of electrodes with the general layout of interlocking between described well region and described the second highly doped silicon area.
11. semiconductor transistors according to claim 1, wherein, described semiconductor transistor is that MOSFET and described the first highly doped silicon area form source region, and described the second highly doped silicon area be described the first conductivity type and form drain region, described device also comprises:
Planar gate is extended and partly overlap described source region and described drift region on a part for described well region.
12. semiconductor transistors according to claim 11, also comprise high conductive drain connector, extend to described the second highly doped silicon area.
13. semiconductor transistors according to claim 12, wherein, described high conductive drain connector and described a plurality of groove extend to the essentially identical degree of depth.
14. semiconductor transistors according to claim 1, wherein, described semiconductor transistor is IGBT, and described the second highly doped silicon area be described the second conductivity type and form collector region, described device also comprises:
Planar gate is extended and partly overlap described the first highly doped silicon area and described drift region on a part for described well region.
15. semiconductor transistors according to claim 14, also comprise high conduction collector electrode connector, extend to described collector region.
16. semiconductor transistors according to claim 15, wherein, described high conduction collector electrode connector and described a plurality of groove extend to the essentially identical degree of depth.
17. 1 kinds of semiconductor diodes, comprising:
The drift region of the first conductivity type;
The anode region of the second conductivity type in described drift region, forms pn knot between described anode region and described drift region;
The first highly doped silicon area of described the first conductivity type in described drift region, described the first highly doped silicon area and described anode region laterally isolate, once make under conduction state, bias voltage to be added to described semiconducter power diode, electric current laterally flows between described anode region and described the first highly doped silicon area by described drift region; And
Perpendicular to a plurality of grooves in the described drift region of extending to of described electric current, each groove all has dielectric layer and at least one conductive electrode that covers at least a portion that is lining in described trenched side-wall.
18. semiconductor diodes according to claim 17, wherein, each conductive electrode all electrically contacts described drift region along the upper portion side wall of each groove.
19. semiconductor diodes according to claim 18, wherein, extend on the second silicon area of described the first conductivity type described drift region, and described the second silicon area has the doping content higher than described drift region.
20. semiconductor diodes according to claim 17, wherein, each conductive electrode all contacts described drift region along the bottom electrical of each groove.
21. semiconductor diodes according to claim 17, wherein, extend on the second silicon area described drift region, described the second silicon area has the doping content lower than the doping content of described drift region, wherein, described a plurality of groove runs through described drift region and ends in described the second silicon area, and the described conductive electrode in each groove contacts described the second silicon area along the bottom electrical of each groove.
22. semiconductor diodes according to claim 21, wherein, described the second silicon area extends on dielectric layer.
23. semiconductor diodes according to claim 17, wherein, extend on dielectric layer described drift region.
24. semiconductor diodes according to claim 17, wherein, each conductive electrode is all second conductivity types.
25. semiconductor diodes according to claim 17, wherein, described a plurality of electrodes with the general layout of interlocking between described anode region and described the first highly doped silicon area.
26. semiconductor diodes according to claim 17, also comprise high conductive plunger, extend to described the first highly doped silicon area.
27. semiconductor diodes according to claim 26, wherein, described high conductive plunger and described a plurality of groove extend to the essentially identical degree of depth.
28. 1 kinds of Schottky diodes, comprising:
The drift region of the first conductivity type;
The light dope silicon area of described the first conductivity type in described drift region;
On described light dope silicon area and the conductor layer contacting with described light dope silicon area, described conductor layer forms the Schottky contacts with described light dope silicon area;
The highly doped silicon area of described the first conductivity type in described drift region, described highly doped silicon area and described light dope silicon area laterally separate, once make under conduction state, bias voltage to be added to described Schottky diode, electric current laterally flows between described light dope silicon area and described highly doped silicon area by described drift region; And
Perpendicular to a plurality of grooves in the described drift region of extending to of described electric current, each groove all has dielectric layer and at least one conductive electrode that covers at least a portion that is lining in described trenched side-wall.
29. Schottky diodes according to claim 28, wherein, each conductive electrode all electrically contacts described drift region along the upper portion side wall of each groove.
30. Schottky diodes according to claim 29, wherein, extend on the silicon area of described the first conductivity type described drift region, and described silicon area has the doping content higher than described drift region.
31. Schottky diodes according to claim 28, wherein, each conductive electrode all contacts described drift region along the bottom electrical of each groove.
32. Schottky diodes according to claim 28, wherein, extend on silicon area described drift region, described silicon area has the doping content lower than the doping content of described drift region, wherein, described a plurality of groove runs through described drift region and ends in described silicon area, and the described conductive electrode in each groove all contacts described silicon area along the bottom electrical of each groove.
33. Schottky diodes according to claim 32, wherein, described silicon area extends on dielectric layer.
34. Schottky diodes according to claim 28, wherein, extend on dielectric layer described drift region.
35. Schottky diodes according to claim 28, wherein, each conductive electrode is all second conductivity types.
36. Schottky diodes according to claim 28, wherein, described a plurality of electrodes with the general layout of interlocking between described light dope silicon area and described highly doped silicon area.
37. Schottky diodes according to claim 28, also comprise the high conductive plunger extending in described highly doped silicon area.
38. according to the Schottky diode described in claim 37, and wherein, described high conductive plunger and described a plurality of groove extend to the essentially identical degree of depth.
39. 1 kinds of methods that form semiconductor transistor, comprising:
In the drift region of the first conductivity type, form well region, described well region is the second conductivity type, forms pn knot between described drift region and described well region;
In described well region, form the first highly doped silicon area of described the first conductivity type;
In described drift region, form the second highly doped silicon area, described the second highly doped silicon area and described well region laterally separate, once make under conduction state, bias voltage to be added to described semiconductor transistor, electric current laterally flows between the first highly doped silicon area and the second highly doped silicon area by described drift region;
Formation is perpendicular to a plurality of grooves that extend to described drift region of described electric current;
The dielectric layer of at least a portion that is lining in described trenched side-wall is covered in formation; And
In each groove, form at least one conductive electrode.
40. according to the method described in claim 39, wherein, forms described dielectric layer, makes each conductive electrode all along the upper side wall of each groove, electrically contact described drift region.
41. according to the method described in claim 40, is also included on the substrate of described the first conductivity type and forms epitaxial loayer, and described epitaxial loayer forms described drift region, and described substrate has the doping content higher than described drift region.
42. according to the method described in claim 39, wherein, forms described dielectric layer, makes each conductive electrode all along the bottom electrical of each groove, contact described drift region.
43. according to the method described in claim 39, and wherein, the step of described at least one conductive electrode of formation comprises the polysilicon layer that forms the described a plurality of grooves of filling, and described polysilicon layer is in-situ doped to have the second conductivity type.
44. according to the method described in claim 39, also comprises the planar gate of extending on the predetermined surface region that is formed on described drift region.
45. 1 kinds of methods that form semiconductor diode, comprising:
In the drift region of the first conductivity type, form anode region, described anode region is the second conductivity type, forms pn knot between described anode region and described drift region;
In described drift region, form the first highly doped silicon area of described the first conductivity type, described the first highly doped silicon area and described anode region laterally separate, once make under conduction state, bias voltage to be added to described semiconducter power diode, electric current laterally flows between described anode region and described the first highly doped silicon area by described drift region;
Formation is perpendicular to a plurality of grooves in the described drift region of extending to of described electric current;
The dielectric layer of at least a portion that is lining in each trenched side-wall is covered in formation; And
In each groove, form at least one conductive electrode.
46. according to the method described in claim 45, wherein, forms described dielectric layer, makes each conductive electrode all along the upper side wall of each groove, electrically contact described drift region.
47. according to the method described in claim 46, is also included on the substrate of described the first conductivity type and forms epitaxial loayer, and described epitaxial loayer forms described drift region, and described substrate has the doping content higher than described drift region.
48. according to the method described in claim 45, wherein, forms described dielectric layer, makes each conductive electrode all along the bottom electrical of each groove, contact described drift region.
49. according to the method described in claim 45, and wherein, the step of described at least one conductive electrode of formation comprises the polysilicon layer that forms the described a plurality of grooves of filling, and described polysilicon layer is in-situ doped to have the second conductivity type.
50. 1 kinds of methods that form Schottky diode, comprising:
The light dope silicon area of described the first conductivity type in the drift region of the first conductivity type;
On described light dope silicon area and with described light dope silicon area, form contiguously conductor layer, described conductor layer forms the Schottky contacts with described light dope silicon area;
In described drift region, form the highly doped silicon area of described the first conductivity type, described highly doped silicon area and described light dope silicon area laterally separate, once make under conduction state, bias voltage to be added to described Schottky diode, electric current laterally flows between described light dope silicon area and described highly doped silicon area by described drift region;
Formation is perpendicular to a plurality of grooves in the described drift region of extending to of described electric current;
The dielectric layer of at least a portion that is lining in each trenched side-wall is covered in formation; And
In each groove, form at least one conductive electrode.
51. according to the method described in claim 50, wherein, forms described dielectric layer, makes each conductive electrode all along the upper side wall of each groove, electrically contact described drift region.
52. according to the method described in claim 51, is also included on the substrate of described the first conductivity type and forms epitaxial loayer, and described epitaxial loayer forms described drift region, and described substrate has the doping content higher than described drift region.
53. according to the method described in claim 50, wherein, forms described dielectric layer, makes each conductive electrode all along the bottom electrical of each groove, contact described drift region.
54. according to the method described in claim 50, and wherein, the step of described at least one conductive electrode of formation comprises the polysilicon layer that forms the described a plurality of grooves of filling, and described polysilicon layer is in-situ doped to have the second conductivity type.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US77490006P | 2006-02-16 | 2006-02-16 | |
| US60/774,900 | 2006-02-16 | ||
| US11/404,062 | 2006-04-12 | ||
| US11/404,062 US7473976B2 (en) | 2006-02-16 | 2006-04-12 | Lateral power transistor with self-biasing electrodes |
| PCT/US2007/061718 WO2007098317A2 (en) | 2006-02-16 | 2007-02-06 | Lateral power devices with self-biasing electrodes |
Publications (2)
| Publication Number | Publication Date |
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| CN101385151A true CN101385151A (en) | 2009-03-11 |
| CN101385151B CN101385151B (en) | 2013-07-24 |
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| CN200780005748.9A Expired - Fee Related CN101385151B (en) | 2006-02-16 | 2007-02-06 | Lateral power transistor with self-biasing electrodes |
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| Country | Link |
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| CN (1) | CN101385151B (en) |
| MY (1) | MY147514A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102945838A (en) * | 2012-11-05 | 2013-02-27 | 电子科技大学 | High voltage interconnection structure |
| CN106549052A (en) * | 2015-09-17 | 2017-03-29 | 联华电子股份有限公司 | LDMOS transistor and preparation method thereof |
| CN110739345A (en) * | 2019-08-30 | 2020-01-31 | 电子科技大学 | Self-biased split gate trench type power MOSFET device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB0006957D0 (en) * | 2000-03-23 | 2000-05-10 | Koninkl Philips Electronics Nv | A semiconductor device |
| JP3634830B2 (en) * | 2002-09-25 | 2005-03-30 | 株式会社東芝 | Power semiconductor device |
-
2007
- 2007-02-06 CN CN200780005748.9A patent/CN101385151B/en not_active Expired - Fee Related
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2008
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102945838A (en) * | 2012-11-05 | 2013-02-27 | 电子科技大学 | High voltage interconnection structure |
| CN106549052A (en) * | 2015-09-17 | 2017-03-29 | 联华电子股份有限公司 | LDMOS transistor and preparation method thereof |
| CN106549052B (en) * | 2015-09-17 | 2021-05-25 | 联华电子股份有限公司 | Lateral diffusion metal oxide semiconductor transistor and manufacturing method thereof |
| CN110739345A (en) * | 2019-08-30 | 2020-01-31 | 电子科技大学 | Self-biased split gate trench type power MOSFET device |
Also Published As
| Publication number | Publication date |
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| CN101385151B (en) | 2013-07-24 |
| MY147514A (en) | 2012-12-31 |
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