CN101383133B - Shifting cache unit for eliminating ghost - Google Patents
Shifting cache unit for eliminating ghost Download PDFInfo
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- CN101383133B CN101383133B CN2008101697046A CN200810169704A CN101383133B CN 101383133 B CN101383133 B CN 101383133B CN 2008101697046 A CN2008101697046 A CN 2008101697046A CN 200810169704 A CN200810169704 A CN 200810169704A CN 101383133 B CN101383133 B CN 101383133B
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Abstract
The invention provides a device for eliminating remnant trace, a shift buffer unit, liquid crystal display equipment and a method. By only matching a delay discharge phenomenon of a high voltage source, which is generated by a power supply device in shutting off, the shift buffer unit is driven, any two signal sources in a plurality of signal sources form high quasi-bits so as to control a discharge switch module to charge and discharge pixel units. The invention not only can solve the problem of the remnant trace in shutting off, but also has the signal resetting function in startup.
Description
Technical field
The invention relates to a kind of device, shift buffer memory unit, liquid crystal display and method that is used to eliminate ghost, particularly about a kind of shift buffer memory unit of eliminating power-off ghost shadow.
Background technology
The generation of the GTG signal of a plurality of pixels (Pixel) on the panel mostly general LCD (LCD) is to utilize driver module (Driving Circuit) to control this LCD, this driver module comprises that mainly a gate drivers (Gate Driver) is electrically connected several sweep traces (or claiming gate line) to export grid impulse signal (Gate Pulse Signal) respectively to each respective pixel, and one source pole driver (Source Driver) be electrically connected several data lines (or claim source electrode line) with data signal (Data Signal) respectively to each respective pixel, and each bar sweep trace and the confluce of each bar data line also connect the bipolarity end (as the grid and the source electrode of thin film transistor (TFT) (TFT)) of the active member of a corresponding pixel respectively.At present, some known LCD (LCD) panels such as low temperature polycrystalline silicon (Low Temperature Poly-Silicon, LTPS) the offset buffer (Shift Register) that originally is positioned at a gate drivers chip is transformed on glass substrate, offset buffer (the Shift Register Stages) module that forms multi-stage serial connection is to realize GOA (Gate onArray).When the offset buffer (Shift Registers) of respectively organizing of this gate drivers is exported the grid impulse signal when opening the thin film transistor (TFT) that connects on each bar sweep trace one by one in regular turn, this source electrode driver can be exported corresponding data-signal simultaneously and charge to required pixel current potential with storage capacitors (Cs) and liquid crystal capacitance (Clc) to the thin film transistor (TFT) on these data lines, uses to show different GTGs.But because the relation of charging, known LCD (LCD) is after the long-time display image of process, stored charge in the liquid crystal capacitance (Clc) of meeting between two counter electrodes (as common electrode and show electrode) makes it maintain a specific pixel current potential (Pixel Potential); At this moment, if (Power off) closed in the power supply supply of LCD (LCD), still may the last image (Afterimage) of residual fraction on its picture moment, and these known LCD (LCD) can only be by corresponding each pixel the leakage current (Current leakage) of thin film transistor (TFT) itself reach the pixel current potential purpose of (Discharge) of discharging gradually, thereby cause power-off ghost shadow (Power-offafterimage) phenomenon to continue more of a specified duration.
In order to solve the power-off ghost shadow phenomenon, moment that must be behind system closedown, simultaneously the output potential of each bar gate line is pulled up to more tallerly than maximum pixel current potential, could snap-out release be stored in the electric charge among the liquid crystal capacitance.The method that all gate line output potentials moments is drawn high has many kinds simultaneously, wherein a kind of known method is to utilize a gate driver circuit (Gate Driver CircuitIntegrated On Array who is integrated in array base palte, GOA), it uses two groups of different clocks (Clock) signal (CLK1 and CLK2) to provide strange respectively, the grid impulse signal output of even level, and the grid impulse signal of output transmits in regular turn from the extremely final stage of the first order, and use a low-voltage source (Vss), and CLK1 by the output of improvement one power control circuit, CLK2 and Vss circuit, after making system closedown, CLK1, CLK2 and VSS can be promoted to the accurate position of a high voltage simultaneously as Vdd together in moment, make the grid impulse signal of each grade gate driver circuit export noble potential simultaneously by this, reach the purpose of shutdown back pixel rapid discharge.
Gate driver circuit unit (the Gate Driver Circuit Integrated On Array unit that be integrated in array base palte of another kind of known method shown in Figure 1A, GOA unit) 2, its structure division and aforementioned known gate driver circuit are similar, have many group gate driver circuits 22 as offset buffer, be used for connecting respectively first end of each bar gate line 4, to produce the corresponding thin film transistor (TFT) (T that the grid impulse signal exports each bar gate line 4 and data line 5 intersections in regular turn
MIN) grid, but wherein be than difference with the design of aforementioned gate driver circuit: relative second end of this each bar gate line 5 electrically adds an XON circuit 9, and it comprises one group of accurate bit shift device (level shifter) 10 and organizes second end that charge (charge/discharge circuit) 11 are connected these gate lines 5 respectively more.
Shown in Figure 1A and Figure 1B, during system boot (Power on), accurate bit shift device 10 is exported low level (V according to the accurate position of an XON input signal
Gl) to close each charge 11, therefore can not do the action that discharges and recharges to arbitrary gate line 4; Otherwise when the moment of system closedown (Power off), accurate bit shift device 10 is exported high levle (V according to the XON input signal of different accurate positions
Gh) with each charge 11 of activation these gate lines 4 are charged to noble potential after, slowly be discharged to the accurate position of ground connection (GND) (as the Gn waveform of Figure 1B) again, be stored in electric charge among the liquid crystal capacitance Cs with release, can improve the phenomenon of power-off ghost shadow by this.And the design of this gate driver circuit unit certainly will additionally increase the element cost of XON circuit 9, and controls discharging and recharging of pixel because need to use an extra XON input signal, so can increase the complexity of system design.
Summary of the invention
The object of the present invention is to provide a kind of shift buffer memory unit that is used to eliminate ghost, be that several existing signal sources of utilizing shift buffer memory unit to use comprise initial setting signal (STV), any two signal sources among first clock signal (CKV1) and the second clock signal (CKV2) are controlled at least one discharge switch module and are discharged and recharged with the pixel cell to correspondence, eliminate power-off ghost shadow (Power-offafterimage) by this, drive the discharge switch module and need not to set up especially extra signal source, also need not to use extra accurate bit shift device, so can reduce the element cost and reduce system complexity.
For reaching the object of the invention, the invention provides a kind of shift buffer memory unit that is used to eliminate ghost, described shift buffer memory unit is applicable in the liquid crystal display and connects a signaling control unit, wherein said signaling control unit has one first signal and a secondary signal, the waveform that receives a power supply input signal when described signaling control unit is when being the drop edge, first signal and secondary signal with high levle are provided simultaneously, and described shift buffer memory unit comprises: at least one offset buffer has: draw driver module at least one; Drawing-die piece on one, connect and draw driver module and have a signal output terminal on described, and, export at least one corresponding pixel cell of a signal to liquid crystal display in described signal output terminal according to described first signal and both one of them signals of a secondary signal; At least one drop-down control module connects the described signal output terminal of going up the drawing-die piece; And at least one discharge switch module, be electrically connected the secondary signal and the described signal output terminal of going up the drawing-die piece of high levle, wherein said discharge switch module is first signal triggering startup according to high levle, and at least one corresponding pixel cell in the liquid crystal display is discharged.
Description of drawings
Figure 1A is the circuit diagram that shows a known gate driver circuit unit;
Figure 1B is the oscillogram that shows several unlike signals in the known gate driver circuit unit of Figure 1A;
Fig. 2 A is the functional-block diagram that shows a kind of liquid crystal display according to first preferred embodiment of the present invention;
Fig. 2 B is the circuit diagram that shows according to the shift buffer memory unit of first preferred embodiment of the present invention;
Fig. 2 C is the wherein circuit diagram of an offset buffer that shows according to first preferred embodiment of the present invention;
Fig. 2 D is the oscillogram that shows according to several unlike signals of first preferred embodiment of the present invention;
Fig. 3 is the structure schematic diagram that shows according to the discharge switch module of first preferred embodiment of the present invention;
Fig. 4 A is the circuit diagram that shows according to an offset buffer of second preferred embodiment of the present invention;
Fig. 4 B is the oscillogram that shows several unlike signals of second preferred embodiment of the present invention;
Fig. 5 A is the analog waveform figure that shows according to each clock signal in the shift buffer memory unit of first preferred embodiment of the present invention;
Fig. 5 B is the analog waveform figure that shows according to the pixel current potential of the corresponding generation of thin film transistor (TFT) institute of several different sizes of first preferred embodiment of the present invention; And
Fig. 5 C is the analog waveform figure of grid impulse signal of the corresponding generation of thin film transistor (TFT) institute that shows several different sizes of first preferred embodiment of the present invention.
Drawing reference numeral:
1 power control circuit, 2 gate driver circuit unit
4,2422 gate lines, 5,2442 data lines
9 XON circuit, 10 accurate bit shift devices
11 charge, 22 gate driver circuits
20 liquid crystal displays, 24 grid array substrates
26 signaling control units, 242 gate driver circuit unit
244 source electrode drive circuit unit, 246,446 offset buffers
252 thin film transistor (TFT)s, 262 voltage up converting circuit
264 power controls, 268 accurate displacement digital devices
270 flexible circuit boards, 272 contact mats
250 pixel cells, 280 rising driver modules
282 rising modules
The drop-down control module of 284 first clocks
The drop-down control module of 288 second clocks
290 are used to eliminate the device of ghost
300 cablings
292,492, the G grid
294,494, the S source electrode
296, the D drain electrode
400 waveforms indicate
The input node of Q rising module
The signal output terminal of OUT rising module
The setting signal of N-1 upper level shift buffer memory unit
ST, STV initial setting signal
CKV1 first clock signal
CKV2 second clock signal
T1, T2, T3, TMIN thin film transistor (TFT)
Gn, G (1)～G (N) grid impulse signal
D (1)～D (M) data
The Vin power supply input signal
V
SS, V
GlLow-voltage source
V
DD, V
GhHigh voltage source
XON XON input signal
C
LCLiquid crystal capacitance
C
SStorage capacitors
During the t0 delayed discharge
The t1 unused time
T2 sample time
Embodiment
Below put up with diagram and describe technology contents of the present invention in detail.
Please consult earlier shown in Fig. 2 A and Fig. 2 B, be a kind of liquid crystal display 20 that is used to eliminate ghost according to one first preferred embodiment of the present invention, have a upper substrate (not shown) and an infrabasal plate such as grid array substrate 24, and seal liquid crystal (LC) molecule between this upper and lower base plate up for safekeeping.Configuration one gate driver circuit unit 242 (as GOA) and one source pole drive circuit unit 244 on this grid array substrate 24.In the present embodiment shown in Fig. 2 B, this this gate driver circuit unit 242 can be a shift buffer memory unit, have a plurality of odd level offset buffer 246 and a plurality of even level offset buffers 246, wherein these odd levels and even level shift buffer memory unit 246 are all exported the grid (G) of grid impulse signal (G (1)～G (N)) with each thin film transistor (TFT) (TFT) 252 of triggering forming array pixel (Pixel) unit 250 respectively in regular turn via several gate lines (or sweep trace) 2422, and source electrode drive circuit unit 244 is sent to the source electrode (S) of thin film transistor (TFT) (TFT) 252 via associated data line (D (1)～D (N)) 2442 luma data that transmit, with the storage capacitors (C that drain electrode (D) is connected
S) and liquid crystal capacitance (C
LC) discharge and recharge.In fact, during the start (Power on) of liquid crystal display 20, can make between this two substrates and produce electric field, make the liquid crystal (LC) of respective pixel unit 250 electrically charged as forming liquid crystal capacitance (C
S).
Shown in Fig. 2 A and Fig. 2 B, this liquid crystal display 20 also has a traditional signaling control unit 26, can give this grid array substrate 24 to transmit each signal source by the contact mat (Pad) 272 that a flexible circuit board (FPC) 270 is electrically connected these grid array substrate 24 edges in present embodiment.This classical signal control module 26 can be the product that industry is commonly used, and it comprises that a voltage up converting circuit (Boost circuit) 262, one power control (as PWM IC) 264 reaches displacement digital device (Level shifter) 268 surely.Because voltage up converting circuit 262 consist of a big electric capacity and an inductance, to promote the high voltage source (V that produces by power control 264
Gh) and low-voltage source (V
Gl) current potential, can charge under the situation that the system power supply supply is arranged to this big electric capacity; Otherwise the moment after the power supply supply is cut off, this big electric capacity can discharge output one near high voltage source (V
Gh) current potential.This accurate displacement digital device (Level shifter) 268 is according to the high voltage source (V of input
Gh) and low-voltage source (V
Gl) produce the high voltage source (V of accurate bit shift
DD) and low-voltage source (V
SS) give each offset buffer 246, with height potential reference as each offset buffer 246 output grid impulse signal (G (1)～G (N)).Because power control 264 is to receive a power supply input signal Vin, so the accurate bit map of each signal source of these power control 264 outputs is reference with the accurate position of this power supply input signal Vin all.For example, when the power control 264 of this signaling control unit 26 receives a waveform when being the power supply input signal Vin of drop edge, the supply of representative system power supply is cut off, and the big capacitor discharge output one that impels this voltage up converting circuit (Boost circuit) 262 is near high voltage source (V
Gh) high levle, and then descend gradually, form a high voltage source and postpone (V
GhDelay) discharge is wherein except low-voltage source (V
SS) accurate position unaffected and be raised to gradually outside the 0V, can relatedly influence this signaling control unit 26 provides the offset buffers at different levels 246 of the gate driver circuit unit 242 that the initial setting signal (STV), first clock signal (CKV1), the second clock signal (CKV2) (shown in Fig. 2 D) that all are high levle give this grid array substrate 24 to use in this moment simultaneously.
Shown in Fig. 2 A, Fig. 2 B and Fig. 2 C, the offset buffers at different levels 246 of the gate driver circuit unit 242 of this grid array substrate 24 have a signal output terminal OUT, and are electrically connected several signal sources that the cabling of each contact mat 272 transmits respectively and comprise as initial setting signal (STV), first clock signal (CKV1), second clock signal (CKV2) and low-voltage source (V
SS), export the thin film transistor (TFT) (TFT) 252 of a grid impulse signal G (N) in this signal output terminal OUT to corresponding pixel cell 250.Wherein first clock signal (CKV1) and second clock signal (CKV2) can be anti-phase each other, and according to the difference of odd level or even level offset buffer 246, the connected mode of signal is also different.In present embodiment, except first order offset buffer 246 is to receive this initial setting signal (STV) output grid impulse signal G (N), other N level offset buffers 246 are that the output signal (N-1) that receives the offset buffer 246 of upper level drives, but be not to be used to limit spirit of the present invention, also available other modes of the present invention are connected in series offset buffer 246.
As Fig. 2 C is the internal circuit synoptic diagram that shows according to the offset buffers at different levels 246 of the first embodiment of the present invention, this offset buffer 246 mainly comprises and draws driver module 280 on one, drawing-die piece 282 on one, the drop-down control module 284 of one first clock, the drop-down control module 288 of one second clock and one is used to eliminate the device 290 of ghost, draw driver module 280 to comprise a first transistor T1 on wherein being somebody's turn to do, its drain electrode (Drain) is to be connected the setting signal (N-1) that initial setting signal (as STV) is made initial setting or transmitted by the upper level offset buffer jointly with grid (Gate), and the input node Q that its source electrode (Source) connects produces drive signal.
Should go up drawing-die piece 282 and have a transistor seconds T2, its grid connects this input node Q to be triggered with the drive signal of drawing driver module 280 on being subjected to, its drain electrode is that odd level or even level are selected to connect first clock signal (CKV1) or second clock signal (CKV2) according to this offset buffer 246, and its source electrode connects this signal output terminal OUT.
Drop-down control module 284 of this first clock and the drop-down control module 288 of second clock are electrically connected the signal output terminal OUT of drawing-die piece 282 on this respectively, wherein at least one drop-down control module 284,288 comprise that a drop-down driver module reaches drawing-die piece (not shown), behind this grade offset buffer 246 outputs one grid impulse signal G (N), utilize the drop-down control module 288 of drop-down control module 284 of this first clock and second clock to be electrically connected this low-voltage source (V by this
SS) to distinguish the accurate position of drop-down first clock signal (CKV1) or second clock signal (CKV2).
The device 290 that is used to eliminate ghost that is used to eliminate ghost according to first preferred embodiment of the present invention comprises at least one discharge switch module (can also be formed by many pack modules), in this first embodiment, be to realize with one the 3rd transistor T 3, the grid 292 of the 3rd transistor T 3 is to be electrically connected initial setting signal (STV), its source electrode 294 is electrically connected to first clock signal (CKV1), and its drain electrode 296 is electrically connected to signal output terminal OUT and the source electrode of the transistor seconds T2 of drawing-die piece 282 on this.
Shown in Fig. 2 A, Fig. 2 C and Fig. 2 D, when the power control 264 of this signaling control unit 26 received the power supply input signal Vin of a high levle, the supply of representative system power supply was at open state; Otherwise when power control 264 receives the moment that a waveform is the power supply input signal Vin of drop edge, the supply of representative system power supply is shut down, utilizes the design of power control 264, makes high voltage source (V
Gh) waveform initially presents (DelayDischarge Time) t0 during the moment delayed discharge that descends gradually then of high levle, by this except low-voltage source (V
SS) accurate position unaffected and rise to outside the 0V gradually, can related initial setting signal (STV), first clock signal (CKV1) and the second clock signal (CKV2) of influencing during this delayed discharge, also occur the moment high levle in the t0, and then discharge drops to the waveform of 0V (shown in Fig. 2 D) gradually.In addition, at initial setting signal (STV), first clock signal (CKV1) and second clock signal (CKV2) from moment high levle be discharged to gradually 0V this section during t0, the grid 292 of the 3rd transistor T 3 of offset buffers 246 at different levels is according to the triggering of the initial setting signal (STV) of high levle, be electrically connected first clock signal (CKV1) and this signal output terminal OUT of high levle, make offset buffers 246 at different levels can export the grid impulse signal of high levle (G (1)～G (N)) simultaneously, drop to 0V more gradually, so that each pixel cell of the correspondence in the viewing area is discharged and recharged, make liquid crystal capacitance C
SIn electric charge to discharge to reduce pixel current potential (Pixel Potential).What need pay special attention to is, utilize design of the present invention, during the system power supply start (being that power supply input signal Vin is high levle), when first clock signal (CKV1) that connects as the source electrode 294 of discharge switch module (the 3rd transistor T 3) is high levle, therefore initial setting signal (STV) is all low level, can not trigger the grid 292 of discharge switch module (the 3rd transistor T 3) and has influence on offset buffers 246 at different levels operate as normal originally.In another embodiment, this device 290 that is used to eliminate ghost also can change to be located at outside these offset buffers 246 at different levels, as long as each signal source that is electrically connected each offset buffer 246 and signaling control unit 26 is arranged.In other embodiment, but the grid 292 of the 3rd transistor T 3 is reconfiguration first clock signal (CKV1) also, its source electrode 294 reconfiguration initial setting signals (STV), but compare, the system dependability (Relability) that is obtained with grid 292 connection initial setting signals (STV) in first embodiment is preferable.
When system power supply one start (being that power supply input signal Vin is high levle), this initial setting signal (STV) is a high levle, but first clock signal (CKV1) that the source electrode 294 of discharge switch module (the 3rd transistor T 3) connects is a low level, by this simultaneously the grid impulse signal (G (1)～G (N)) of drop-down offset buffers 246 at different levels to low level, as the output signal of offset buffers 246 at different levels is reseted (Reset), so the present invention's function of having signal to reset also can reach start the time.
In addition, in first embodiment, the big electric current of moment causes perforation (Throughhole) to burn when avoiding shutting down, as Fig. 2 A and shown in Figure 3, the cabling 300 that this signaling control unit 26 is formed via single kind of metal from contact mat 272 is connected directly to the discharge switch module (i.e. the source electrode 294 of the 3rd transistor T 3) of device 290 that is used to eliminate ghost of this each offset buffer 246 transmitting first clock signal (CKV1) (or second clock signal CKV2), and this cabling 300 has single sectional area and do not use perforation (Through hole) mode to be connected with other elements.
As Fig. 4 A is the internal circuit synoptic diagram that shows according to the offset buffers at different levels 446 of the second embodiment of the present invention, its configuration is similar to aforementioned first embodiment, unique difference is: the source electrode 494 reconfiguration second clock signals (CKV2) of the 3rd transistor T 3 of the offset buffer 446 of second embodiment, it is constant that all the other end points such as grid 492 connect initial setting signal (STV).And because the signal source that source electrode 494 connects changes, so the square frame label 400 as Fig. 4 B shows, power supply input signal Vin and initial setting signal (STV) be all high levle during, corresponding second clock signal waveform will change and is made as low level, just can reach the function that has signal to reset when reaching start., do not repeat them here because identical as for other signal waveforms with first embodiment shown in Fig. 2 B.
Please further simultaneously with reference to figure 5A, Fig. 5 B and Fig. 5 C, Fig. 5 A shows the analog waveform figure of first clock signal (CKV1) and second clock signal (CKV2), wherein simulate moment at system closedown time t1, this first clock signal V (CKV1) and second clock signal V (CKV2) all rise approximately to 1, the high levle of 60761V, after system closedown time t1 during the measurement of about 1000us in this first clock signal (CKV1) maintain and be 28, the square wave of 60761V high levle, drop to approaching-0.00164V then, wherein t2 is sample time.
The analog waveform figure of Fig. 5 B display pixel current potential (Pixel Potential), wherein utilize the thin film transistor (TFT) (TFT) of a plurality of different sizes to test respectively as the 3rd transistor T 3 of aforementioned offset buffer 446, because the usefulness of discharge can be depending on the size of thin film transistor (TFT) (TFT), so-called thin film transistor (TFT) (TFT) size is to discuss than (W/L) with length with the channel width of this thin film transistor (TFT) (TFT).Generally speaking, channel width and length are than (W/L) the big person of healing, discharging efficiency better (being that discharge time is faster), V shown in Fig. 5 B (P1_W500) represents the pixel current potential of the minimum thin film transistor (TFT) correspondence of W/L=500/5.5, V (P1_W750) represents the pixel current potential of the thin film transistor (TFT) correspondence of W/L=750/5.5, V (P1_W1000) represents the pixel current potential of the thin film transistor (TFT) correspondence of W/L=1000/5.5, and V (P1_W1500) represents the pixel current potential of the thin film transistor (TFT) correspondence of W/L=1500/5.5.In Fig. 5 B, can find, under the driving of same high levle first clock signal CKV 1, after system closedown time t1 during the measurement of about 1000us, the discharging efficiency of the thin film transistor (TFT) (TFT) of these different sizes is the poorest with the minimum thin film transistor (TFT) performance of V (P1_W500) representative, its sample time the t2 correspondence the pixel current potential still up to 11.81739V, and the performance of the velocity of discharge of the maximum thin film transistor (TFT) of V (P1_W1500) representative is the fastest, its sample time the t2 correspondence the pixel current potential closely-0.0000V, but it is in order to consider the problem of element cost, the most suitable with the discharging efficiency of the thin film transistor (TFT) of V (P1_W750) representative.Fig. 5 C shows the analog waveform figure of the grid impulse signal output of offset buffer (as GOA), wherein equally with the thin film transistor (TFT) (TFT) of a plurality of different sizes as the 3rd transistor T 3 of aforementioned offset buffer 446 to test, represent the grid impulse signal of the minimum thin film transistor (TFT) correspondence of W/L=500/5.5 as V (G1_W500), V (G1_W750) represents the grid impulse signal of the thin film transistor (TFT) correspondence of W/L=750/5.5, V (G1_W1000) represents the grid impulse signal of the thin film transistor (TFT) correspondence of W/L=1000/5.5, and V (G1_W1500) represents the grid impulse signal of the thin film transistor (TFT) correspondence of W/L=1500/5.5.
In addition, in this method that is used to eliminate ghost of introducing the preferred embodiment of the present invention of a kind of foundation, be applicable to liquid crystal display, it has a signaling control unit and multistage offset buffer, comprising:
When the moment that this liquid crystal display is shutting down, signaling control unit provides one first signal and a secondary signal that all is high levle simultaneously, and a wherein signal of this first signal and secondary signal is that initial setting signal (STV) is used for initial setting first order offset buffer, and another signal can be first clock signal CKV 1 or second clock signal CKV2; And
Utilize the grid of first signal triggering, the one discharge switch module of high levle as a thin film transistor (TFT), make this discharge switch module be electrically connected the secondary signal of high levle and a signal output terminal of this grade offset buffer, the liquid crystal capacitance CS that gives in the corresponding pixel cell that makes liquid crystal display with the grid impulse signal of exporting a high levle discharges and recharges, so can reduce the problem of power-off ghost shadow (Power-off Afterimage).After first signal and secondary signal present high levle, can slowly be discharged to a low level again.
Based on aforementioned, a kind of device that is used to eliminate ghost provided by the invention, shift buffer memory unit, liquid crystal display and method, high voltage source delayed discharge (the Vgh delay discharge) phenomenon that supply unit (as PWM IC) produces in the time of only need arranging in pairs or groups shutdown, drive several existing signal sources of shift buffer memory unit (as initial setting signal (STV), first clock signal (CKV1) and second clock signal (CKV2)) among any two signal sources form high levles and pixel cell discharged and recharged with control discharge switch module, therefore can be at the residual charge in the shutdown abrupt release viewing area, improve the problem of power-off ghost shadow, drive the discharge switch module and need not set up extra signal source especially, ASIC need not change yet, also need not to use extra accurate bit shift device, so can reduce the element cost and reduce system complexity, also also have the function of starting-up signal replacement (Reset) simultaneously.
In sum, the present invention meets the patent of invention key element, so propose patented claim in accordance with the law.And the above person only is preferred embodiment of the present invention, all those of ordinary skill in the art, and the equivalence of being done under according to the present invention's spirit framework is modified or is changed, and all should be contained in the appended claim scope.
Claims (11)
1. shift buffer memory unit that is used to eliminate ghost, it is characterized in that, described shift buffer memory unit is applicable in the liquid crystal display and connects a signaling control unit, wherein said signaling control unit has one first signal and a secondary signal, the waveform that receives a power supply input signal when described signaling control unit is when being the drop edge, first signal and secondary signal with high levle are provided simultaneously, and described shift buffer memory unit comprises: at least one offset buffer has:
Draw driver module at least one;
Drawing-die piece on one, connect and draw driver module and have a signal output terminal on described, and, export at least one corresponding pixel cell of a signal to liquid crystal display in described signal output terminal according to described first signal and both one of them signals of a secondary signal;
At least one drop-down control module connects the described signal output terminal of going up the drawing-die piece; And
At least one discharge switch module, be electrically connected the secondary signal and the described signal output terminal of going up the drawing-die piece of high levle, wherein said discharge switch module is first signal triggering startup according to high levle, and at least one corresponding pixel cell in the liquid crystal display is discharged.
2. the shift buffer memory unit that is used to eliminate ghost as claimed in claim 1 is characterized in that, describedly draws driver module at least one, is to receive a wherein signal of described first signal and secondary signal for initial setting.
3. the shift buffer memory unit that is used to eliminate ghost as claimed in claim 1, it is characterized in that, described at least one discharge switch module comprises a thin film transistor (TFT), it has, and a grid connects described first signal, one source pole connects secondary signal, and a drain electrode is connected to the signal output terminal of drawing-die piece.
4. the shift buffer memory unit that is used to eliminate ghost as claimed in claim 1 is characterized in that, described at least one drop-down control module comprises that a drop-down driver module reaches drawing-die piece.
5. the shift buffer memory unit that is used to eliminate ghost as claimed in claim 1 is characterized in that, described first signal is an initial setting signal, and secondary signal be one first clock signal and a second clock signal both one of them.
6. the shift buffer memory unit that is used to eliminate ghost as claimed in claim 1 is characterized in that, described first signal is one first clock signal and a second clock signal both one of them, and secondary signal is an initial setting signal.
7. as claim 5 or the 6 described shift buffer memory units that are used to eliminate ghost, it is characterized in that, when first signal or secondary signal are first clock signal, first clock signal is that low level is all high levle with described power supply input signal of correspondence and initial setting signal, and anti-phase each other with the second clock signal.
8. as claim 5 or the 6 described shift buffer memory units that are used to eliminate ghost, it is characterized in that, when first signal or secondary signal are the second clock signal, the second clock signal is that low level is all high levle with described power supply input signal of correspondence and initial setting signal, and anti-phase each other with first clock signal.
9. the shift buffer memory unit that is used to eliminate ghost as claimed in claim 1 is characterized in that, described signaling control unit comprise a power control and surely displacement digital device give described offset buffer so that power supply to be provided.
10. the shift buffer memory unit that is used to eliminate ghost as claimed in claim 1, it is characterized in that described signaling control unit is connected directly to described at least one discharge switch module to transmit first signal or secondary signal from least one contact mat via the cabling with single cross section structure.
11. the shift buffer memory unit that is used to eliminate ghost as claimed in claim 10 is characterized in that, described cabling is that single kind of metal is made.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101697046A CN101383133B (en) | 2008-10-20 | 2008-10-20 | Shifting cache unit for eliminating ghost |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101697046A CN101383133B (en) | 2008-10-20 | 2008-10-20 | Shifting cache unit for eliminating ghost |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101383133A CN101383133A (en) | 2009-03-11 |
| CN101383133B true CN101383133B (en) | 2010-12-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2008101697046A Expired - Fee Related CN101383133B (en) | 2008-10-20 | 2008-10-20 | Shifting cache unit for eliminating ghost |
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Families Citing this family (26)
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| CN102662284B (en) * | 2009-12-17 | 2014-12-31 | 联咏科技股份有限公司 | Grid drive circuit and relevant liquid crystal display |
| CN101996559B (en) * | 2010-10-19 | 2012-10-24 | 友达光电股份有限公司 | Grid array shifting buffer memory |
| TW201234344A (en) * | 2011-02-11 | 2012-08-16 | Chimei Innolux Corp | Liquid crystal display panel |
| CN103927998A (en) * | 2013-12-27 | 2014-07-16 | 上海天马微电子有限公司 | Driving unit, shifting register circuit, array substrate and residual shadow removing method |
| CN103928000B (en) | 2013-12-30 | 2016-08-17 | 厦门天马微电子有限公司 | Film crystal tube drive circuit and driving method, liquid crystal indicator |
| CN103869516B (en) * | 2014-03-12 | 2016-04-06 | 京东方科技集团股份有限公司 | display panel discharge circuit and display device |
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| CN104575433A (en) * | 2015-02-04 | 2015-04-29 | 京东方科技集团股份有限公司 | GOA reset circuit and driving method, array substrate, display panel and device |
| CN105047158B (en) | 2015-08-21 | 2017-11-10 | 深圳市华星光电技术有限公司 | A kind of GOA circuits and liquid crystal display |
| CN105185333B (en) | 2015-09-14 | 2018-05-11 | 深圳市华星光电技术有限公司 | A kind of gate driving circuit of liquid crystal display device |
| CN105096902B (en) * | 2015-09-28 | 2018-09-11 | 京东方科技集团股份有限公司 | A kind of shift register, its driving method, gate driving circuit and display device |
| CN105096903B (en) * | 2015-09-28 | 2018-05-11 | 深圳市华星光电技术有限公司 | A kind of GOA circuits and liquid crystal display |
| CN105161065B (en) * | 2015-09-30 | 2017-10-27 | 深圳市华星光电技术有限公司 | Liquid crystal display signal control circuit, display panel and display device |
| CN106486085A (en) * | 2017-01-03 | 2017-03-08 | 京东方科技集团股份有限公司 | Shift-register circuit, driving method, GOA circuit and display device |
| CN107358924B (en) * | 2017-07-12 | 2019-03-15 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and its driving method, display panel |
| US10403220B2 (en) | 2017-07-12 | 2019-09-03 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd | GOA circuit, driving method, and display panel |
| CN109817137B (en) * | 2017-11-20 | 2024-04-02 | 京东方科技集团股份有限公司 | Shift register circuit, driving method thereof and related device |
| CN107967889B (en) * | 2018-01-02 | 2021-08-03 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit and control method |
| CN108694903B (en) | 2018-05-28 | 2020-04-07 | 武汉华星光电技术有限公司 | Array substrate row driving circuit |
| CN109545164B (en) | 2019-01-02 | 2021-04-09 | 合肥京东方显示技术有限公司 | Shifting register unit and driving method thereof, grid driving circuit and display device |
| CN110264948B (en) * | 2019-06-25 | 2022-04-01 | 京东方科技集团股份有限公司 | Shifting register unit, driving method, grid driving circuit and display device |
| CN110929645B (en) * | 2019-11-22 | 2023-07-28 | 北京集创北方科技股份有限公司 | Signal acquisition device, acquisition method, display device and electronic equipment |
| CN113257202B (en) * | 2021-04-30 | 2022-04-19 | 北海惠科光电技术有限公司 | Gate drive circuit and drive method of display panel and display device |
-
2008
- 2008-10-20 CN CN2008101697046A patent/CN101383133B/en not_active Expired - Fee Related
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| CN101383133A (en) | 2009-03-11 |
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