CN101364539B - Gate layer manufacturing method, semiconductor device manufacturing method and semiconductor construction - Google Patents
Gate layer manufacturing method, semiconductor device manufacturing method and semiconductor construction Download PDFInfo
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- CN101364539B CN101364539B CN 200710044813 CN200710044813A CN101364539B CN 101364539 B CN101364539 B CN 101364539B CN 200710044813 CN200710044813 CN 200710044813 CN 200710044813 A CN200710044813 A CN 200710044813A CN 101364539 B CN101364539 B CN 101364539B
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Abstract
A manufacturing method of a grid layer comprises the steps of providing a semiconductor substrate with a grid electrode insulating layer; forming a first polycrystalline silicon layer on the semiconductor substrate; forming a second polycrystalline silicon layer with randomly distributed crystal grains; and carrying out ion implantation doping to the second and the first polycrystalline silicon layers. The invention also provides a manufacturing method of a semiconductor device, and a semiconductor structure. The method can prevent or reduce doping ions from entering into or passing through the grid electrode insulating layer when carrying out ion implantation doping to the grid electrode layers.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly the manufacture method of a kind of manufacture method of grid layer, semiconductor device and semiconductor structure.
Background technology
Along with the continuous progress of semiconductor fabrication process, integrated level is more and more higher, and the critical size of grid that represents the semiconductor fabrication process level is also more and more less; In metal oxide semiconductor transistor, generally adopt polysilicon as the material of making grid, and, be to reduce power consumption, raising response speed, usually polysilicon is mixed, form the polysilicon that mixes, to reduce the resistance of grid, for example, polysilicon gate for N-type metal oxide semiconductor transistor (NMOS), mix N-type impurity, the polysilicon gate for P-type mos transistor (PMOS) mixes p type impurity.
Utilize the manufacturing process of doped polycrystalline silicon formation grid as follows: at first to deposit gate insulator in Semiconductor substrate, deposit spathic silicon layer on described gate insulator; Then, described polysilicon layer is carried out ion implantation doping, the impurity that mixes is used for improving the resistivity of polysilicon layer; Then, remove the part polysilicon layer by photoetching and etching technics, form grid;
Number of patent application is the manufacture method that the United States Patent (USP) of US 6949471 B2 discloses a kind of grid, and Fig. 1 to Fig. 3 is the generalized section of each step corresponding construction of the manufacture method of the disclosed grid of described United States Patent (USP);
As shown in Figure 1, at first provide Semiconductor substrate 210, form gate insulator 212 in described Semiconductor substrate 210, form grid layers (Gate Layer) 214 at described gate insulator 212, the material of described grid layer 214 can be polysilicon;
Described grid layer 214 is mixed, to reduce the resistance of described grid layer 214;
As shown in Figure 2, form mask layer 216 and 218 at described grid layer 214, wherein, described mask layer 216 can be silica, and described mask layer 218 can be silicon oxynitride;
As shown in Figure 3, by photoetching and the graphical described grid layer 214 of etching, form grid 220, and remove described mask layer 216 and 218.
The polysilicon that described employing is mixed forms in the technique of grid, and the energy of Implantation and energy are all very large during doping, and the energy of injection can reach 5KeV to 15KeV, and dosage can reach 2 * 10
15Atom/cm
2To 5 * 10
15Atom/cm
2, the ion of injection can enter or penetrate gate insulator, and the metal oxide semiconductor device threshold voltage shifts, leakage current increase etc. that cause formation are problem electrically.
Summary of the invention
The invention provides a kind of manufacture method of grid layer, manufacture method and the semiconductor structure of semiconductor device, the present invention can avoid or reduce the problem that to the sub-dopant implant of grid leafing time doping ion entered or penetrated gate insulator.
The manufacture method of a kind of grid layer provided by the invention comprises:
Semiconductor substrate with gate insulator is provided;
Form the first polysilicon layer in described Semiconductor substrate;
Form the second polysilicon layer of crystal grain disorder distribution at described the first polysilicon layer;
Described the second polysilicon layer and the first polysilicon layer are carried out ion implantation doping.
Optionally, the method that forms described the second polysilicon layer is low-pressure chemical vapor deposition.
Optionally, the reacting gas that forms described the second polysilicon layer is SiH
4, Si
2H
6And H
2
Optionally, the technique that forms described the second polysilicon layer is carried out or is carried out respectively in different process cavity with the technique original position that forms the first polysilicon layer.
Optionally, carry out forming amorphous silicon layer at described the second polysilicon layer before the ion implantation doping.
Optionally, before carrying out ion implantation doping, form the 3rd polysilicon layer at described the second polysilicon layer.
Optionally, the technique that forms described the 3rd polysilicon layer is identical with the technique that forms the first polysilicon layer.
Optionally, the technique that forms described the 3rd polysilicon layer can original position be carried out or carry out respectively in different process cavity from the technique that forms described the second polysilicon layer.
Optionally, described the second polysilicon layer is one or more layers.
Optionally, described the second polysilicon layer is multilayer, and along with the increase of the number of plies, crystallite dimension reduces.
Optionally, after carrying out ion implantation doping, described the first polysilicon layer and the second polysilicon layer are annealed.
The present invention also provides a kind of manufacture method of semiconductor device, comprising:
Semiconductor substrate with gate insulator is provided;
Form the first polysilicon layer in described Semiconductor substrate;
Form the second polysilicon layer of crystal grain disorder distribution at described the first polysilicon layer;
Described the second polysilicon layer and the first polysilicon layer are carried out ion implantation doping;
Graphical described the second polysilicon layer and the first polysilicon layer form grid.
Optionally, the method that forms described the second polysilicon layer is low-pressure chemical vapor deposition.
Optionally, the reacting gas that forms described the second polysilicon layer is SiH
4, Si
2H
6And H
2
Optionally, the technique that forms described the second polysilicon layer is carried out or is carried out respectively in different process cavity with the technique original position that forms the first polysilicon layer.
Optionally, the method further comprises: mix at described grid formation metal silicide with to the Semiconductor substrate of described grid both sides.
Optionally, before or after graphical described the second polysilicon layer and the first polysilicon layer, described the second polysilicon and the first polysilicon layer are annealed.
The present invention also provides a kind of semiconductor structure, comprising:
Semiconductor substrate with gate insulator;
The first polysilicon layer on the described Semiconductor substrate;
The second polysilicon layer of the crystal grain disorder distribution on described the first polysilicon layer.
Optionally, described the second polysilicon layer is one or more layers.
Optionally, on described the second polysilicon layer, also has the 3rd polysilicon layer.
Compared with prior art, the present invention has the following advantages:
By forming the second polysilicon layer of crystal grain disorder distribution at the first polysilicon layer, to reduce or to eliminate the phenomenon that when the first polysilicon layer is carried out ion implantation doping doping ion entered or penetrated gate insulator; Because crystal grain disorder distribution in the second polysilicon layer, the direction in crystal grain gap also has unordered distribution; Thereby, when the first polysilicon layer is carried out ion implantation doping, the ion that injects is owing to be subjected to the stopping of crystal grain of the disorder distribution of this second polysilicon layer, when entering into the first polysilicon layer, energy can reduce to some extent, thereby can reduce or the ion avoiding injecting enters into or pass gate insulator; Can suppress or eliminate threshold voltage shift, problem that leakage current is larger, improve the stability of the semiconductor device that forms, improve the yield of product;
In addition, this second polysilicon layer be positioned at the first polysilicon layer above, the first polysilicon layer that also namely between the second polysilicon layer and gate insulator, has columnar grain, has good interfacial characteristics between this first polysilicon layer and the gate insulator, the second polysilicon layer can directly not contact with gate insulator, thereby can not affect described interfacial characteristics, the semiconductor device of formation still has preferably stability;
Forming the technique of described the second polysilicon layer and the technique of described the first polysilicon layer of formation can original position carry out, can avoid repeatedly carrying or the transmission of Semiconductor substrate, reduce contaminated probability, help to improve stability and the yield of the semiconductor device of formation, simultaneously, can also shorten the manufacturing cycle, reduce manufacturing cost.
Description of drawings
Fig. 1 to Fig. 3 is the generalized section of each step corresponding construction of embodiment of manufacture method of a kind of grid of prior art;
Fig. 4 to Fig. 7 is the generalized section of each step corresponding construction of the first embodiment of the manufacture method of grid layer of the present invention;
Fig. 8 is the generalized section relevant with the second embodiment of the manufacture method of grid layer of the present invention;
Fig. 9 is the generalized section relevant with the 3rd embodiment of the manufacture method of grid layer of the present invention;
Figure 10 is the generalized section relevant with the 4th embodiment of the manufacture method of grid layer of the present invention;
Figure 11 is the flow chart of embodiment of the manufacture method of semiconductor device of the present invention.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Development along with semiconductor fabrication process, the size of grid is done less and less, is the quick response of the semiconductor device that guarantee to form and the characteristic of low-power consumption, needs to reduce the resistance of grid, wherein one of method is when forming polysilicon gate, and polysilicon is carried out ion implantation doping; Yet when Implantation, because the energy of the ion that injects is larger, the ion that causes injecting can pass gate insulator, enters into conducting channel.
The invention provides a kind of manufacture method of grid layer, when forming the polycrystalline silicon grid layer of making grid, at least form in this grid layer that a crystal grain is unordered and arrange the polysilicon layer of (or distribution), this polysilicon layer can slow down the energy of the ion of injection, avoids producing when Implantation the problem that penetrates gate insulator.
Below in conjunction with embodiment the manufacture method of described grid layer is described in detail.
Fig. 4 to Fig. 7 is the generalized section of the corresponding structure of each step of the first embodiment of the manufacture method of grid layer of the present invention.
As shown in Figure 4, provide Semiconductor substrate 10, described Semiconductor substrate 10 can be a kind of in monocrystalline silicon, polysilicon, the amorphous silicon; Described Semiconductor substrate 10 also can have silicon on the insulating barrier (Silicon On Insulator, SOI) structure; In described Semiconductor substrate 10, can mix N-type impurity or p type impurity.
Prerinse is carried out on described Semiconductor substrate 10 surfaces, removed oxide or other impurity on described Semiconductor substrate 10 surfaces.Because described Semiconductor substrate 10 is exposed in the air and can forms natural oxidizing layer on the surface, the thickness evenness of this natural oxidizing layer and rete characteristic are all relatively poor, for avoiding this natural oxidizing layer on the impact of the rete characteristic of the gate insulator of follow-up formation, need this natural oxidizing layer is removed.Common removal method is wet etching, such as BOE or HF or RCA cleaning etc.
Then, form gate insulator 12 in described Semiconductor substrate 10, described gate insulator 12 is oxygen containing dielectric layer, and described oxygen containing dielectric layer comprises silica and silicon oxynitride; Wherein, the method that forms silica is high temperature furnace pipe oxidation, rapid thermal oxidation (Rapid ThermalOxidation, RTO) or the original position water vapour produce oxidation (In-Situ Sream Generation, ISSG) a kind of in, described silica is carried out nitrogen treatment can form silicon oxynitride, wherein the method for nitrogenize comprises a kind of in high temperature furnace pipe nitrogenize, rapid thermal treatment nitrogenize or the pecvd nitride.
As shown in Figure 5, form the first polysilicon layer 14 at described gate insulator 12, the formation method of described the first polysilicon layer 14 can be Low Pressure Chemical Vapor Deposition, and reacting gas comprises SiH
4Or Si
2H
6, the uniformity for the rete of the first polysilicon layer 14 of improve forming can also add N in reacting gas
2
Among the embodiment therein, the temperature of reaction is 700 to 740 degree, and the pressure of reaction chamber is 200 to 300T, and the reaction time is 10 to 50 seconds, can control the thickness of the first polysilicon layer 14 of formation according to the time of reaction; The first polysilicon layer 14 that forms has column structure, and the crystal grain gap is approximately perpendicular to the surface of Semiconductor substrate 10;
After forming the first polysilicon layer 14, because the crystallite dimension of column is larger, and the crystal grain gap is approximately perpendicular to the surface of Semiconductor substrate 10, if directly carry out the operation of ion implantation technology, the ion that injects has part and enters into this first polysilicon layer 14 along described crystal grain gap, and this crystal grain gap is less to the resistance of the ion that injects, so that the implantation affiliation further enters into gate insulator 12, even passes this gate insulator 12 and enters into conducting channel; Make the decreasing insulating of gate insulator 12, and cause the problem such as threshold voltage shift, leakage current increase of the semiconductor device of formation;
For avoiding described problem, present embodiment formed one second polysilicon layer 16 again on described the first polysilicon layer before carrying out ion implantation doping, as shown in Figure 6, and the crystal grain disorder distribution of this second polysilicon layer 16;
Because crystal grain disorder distribution in this second polysilicon layer 16, the direction in crystal grain gap is also no longer the same with the first polysilicon layer 14, is approximately perpendicular to the surface of Semiconductor substrate 10, but also has unordered distribution; Thereby, when the first polysilicon layer 14 is carried out ion implantation doping, the ion that injects is owing to be subjected to the stopping of crystal grain of the disorder distribution of this second polysilicon layer 16, when entering into the first polysilicon layer 14, energy can reduce to some extent, thereby can reduce or the ion avoiding injecting enters or pass gate insulator 12; The also i.e. effect of this second polysilicon layer 16 with buffering;
In addition, this second polysilicon layer 16 be positioned at the first polysilicon layer 14 above, the first polysilicon layer 14 that also namely between the second polysilicon layer 16 and gate insulator 12, has columnar grain, has good interfacial characteristics between this first polysilicon layer 14 and the gate insulator 12, the second polysilicon layer 16 can directly not contact with gate insulator 12, thereby can not affect described interfacial characteristics, the semiconductor device of formation still has preferably stability;
Among the embodiment therein, the method that forms described the second polysilicon layer 16 is Low Pressure Chemical Vapor Deposition, and reacting gas comprises SiH
4, Si
2H
6And H
2, the temperature of reaction is 700 to 740 degree, the pressure of reaction chamber is 200 to 300T, reaction time is 10 to 30 seconds, can control the thickness of the second polysilicon layer 16 of formation according to the time of reaction, after the reaction, the crystal grain disorder distribution in the second polysilicon layer 16 of formation;
For improving the uniformity of the rete that forms the second polysilicon layer 16, in reacting gas, also can add N
2
In addition, the technique that forms described the second polysilicon layer 16 can original position be carried out or carry out respectively in different process cavity with the technique that forms described the first polysilicon layer 14;
If carry out at same process cavity situ, can avoid repeatedly carrying or the transmission of Semiconductor substrate 10, reduce contaminated probability, help to improve stability and the yield of the semiconductor device of formation; Simultaneously, also can shorten the manufacturing cycle, reduce manufacturing cost;
As shown in Figure 7, form described the second polysilicon layer 16 after, described the second polysilicon layer 16 and the first polysilicon layer 14 are carried out ion implantation doping, the impurity that mixes can be the impurity such as phosphorus, arsenic, boron; The energy of Implantation is 5KeV to 15KeV;
Because buffering or the barrier effect of unordered crystal grain in the second polysilicon layer 16, so that the ion that injects energy after through the second polysilicon layer 16 decreases, the ion of injection can be entered in the situation of the first polysilicon layer 14, reduce as much as possible to enter gate insulator 12 or do not enter gate insulator 12;
In a further embodiment, can carry out selective doping to the second polysilicon layer 16 and the first polysilicon layer 14, such as, carry out the Implantation of N-type impurity in the zone of needs being made NMOS, carry out the Implantation of p type impurity in the zone of needs being made PMOS, described selective doping need to define by photoetching process the zone of doping, repeats no more here;
After finishing ion implantation doping process, described the second polysilicon layer 16 and the first polysilicon layer 14 are carried out annealing process, pass through annealing process, can make again crystallization of crystal grain in described the second polysilicon layer 16, formation is similar to the columnar grain in described the first polysilicon layer 14, perhaps form with the first polysilicon layer 14 in identical columnar grain, thereby make this second polysilicon layer 16 and the first polysilicon layer 14 have roughly the same characteristic, common grid layer as the formation grid.
In addition, this annealing process also can make the ion that is injected in the second polysilicon layer 16 and the first polysilicon layer 14 be activated.
Fig. 8 is the generalized section relevant with the second embodiment of the manufacture method of grid layer of the present invention;
As shown in Figure 8, after forming described the second polycrystal layer 16, carry out before the Implantation, can also form the 3rd polysilicon layer 18 at described the second polycrystal layer 16, described the 3rd polysilicon layer 18 can adopt identical manufacturing process manufacturing with described the first polysilicon layer 14, thickness can be different, and namely the crystal grain in described the 3rd polysilicon layer 18 also has column structure; Then described the 3rd polysilicon layer 18, the second polysilicon layer 16 and the first polysilicon layer 14 are carried out ion implantation doping and annealing.Described the second polysilicon layer 16 can play to the ion that injects buffering or barrier effect when carrying out ion implantation doping;
But described the 3rd polysilicon layer 18, the second polysilicon layer 16 and the first polysilicon layer 14 original positions are carried out or are carried out respectively in different process cavity;
In addition, the thickness of described the 3rd polysilicon layer 18, the second polysilicon layer 16 and the first polysilicon layer 14 can adjusting according to different semiconductor device.
Fig. 9 is the generalized section relevant with the 3rd embodiment of the manufacture method of grid layer of the present invention, as shown in Figure 9, after forming described the second polysilicon layer 16, carries out before the Implantation, can also form amorphous silicons 17 at described the second polysilicon layer 16; Then described amorphous silicon layer 17, the second polysilicon layer 16, the first polysilicon layer 14 are carried out ion implantation doping and annealing.Described amorphous silicon layer 17 and described the second polysilicon layer 16 can play buffering or stop when carrying out Implantation to the ion that injects effect.
Figure 10 is the generalized section relevant with the 4th embodiment of the manufacture method of dividing grid layer of the present invention, described the second polysilicon layer 16 can be multilayer, Figure 10 provides described the second polysilicon layer 16 and is two-layer schematic diagram, be that described the second polysilicon layer 16 comprises 16a and 16b, crystal grain among wherein said the second polysilicon layer 16b and the 16a all is in disordered state, and the crystallite dimension among the described 16a is less than the crystallite dimension among the described 16b;
Described the second polysilicon layer 16 can play to the ion that injects buffering or barrier effect when carrying out ion implantation doping;
But described the second polysilicon layer 16 carries out or carries out respectively in different process cavity with the first polysilicon layer 14 original positions.
The present invention also provides a kind of manufacture method of semiconductor device, and Figure 11 is the flow chart of embodiment of the manufacture method of semiconductor device of the present invention.
As shown in figure 11,
Step S100 provides the Semiconductor substrate with gate insulator.
Step S110 forms the first polysilicon layer in described Semiconductor substrate.
Crystal grain in described the first polysilicon layer has column structure.
Step S120 is at the second polysilicon layer of described the first polysilicon layer formation crystal grain disorder distribution.
The method that forms described the second polysilicon layer is low-pressure chemical vapor deposition;
The reacting gas that forms described the second polysilicon layer is SiH
4, Si
2H
6And H
2
The technique that forms described the second polysilicon layer is carried out or is carried out respectively in different process cavity with the technique original position that forms the first polysilicon layer.
Step S130 carries out ion implantation doping to described the second polysilicon layer and the first polysilicon layer.
Because the crystal grain that has disorder distribution in described the second polysilicon layer, when being mixed, described the first polysilicon layer can play buffering or barrier effect to the doping ion, the ion that reduces or avoid injecting enters gate insulator or passes gate insulator, causes the electrical drift of the semiconductor device of formation.
Described the first polysilicon layer and the second polysilicon layer are annealed; By annealing make in described the second polysilicon layer crystal grain again crystallization be column structure, thereby so that the second polysilicon layer and the first polysilicon layer have roughly the same characteristic; This first polysilicon layer and the second polysilicon layer are all the grid layer that forms grid.
Step S140, graphical described the second polysilicon layer and the first polysilicon layer form grid.
By photoetching and graphical described the second polysilicon layer of etching technics and the first polysilicon layer, can form grid.
In other embodiments, can before graphical, described the second polysilicon layer and the first polysilicon layer not annealed yet, and after graphical, described the second polysilicon layer and the first polysilicon layer are annealed, repeat no more here.
Further, can form metal silicide at described grid, and the Semiconductor substrate of described grid both sides is being mixed, form source electrode and drain electrode, thereby form the metal oxide semiconductor transistor with grid, source electrode and drain electrode.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (17)
1. the manufacture method of a grid layer is characterized in that, comprising:
Semiconductor substrate with gate insulator is provided;
Form the first polysilicon layer with columnar grain in described Semiconductor substrate;
Form the second polysilicon layer of crystal grain disorder distribution at described the first polysilicon layer, the energy of ion when slowing down follow-up Implantation;
Described the second polysilicon layer and the first polysilicon layer are carried out ion implantation doping.
2. the manufacture method of grid layer as claimed in claim 1, it is characterized in that: the method that forms described the second polysilicon layer is low-pressure chemical vapor deposition.
3. the manufacture method of grid layer as claimed in claim 1, it is characterized in that: the reacting gas that forms described the second polysilicon layer is SiH
4, Si
2H
6And H
2
4. such as the manufacture method of the described grid layer of arbitrary claim in the claims 1 to 3, it is characterized in that: the technique that forms described the second polysilicon layer is carried out or is carried out respectively in different process cavity with the technique original position that forms the first polysilicon layer.
5. the manufacture method of grid layer as claimed in claim 1 is characterized in that: carry out forming amorphous silicon layer at described the second polysilicon layer before the ion implantation doping.
6. the manufacture method of grid layer as claimed in claim 1 is characterized in that: formed the 3rd polysilicon layer at described the second polysilicon layer before carrying out ion implantation doping.
7. the manufacture method of grid layer as claimed in claim 6 is characterized in that: the technique that forms described the 3rd polysilicon layer is identical with the technique that forms the first polysilicon layer.
8. such as the manufacture method of claim 6 or 7 described grid layers, it is characterized in that: the technique that forms described the 3rd polysilicon layer can original position be carried out or carry out respectively in different process cavity from the technique that forms described the second polysilicon layer.
9. the manufacture method of grid layer as claimed in claim 1 is characterized in that: described the second polysilicon layer is one or more layers.
10. the manufacture method of grid layer as claimed in claim 1, it is characterized in that: described the second polysilicon layer is multilayer, and along with the increase of the number of plies, crystallite dimension reduces.
11. the manufacture method of grid layer as claimed in claim 1 is characterized in that: after carrying out ion implantation doping, described the first polysilicon layer and the second polysilicon layer are annealed.
12. the manufacture method of a semiconductor device is characterized in that, comprising:
Semiconductor substrate with gate insulator is provided;
Form the first polysilicon layer with columnar grain in described Semiconductor substrate;
Form the second polysilicon layer of crystal grain disorder distribution at described the first polysilicon layer, the energy of ion when slowing down follow-up Implantation;
Described the second polysilicon layer and the first polysilicon layer are carried out ion implantation doping;
Graphical described the second polysilicon layer and the first polysilicon layer form grid.
13. the manufacture method of semiconductor device as claimed in claim 12 is characterized in that: the method that forms described the second polysilicon layer is low-pressure chemical vapor deposition.
14. the manufacture method of semiconductor device as claimed in claim 12 is characterized in that: the reacting gas that forms described the second polysilicon layer is SiH
4, Si
2H
6And H
2
15. the manufacture method of semiconductor device as claimed in claim 12 is characterized in that: the technique that forms described the second polysilicon layer is carried out or is carried out respectively in different process cavity with the technique original position that forms the first polysilicon layer.
16. the manufacture method of semiconductor device as claimed in claim 12 is characterized in that, the method further comprises: mix at described grid formation metal silicide with to the Semiconductor substrate of described grid both sides.
17. the manufacture method of semiconductor device as claimed in claim 12 is characterized in that, the method further comprises: before or after graphical described the second polysilicon layer and the first polysilicon layer, described the second polysilicon and the first polysilicon layer are annealed.
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| US8710620B2 (en) * | 2012-07-18 | 2014-04-29 | Infineon Technologies Ag | Method of manufacturing semiconductor devices using ion implantation |
| CN104217940A (en) * | 2014-09-24 | 2014-12-17 | 上海华力微电子有限公司 | Preparation method of polycrystalline silicon film |
| US10468486B2 (en) | 2017-10-30 | 2019-11-05 | Taiwan Semiconductor Manufacturing Company Ltd. | SOI substrate, semiconductor device and method for manufacturing the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6281559B1 (en) * | 1999-03-03 | 2001-08-28 | Advanced Micro Devices, Inc. | Gate stack structure for variable threshold voltage |
| CN1964066A (en) * | 2005-11-09 | 2007-05-16 | 台湾积体电路制造股份有限公司 | Gate electrode and mos transistor including gate and method of fabricating the same |
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| JP2002280550A (en) * | 2001-03-22 | 2002-09-27 | Mitsubishi Electric Corp | Method for manufacturing semiconductor device and semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6281559B1 (en) * | 1999-03-03 | 2001-08-28 | Advanced Micro Devices, Inc. | Gate stack structure for variable threshold voltage |
| CN1964066A (en) * | 2005-11-09 | 2007-05-16 | 台湾积体电路制造股份有限公司 | Gate electrode and mos transistor including gate and method of fabricating the same |
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