CN101335216A - 散热型封装结构及其制法 - Google Patents

散热型封装结构及其制法 Download PDF

Info

Publication number
CN101335216A
CN101335216A CNA2007101268012A CN200710126801A CN101335216A CN 101335216 A CN101335216 A CN 101335216A CN A2007101268012 A CNA2007101268012 A CN A2007101268012A CN 200710126801 A CN200710126801 A CN 200710126801A CN 101335216 A CN101335216 A CN 101335216A
Authority
CN
China
Prior art keywords
semiconductor chip
radiating part
heat
chip
active surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2007101268012A
Other languages
English (en)
Inventor
洪敏顺
蔡和易
黄建屏
萧承旭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to CNA2007101268012A priority Critical patent/CN101335216A/zh
Publication of CN101335216A publication Critical patent/CN101335216A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本发明公开了一种散热型封装结构及其制法,是将半导体芯片以其主动面接置并电性连接至芯片承载件,且于该芯片承载件上接置一具散热部及支撑部的散热件,以供半导体芯片容置于该散热部及支撑部所形成的容置空间中,其中该散热部形成有对应于半导体芯片的开孔,接着形成一用以包覆该半导体芯片及散热件的封装胶体,再薄化该封装胶体以移除该半导体芯片上的封装胶体,以使该半导体芯片非主动面及散热部顶面外露出该封装胶体,从而通过简化制程步骤及成本的方式制得散热型封装结构,同时避免现有技术中封装模压制程中压损芯片问题。

Description

散热型封装结构及其制法
技术领域
本发明涉及一种半导体封装结构及其制法,特别是涉及一种得以供半导体芯片有效散热的散热型半导体封装结构及其制作方法。
背景技术
传统半导体封装件为避免内部的半导体芯片受到外界水尘污染,因此必须在半导体芯片上覆盖一封装胶体以与外界隔绝,但是构成该封装胶体的封装树脂为一热传导性甚差的材料,其热导系数仅为0.8w/m°K,是以,半导体芯片运行时产生的热量无法有效通过该封装胶体传递到外界,导致热积存现象产生,使芯片性能及使用寿命备受考验。因此,为提高半导体封装件的散热效率,遂有于封装件中增设散热件的构想应运而生。
但是,若散热件亦为封装胶体所完全包覆时,半导体芯片产生的热量的散热途径仍须通过封装胶体,散热效果的提升仍然有限,甚而无法符合散热的需求,因而,为有效逸散芯片热量,其一方式是使散热件充分显露出该封装胶体,相对另一方式是使半导体芯片的表面直接外露出封装胶体,以供半导体芯片产生的热量得由外露于大气中的表面直接逸散。
请参阅图1A所示,美国专利第5,450,283号即公开了一种直接外露出半导体芯片表面的半导体封装件,该半导体封装件10是使半导体芯片11的顶面外露出用以包覆该半导体芯片11的封装胶体14。由于该半导体芯片11的顶面外露出封装胶体14而直接与大气接触,故该半导体芯片11产生的热量可直接逸散至大气中,其散热途径不需通经封装胶体14,藉以增加散热效率。
请配合参阅图1B,然而,该种半导体封装件10在制造上存在有若干的缺点。首先,该半导体芯片11黏接至基板12后,并置入封装模具的模腔15中以进行形成该封装胶体14的模压作业(Molding)时,须先将一胶片(Tape)13黏置于模腔15的顶壁上,从而使封装模具合模后该半导体芯片11的顶面得通过该胶片13顶抵至模腔15的顶壁,以避免该半导体芯片11的顶面上形成有溢胶(Flash);然而,若该半导体芯片11于基板12上的黏接高度控制不佳而导致该黏接有该半导体芯片11的基板12的整体高度过低,使该半导体芯片11的顶面未能通过该胶片13有效地顶抵至模腔15的顶壁,而于两者间形成有间隙时,用以形成该封装胶体14的封装化合物即会溢胶于该半导体芯片11的顶面上。一旦该半导体芯片11的顶面上形成有溢胶,除会影响该半导体芯片11的散热效率外,还会造成制成品的外观上的不良,故往往须予去胶(Deflash)的后处理;然而,是种去胶处理不但耗时,增加封装成本,且亦会导致制成品的受损。反之,若该黏接有该半导体芯片11的基板12的整体高度过高,导致该半导体芯片11通过该胶片13顶抵住模腔15的顶壁的力量过大,则往往会使质脆的该半导体芯片11因过度的压力而裂损(Crack)。
同时,封装模具的合模压力仍会经由该胶片13传递至该半导体芯片11,而造成该半导体芯片11的裂损,故令封装完成的制成品的良率无法有效提升,亦令其制造费用难以降低。
鉴于前述现有技术的缺陷,美国第6,458,626号(如图2A至图2C)、第6,444,498号(如图3)、以及第6,699,731号(如图4)专利(专利权人均同于本申请的申请人),揭露一种可将散热件直接黏置于半导体芯片上而不会产生压损芯片或溢胶问题,或可直接使半导体芯片表面外露的半导体封装件。
如图2A所示,该半导体封装件乃在散热件21欲外露于大气中的表面上形成一与封装胶体24间的接合性差的接口层25,再将该散热件21直接黏置于一接置在基板23的半导体芯片20上,继而进行封装模压制程,以使封装胶体24完全包覆该散热件21及半导体芯片20,并使封装胶体24覆盖于散热件21的接口层25上(如图2A所示),如此,封装模压制程所使用的模具的模腔的深度乃大于半导体芯片20与散热件21的厚度和,故在模具合模后,模具不会触及散热件21而使半导体芯片20无受压导致裂损的问题;接着,进行切割作业(如图2B所示),并将散热件21上方的封装胶体24去除,其中当形成于散热件21上的接口层25(例如为镀金层)与散热件21间的黏结性大于其与封装胶体24间的黏结性时,将封装胶体24剥除后,该接口层25仍存留于散热件21上,但因接口层25与封装胶体24间的黏结性差,封装胶体24不致残留于接口层25上(如图2C所示),故无溢胶的问题。相对地,当形成于散热件21上的接口层25(例如为聚亚酰胺树脂制成的胶黏片)与散热件21间的黏结性小于其与封装胶体24间的黏结性时,将封装胶体24剥除后,该接口层25会黏附于封装胶体24上而随之去除(如图3所示),故该散热件21上亦不会形成溢胶。
亦或如图4所示,该种半导体封装件是于半导体芯片31上形成一附有接口层333的金属材料的覆接片33,以通过形成该封装胶体34的封装化合物的热膨胀系数不同于接口层333的关系,使黏结性差的接口层333与该半导体芯片31及形成于该半导体芯片31周围的封装胶体34间的接口产生脱层,如此即可轻易地将该接口层333、覆接片33、及形成于该覆接片33上的封装化合物340自该半导体芯片31表面及形成于该半导体芯片31周围的封装胶体34的表面上轻易地撕除,使该半导体芯片31表面能外露出封装胶体34,以让该半导体芯片31产生的热量得由外露于大气中的表面直接逸散。且在模压的过程中,由于该半导体芯片31的表面是完全由接口层333所覆接,因此不会于半导体芯片31表面残留任何封装化合物,故毋须进行任何去除溢胶的后处理,而可降低封装成本并确保制成的半导体封装件外观的良好。
但是于前述的半导体封装件制程过于繁琐且成本高,不利半导体封装业界实际操作应用。
因此,如何提供一种于封装模压制程时不致压伤半导体芯片,同时制程简便且成本较低的散热型封装结构及制法,实为目前亟待解决的问题。
发明内容
鉴于以上所述现有技术的缺点,本发明的一目的在于提供一种散热型封装结构及其制法,得以有效逸散半导体芯片运行时产生的热量。
本发明的再一目的在于提供一种散热型封装结构及其制法,不致于封装模压过程中压伤半导体芯片。
本发明的另一目的在于提供一种散热型封装结构及其制法,得以降低制程成本及简化制程步骤。
为达到上述及其它目的,本发明的散热型封装结构制法,包括:提供至少一具相对主动面及非主动面的半导体芯片,以将该半导体芯片主动面通过覆晶方式接置并电性连接于芯片承载件上;于该芯片承载件上接置一散热件,该散热件具有一散热部、一自该散热部向下延伸的支撑部、以及一形成于该散热部的开孔,以供该散热件通过该支撑部而架撑于该芯片承载件上,同时使该半导体芯片容置于该散热部与该支撑部所构成的容置空间中,并使该散热部的开孔对应于该半导体芯片非主动面的上方;进行封装模压作业,以于该芯片承载件上形成一包覆该半导体芯片及散热件的封装胶体;以及薄化该半导体芯片上方的封装胶体,藉以外露出该半导体芯片非主动面及散热部顶面。该芯片承载件可采用基板或导线架型式。
通过前述的制法,本发明还提供一种散热型封装结构,包括:芯片承载件;半导体芯片,具相对的主动面及非主动面,该半导体芯片是以其主动面接置并电性连接至该芯片承载件上;散热件,具有一散热部、一自该散热部向下延伸的支撑部、以及一形成于该散热部的开孔,以供该散热件通过该支撑部而架撑于该芯片承载件上,同时使该半导体芯片容置于该散热部与该支撑部所构成的容置空间中,且该散热部的顶面高度与该半导体芯片非主动面高度相等;以及封装胶体,形成于该芯片承载件上,用以包覆该半导体芯片及散热件,且使该半导体芯片非主动面及散热部顶面外露出该封装胶体。
因此,本发明的散热型封装结构及其制法主要是将半导体芯片以覆晶方式接着并电性连接至芯片承载件,并于该芯片承载件上接置一具散热部及自该散热部向下延伸的支撑部的散热件,其中该散热部形成有对应于半导体芯片的开孔,以使该半导体芯片容置于该散热部与该支撑部所构成的容置空间中,且该散热部的开孔对应于该半导体芯片非主动面的上方,接着形成一用以包覆该半导体芯片及该散热件的封装胶体,并薄化该封装胶体,从而使该半导体芯片非主动面及散热部顶面外露出该封装胶体,如此即可通过低制程成本及简易制程方式制得外露出半导体芯片的散热型封装结构,同时本发明制程中是使封装胶体先覆盖半导体芯片及散热件,再薄化封装胶体以外露出半导体芯片及散热件,避免于封装模压过程中压伤半导体芯片。
附图说明
图1A及图1B为美国专利第5,450,283号所公开的半导体封装件剖面示意图;
图2A至图2C为美国专利第6,458,626号所公开的半导体封装件剖面示意图;
图3为美国专利第6,444,498号所公开的半导体封装件剖面示意图;
图4为美国专利第6,699,731号所公开的半导体封装件剖面示意图;
图5A至图5E为本发明的散热型封装结构及其制法第一实施例的示意图;以及
图6为本发明的散热型封装结构第二实施例的示意图。
元件符号说明
10   半导体封装件    11   半导体芯片
12   基板            13   胶片
14   封装胶体        15   模腔
20   半导体芯片      21   散热件
23   基板            24   封装胶体
25   接口层          31   半导体芯片
333  界面层          33   覆接片
34   封装胶体        41   半导体芯片
410  导电凸块        411  主动面
412  非主动面        42   芯片承载件
44   封装胶体        45   散热件
450  开孔            451  散热部
452  支撑部          51   半导体芯片
54   封装胶体        551  散热部
56   保护层
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式,本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点与功效。
第一实施例
请参阅图5A至图5E,为本发明的散热型封装结构及其制法第一实施例的示意图。
如图5A所示,提供至少一具相对主动面411及非主动面412的半导体芯片41,以将该半导体芯片41接置并电性连接于芯片承载件42上。该芯片承载板42是例如为球栅阵列(BGA)基板或平面栅格阵列(LGA)基板,而该半导体芯片41是例如为覆晶式半导体芯片,且该覆晶式半导体芯片通过多个导电凸块410以将其主动面电性连接至该芯片承载件42。
如图5B所示,于该芯片承载件上接置一散热件45,该散热件45具有一散热部451、一自该散热部451向下延伸的支撑部452、以及一形成于该散热部451的开孔450,以供该第一散热件45通过该支撑部452而架撑于该芯片承载件42上,同时使该半导体芯片41容置于该散热部451与该支撑部452所构成的容置空间中,并使该半导体芯片41对应于该散热部451的开孔450位置。该散热部开孔450的尺寸大于半导体芯片41平面尺寸,且该散热部451高度略高于该半导体芯片非主动面412高度。
如图5C所示,进行封装模压作业,将该结合有半导体芯片41、散热件45及芯片承载件42的结构置入封装模具的模腔中(未图示),以填入封装树脂,以后即可移除该封装模具,从而于该芯片承载件42上形成一用以包覆该半导体芯片41及散热件45的封装胶体44,其中由于该散热部451高度略高于该半导体芯片非主动面412高度,因而可避免现有技术中封装模具直接抵压于半导体芯片上而发生裂损问题。
如图5D及图5E所示,利用如研磨等薄化作业,以移除覆盖于该半导体芯片非主动面412上方的封装胶体44及散热件的部分散热部451,藉以使该半导体芯片非主动面412及散热件45的散热部451顶面外露出该封装胶体44,进而提供半导体芯片41良好散热途径。
通过前述制法,本发明还提供一种散热型封装结构,包括有:芯片承载件42;半导体芯片41,具相对的主动面411及非主动面412,该半导体芯片41是以其主动面411接置并电性连接至该芯片承载件42上;散热件45,具有一散热部451、一自该散热部451向下延伸的支撑部452、以及一形成于该散热部451的开孔450,以供该散热件45通过该支撑部452而架撑于该芯片承载件42上,同时使该半导体芯片41容置于该散热部451与该支撑部452所构成的容置空间中,且该散热部451顶面高度与该半导体芯片41非主动面高度相等;以及封装胶体44,形成于该芯片承载件42上,用以包覆该半导体芯片41及散热件45,且使该半导体芯片41非主动面及散热部451顶面外露出该封装胶体44,如此即可使该半导体芯片41有效逸散其运行时所产生的热量至外界。
第二实施例
请参阅图6,为本发明的散热型封装结构第二实施例的示意图。如图所示,本实施例的散热型封装结构与前述实施例大致相同,其主要差异在移除位于半导体芯片51上的封装胶体后,复于外露出该封装胶体54的散热部551顶面上涂布一如油墨(ink)的保护层56,以防止该散热部551的氧化。
因此,本发明的散热型封装结构及其制法主要是将半导体芯片以覆晶方式接着并电性连接至芯片承载件,并于该芯片承载件上接置一具散热部及自该散热部向下延伸的支撑部的散热件,其中该散热部形成有对应于半导体芯片的开孔,以使该半导体芯片容置于该散热部与该支撑部所构成的容置空间中,且该散热部的开孔对应于该半导体芯片非主动面的上方,接着形成一用以包覆该半导体芯片及该散热件的封装胶体,并薄化该封装胶体,从而使该半导体芯片非主动面及散热部顶面外露出该封装胶体,如此即可通过低制程成本及简易制程方式制得外露出半导体芯片的散热型封装结构,同时本发明制程中是使封装胶体先覆盖半导体芯片及散热件,再薄化封装胶体以外露出半导体芯片及散热件,避免于封装模压过程中压伤半导体芯片。
上述实施例仅例示性说明本发明的原理及其功效,而非用于限制本发明。尤其应特别注意的是,该芯片承载件的选择,以及芯片与芯片承载件的电性连接方式的采用,任何本领域技术人员均可在不违背本发明的精神及范畴下,对上述实施例进行修饰与改变。因此,本发明的权利保护范围,应以权利要求书的范围为依据。

Claims (14)

1.一种散热型封装结构制法,包括:
提供至少一具相对主动面及非主动面的半导体芯片,以将该半导体芯片主动面通过覆晶方式接置并电性连接于芯片承载件上;
于该芯片承载件上接置一散热件,该散热件具有一散热部、一自该散热部向下延伸的支撑部、以及一形成于该散热部的开孔,以供该散热件通过该支撑部而架撑于该芯片承载件上,同时使该半导体芯片容置于该散热部与该支撑部所构成的容置空间中,并使该散热部的开孔对应于该半导体芯片非主动面的上方;
进行封装模压作业,以于该芯片承载件上形成一包覆该半导体芯片及散热件的封装胶体;以及
薄化该半导体芯片上方的封装胶体,藉以外露出该半导体芯片非主动面及散热部顶面。
2.根据权利要求1所述的散热型封装结构制法,其中,该芯片承载件为基板及导线架的其中一者。
3.根据权利要求1所述的散热型封装结构制法,其中,该半导体芯片是通过多个导电凸块以将其主动面电性连接至该芯片承载件。
4.根据权利要求1所述的散热型封装结构制法,其中,该散热部开孔的尺寸大于半导体芯片平面尺寸。
5.根据权利要求1所述的散热型封装结构制法,其中,该薄化作业是利用研磨技术移除覆盖于该半导体芯片非主动面上方的封装胶体。
6.根据权利要求5所述的散热型封装结构制法,其中,该薄化作业中亦同时研磨掉部分散热部。
7.根据权利要求1所述的散热型封装结构制法,复包括于外露出该封装胶体的散热部顶面涂布一保护层。
8.根据权利要求7所述的散热型封装结构制法,其中,该保护层为油墨。
9.一种散热型封装结构,包括:
芯片承载件;
半导体芯片,具相对的主动面及非主动面,该半导体芯片是以其主动面接置并电性连接至该芯片承载件上;
散热件,具有一散热部、一自该散热部向下延伸的支撑部、以及一形成于该散热部的开孔,以供该散热件通过该支撑部而架撑于该芯片承载件上,同时使该半导体芯片容置于该散热部与该支撑部所构成的容置空间中,且该散热部的顶面高度与该半导体芯片非主动面高度相等;以及
封装胶体,形成于该芯片承载件上,用以包覆该半导体芯片及散热件,且使该半导体芯片非主动面及散热部顶面外露出该封装胶体。
10.根据权利要求9所述的散热型封装结构,其中,该芯片承载件为基板及导线架的其中一者。
11.根据权利要求9所述的散热型封装结构,其中,该半导体芯片是通过多个导电凸块以将其主动面电性连接至该芯片承载件。
12.根据权利要求9所述的散热型封装结构,其中,该散热部开孔的尺寸大于半导体芯片平面尺寸。
13.根据权利要求9所述的散热型封装结构,复包括有一保护层,形成于外露出该封装胶体的散热部顶面。
14.根据权利要求13所述的散热型封装结构,其中,该保护层为油墨。
CNA2007101268012A 2007-06-27 2007-06-27 散热型封装结构及其制法 Pending CN101335216A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNA2007101268012A CN101335216A (zh) 2007-06-27 2007-06-27 散热型封装结构及其制法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNA2007101268012A CN101335216A (zh) 2007-06-27 2007-06-27 散热型封装结构及其制法

Publications (1)

Publication Number Publication Date
CN101335216A true CN101335216A (zh) 2008-12-31

Family

ID=40197694

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2007101268012A Pending CN101335216A (zh) 2007-06-27 2007-06-27 散热型封装结构及其制法

Country Status (1)

Country Link
CN (1) CN101335216A (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106409747A (zh) * 2016-11-15 2017-02-15 广东美的制冷设备有限公司 智能功率模块及其制造方法
CN111933604A (zh) * 2020-07-08 2020-11-13 南京晟芯半导体有限公司 一种提高半导体场效应晶体管芯片短路能力的结构及方法
CN112185903A (zh) * 2019-07-03 2021-01-05 矽品精密工业股份有限公司 电子封装件及其制法
WO2022067589A1 (zh) * 2020-09-29 2022-04-07 华为技术有限公司 一种芯片封装和电子设备

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106409747A (zh) * 2016-11-15 2017-02-15 广东美的制冷设备有限公司 智能功率模块及其制造方法
CN112185903A (zh) * 2019-07-03 2021-01-05 矽品精密工业股份有限公司 电子封装件及其制法
CN111933604A (zh) * 2020-07-08 2020-11-13 南京晟芯半导体有限公司 一种提高半导体场效应晶体管芯片短路能力的结构及方法
CN111933604B (zh) * 2020-07-08 2021-07-27 南京晟芯半导体有限公司 一种提高半导体场效应晶体管芯片短路能力的结构及方法
WO2022067589A1 (zh) * 2020-09-29 2022-04-07 华为技术有限公司 一种芯片封装和电子设备

Similar Documents

Publication Publication Date Title
TW498516B (en) Manufacturing method for semiconductor package with heat sink
CN101101880A (zh) 散热型封装结构及其制法
US8013436B2 (en) Heat dissipation package structure and method for fabricating the same
TWI455215B (zh) 半導體封裝件及其之製造方法
US20080284047A1 (en) Chip Package with Stiffener Ring
US20070155049A1 (en) Method for Manufacturing Chip Package Structures
TW200531191A (en) Wafer level semiconductor package with build-up layer and process for fabricating the same
CN101425469A (zh) 使用大尺寸面板的半导体构装方法
US7157311B2 (en) Substrate sheet material for a semiconductor device and a manufacturing method thereof, a molding method using a substrate sheet material, a manufacturing method of semiconductor devices
US7858446B2 (en) Sensor-type semiconductor package and fabrication method thereof
US8779573B2 (en) Semiconductor package having a silicon reinforcing member embedded in resin
CN101101881A (zh) 散热型封装结构及其制法
CN101335216A (zh) 散热型封装结构及其制法
CN1855450A (zh) 高散热性的半导体封装件及其制法
TW201448163A (zh) 半導體封裝件及其製法
US20060292741A1 (en) Heat-dissipating semiconductor package and fabrication method thereof
CN102332408B (zh) 芯片尺寸封装件及其制法
CN1172369C (zh) 具散热片的半导体封装件
CN100411121C (zh) 散热型封装结构及其制法
CN101221909A (zh) 散热型封装件的制法及其所应用的散热结构
CN101110370A (zh) 散热型封装结构及其制法
CN100446200C (zh) 散热型封装结构及其制法
JP5383464B2 (ja) 半導体装置及びその製造方法
TWI440146B (zh) 避免模封溢膠污染至內置散熱片之半導體封裝構造
JP2004063680A (ja) チップ上基板のチップアレイ式ボールグリッドアレイパッケージの製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Open date: 20081231