CN101326636A - Device and method for assembling a top and bottom exposed packaged semiconductor - Google Patents

Device and method for assembling a top and bottom exposed packaged semiconductor Download PDF

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Publication number
CN101326636A
CN101326636A CNA2006800460367A CN200680046036A CN101326636A CN 101326636 A CN101326636 A CN 101326636A CN A2006800460367 A CNA2006800460367 A CN A2006800460367A CN 200680046036 A CN200680046036 A CN 200680046036A CN 101326636 A CN101326636 A CN 101326636A
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CN
China
Prior art keywords
lead frame
lead
semiconductor device
wafer
solderable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2006800460367A
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Chinese (zh)
Inventor
张德忠
玛丽亚·克里斯蒂娜·B·埃斯塔西奥
张叔林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
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Fairchild Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor Corp filed Critical Fairchild Semiconductor Corp
Publication of CN101326636A publication Critical patent/CN101326636A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

A packaged semiconductor device includes a two piece lead assembly having vertically separated top and bottom lead frames. A semiconductor die is between the two lead frames and makes electrical and thermal contact to the two lead frames. The lower lead frame is generally flat while the upper lead frame has a flat top surface and downward extensions that fell on two opposite sides of the lower lead frame and that end in flanges that have bottom surfaces that are coplanar with the bottom surface of the bottom lead frame. When the assembly is molded, the top surface of the top lead frame and the bottom surfaces of the flanges and the bottom lead frame are exposed to allow electrical contact to the semiconductor die and to provide thermal conductive paths to dissipate heat developed in the semiconductor die.

Description

Be used to assemble the apparatus and method of the encapsulated semiconductor that top and bottom exposes
Technical field
The present invention relates to a kind of packaged semiconductor devices and a kind of method of making described packaged semiconductor devices.
Background technology
The power semiconductor arrangement of encapsulation need conduct the encapsulation of heat away from semiconductor device usually efficiently.The known encapsulated semiconductor that makes is molded with the heat that fin or pressing plate are produced with the dissipation semiconductor device.Yet placing the prior art pressing plate exactly and do not make described pressing plate be tilted in the manufacturing of these encapsulation may be a problem.
Another problem that is associated with the manufacturing molded packaged semiconductors is the uniformly final package thickness of holdout device.For instance, in some prior-art devices, the stacks as high with device of top exposed drain pressing plate depends on the height that is welded to connect part between pressing plate and wafer (die) bonding frame.Compare with the screen printing welding procedure, amount of solder can not as one man be divided the thickness evenness that is equipped with between the holdout device.
Another problem that is associated with the manufacturing molded packaged semiconductor devices is to control mechanical stress during molding process.For instance, in the device with top exposed drain pressing plate, vertical compression stress will concentrate on the drain clip, and further transfer to along vertical axis and be welded to connect part, and shift downwards along semiconductor wafer.Formed stress may cause the problem of both aspects of 26S Proteasome Structure and Function performance of device when molded.Therefore, need a kind of making that the compression stress of semiconductor wafer is reduced to minimum device.
Summary of the invention
The present invention comprises a kind of method of packaged semiconductor devices in its a kind of form, described method comprises: first lead frame is provided, and it has first and second lead-in wires that electricity is isolated; The semiconductor device that will have the connector of solderable is attached to described first lead frame; Second lead frame is placed on described semiconductor device and described first lead frame, described second lead frame has the extension leg, described extension leg is positioned on the opposite side of described second lead frame, and extend downwards towards described first lead frame from the top of described second lead frame, and in two flanges parallel with the top of described second lead frame, stop, make the bottom of described flange and the bottom coplane of described first lead frame.Described method comprises: the downside at the top of described second lead frame is welded to wafer; Molded with encapsulating material on described first and second lead frames and described wafer, make the top of second lead frame, the bottom of flange and the bottom of first lead frame keep exposing simultaneously.
The present invention also comprises a kind of packaged semiconductor devices in its a kind of form, and it has: have first and second first lead frames that go between that electricity is isolated; Semiconductor device with connector of solderable, it is attached to described first lead frame; And second lead frame, its be welded to described semiconductor device and be positioned at described semiconductor device and described first lead frame on, described second lead frame has the extension leg, described extension leg is positioned on the opposite side of described second lead frame, and extend downwards towards described first lead frame from the top of described second lead frame, and in two flanges parallel with the top of described second lead frame, stop, make the bottom of described flange and the bottom coplane of described first lead frame.
Advantage of the present invention is that upper frame has top exposed drain pressing plate so that heat is removed from device, and comprises the leg extension that drain lead is carried to the plane identical with source electrode and grid lead.
Description of drawings
In conjunction with the drawings with reference to the following description content of each embodiment of the present invention, with the mode of understanding and understanding above-mentioned and further feature and advantage of the present invention better and realize described feature and advantage, in the accompanying drawings:
Figure 1A, Figure 1B, Fig. 1 C, Fig. 1 D, Fig. 1 E and Fig. 1 F are the cross-sectional views that the line 1A-F along among Fig. 4 with the assembly of the series of steps assembling in the manufacture method that is used to form packaged semiconductor devices according to the present invention intercepts to 1A-F;
Fig. 2 is the isometric view of overlooking according to two pieces type lead frame sub-assembly of the present invention;
Fig. 3 is the isometric view of overlooking of the encapsulated semiconductor shown in Fig. 1 F;
Fig. 4 is the upward view of the packaged semiconductor devices shown in Fig. 1 F; And
Fig. 5 is the cross-sectional view of the modification of one in the device shown in Fig. 1 C.
To understand, for purpose clearly and be regarded as suitable part, repeat reference numerals is with the indication character pair in the drawings.And, the relative size of each object in graphic in some cases distortion more clearly to show the present invention.
Embodiment
To Fig. 1 F, show a series of manufacturing steps that are associated with the method for generation packaged semiconductor devices according to the present invention referring to Figure 1A.In one embodiment, bottom lead frame 10 be with 12 laminations, such as in Figure 1A displaying.Although Figure 1A only shows single individual device bar in Fig. 1 F, the form that manufacturing process can bar or make described device with the form of matrix.Following lead frame 10 can be configured to copper or the similar electric conducting material of one deck through rolling or electro-deposition and plating.Following lead frame 10 comprises source lead 14 and the grid lead 16 that electricity is isolated.
Such as in Figure 1B displaying, the flip-chip die 20 (it can be a power MOSFET) with solder ball is installed in down on the lead frame 10, and is welded to connect part 22 and 24 through reflow to form respectively between source lead 14 and gate lead-in wire 16.Can use metal under the projection (under bump metal, UMB) or use the copper binding post to form solder contacts.
Now referring to Fig. 1 C, on the back side that solder(ing) paste 22 is printed onto or is assigned to wafer 20 and will go up after lead frame 30 is placed on bottom lead frame 10 and the wafer 20, top lead frame 30 is welded on the wafer 20 by second reflow operation.In one embodiment, top lead frame 30 is based on copper.The top lead frame 30 of drain electrode that can be connected to wafer 20 through perpendicular positioning so that contact with the exposed leads 32 of finishing device on the opposite side of bottom lead frame 10 (in displaying) as Fig. 4 with 12.As mentioned above, each can form independent bar or matrix bottom lead frame 10 and top lead frame 30, and uses guide hole and alignment pin to assemble, and aims at top lead frame to make bottom lead frame exactly.The 6th, 762, No. 067 United States Patent (USP) is described this program.
Fig. 1 D is illustrated in the device bar of being showed among Fig. 1 C (or matrix) is carried out molded operation treatment state afterwards.Before injection molding compound 40, placement is used for the auxiliary molded film 42 of film on the top 44 of top lead frame 30.Perhaps, can be before engage base lead frame 10 and top lead frame 30, with band such as with 12 tops 44 that are applied to top lead frame 30.After film 42 is in suitable position, sub-assembly is placed in the molding press 46 with top die sleeve 46a and bottom die sleeve 46b, and mold compound 40 is injected in the molding press.Described mold compound can be non-conductive polymer encapsulation material, for example epoxy resin.
Rectangle 48 indications among Fig. 1 E will be cut sub-assembly wherein, and Fig. 1 F shows the device of finishing through cutting 50.
Fig. 2 be show top lead frame 30 and bottom lead frame 10 in the finishing device 50 relative position overlook isometric view.The top of top lead frame 30 or pressing plate 44 are not covered by the moulding material in the finishing device 50 40, and are fin therefore, and it allows the extra heat dissipation sheet directly to be installed on the top 44.Top lead frame 30 also comprises the extension leg 54 on the opposite side that is positioned at top lead frame 30, and described extension leg extends downwardly into two flanges 56 parallel with top 44 from the top 44 that exposes.Extending leg 54 provides vertical jumping-up (vertical upset) from bottom lead frame 10, and the height of definite finishing device 50.Connecting rod 58 is to be used for making before the operation top and bottom lead frame remain on the remainder (reminent) of connecting rod of the appropriate position of its corresponding bar or matrix assemblies cutting of above describing with respect to Fig. 1 E.
Fig. 3 overlooks isometric view, and Fig. 4 is the vertical view of finishing device 50 of showing the expose portion of top lead frame 30 and bottom lead frame 10.
Fig. 5 is cross section Figure 60 of one in the device of being showed among Fig. 1 C that revises according to another embodiment of the present invention.In Fig. 5, the top lead frame 30 of being showed among the previous figure is replaced by modified top lead frame 62.Top lead frame 62 each place, crooked inside in top lead frame 62 has otch 64, and otch 64 allows outer corner 66 more sharp-pointed than the turning to outer bend of top lead frame 30.Therefore, the area of the exposed surface of the top lead frame 62 on the finishing device still keeps identical device external dimensions and holds identical wafer size simultaneously greater than the area of the exposed surface of top lead frame 30.
Top lead frame 30,62 is supported on the bottom and means the height decision of packaging height by top lead frame 30,62 on 12.In addition; in molded operating period; as indicated by the arrow among Fig. 5 68; molding press applies vertical compression stress to device; with prevent moulding material with 12 and the lower surface 32 of bottom lead frame 10 and top lead frame 30 between flow, and prevent that moulding material is mobile between the top surface 44 of film 42 and top lead frame 30. Top lead frame 30,62 provides required support to absorb the major part of this stress, makes wafer 20 without undergoing the vertical stress that may damage wafer 20 during molding process, and has also in fact eliminated any reducing of molded operating period device height.
Though described the present invention with reference to specific embodiment, be understood by those skilled in the art that, can make various changes, and equipollent can replace element of the present invention without departing from the scope of the invention.In addition, can make many modifications so that particular condition or material are suitable for teaching of the present invention without departing from the scope of the invention.
Therefore, wish to the invention is not restricted to be disclosed as the specific embodiment of carrying out the desired optimal mode of the present invention, but wish that the present invention will comprise all embodiment of the scope and spirit that belong to appended claims.

Claims (22)

1. the method for a packaged semiconductor devices, it may further comprise the steps:
(a) provide first lead frame, it has first and second lead-in wires that electricity is isolated;
(b) semiconductor device that will have a connector of solderable is attached to described first lead frame;
(c) second lead frame is placed on described wafer and described first lead frame, described second lead frame has the extension leg, described extension leg is positioned on the opposite side of described second lead frame, and extend downwards towards described first lead frame from the top of described second lead frame, and in two flanges parallel with the described top of described second lead frame, stop, make the bottom of described flange and the bottom coplane of described first lead frame;
(d) downside with the described top of described second lead frame is welded to described semiconductor device; And
(e) molded with encapsulating material on described first and second lead frames and described wafer, make the described bottom of the described top of described second lead frame, described flange and the described bottom of described first lead frame keep exposing simultaneously.
2. method according to claim 1, wherein said first lead frame comprises copper.
3. method according to claim 1, the connector of wherein said solderable comprises a plurality of conductive projections.
4. method according to claim 3, wherein said conductive projection comprises the material of solderable.
5. method according to claim 1 wherein was applied to described semiconductor device with solder(ing) paste before placing described second lead frame, and carried out the reflow operation after described second lead frame is in suitable position.
6. method according to claim 1, wherein said second lead frame comprises copper.
7. method according to claim 1, wherein said second lead frame is determined the overall height of described individual package device.
8. method according to claim 1, wherein molded step comprise and apply the non-conductive polymer encapsulating material.
9. method according to claim 8, wherein said non-conductive polymer encapsulating material is an epoxy resin.
10. method according to claim 1 wherein forms groove in the position that second lead frame described in described second lead frame will form interior curve.
11. a packaged semiconductor devices, it comprises:
(a) first lead frame, it has first and second lead-in wires that electricity is isolated;
(b) have the semiconductor device of the connector of solderable, it is attached to described first lead frame; And
(c) second lead frame, it is welded to described wafer, and be positioned on described semiconductor device and described first lead frame, described second lead frame has the extension leg, described extension leg is positioned on the opposite side of described second lead frame, and extend downwards towards described first lead frame from the top of described second lead frame, and in two flanges parallel, stop, make the bottom of described flange and the bottom coplane of described first lead frame with the described top of described second lead frame.
12. device according to claim 11, the part of wherein said wafer and described first and second lead frames contacts with mold compound.
13. device according to claim 11, the connector of wherein said solderable comprises a plurality of conductive projections.
14. device according to claim 13, wherein said conductive projection comprises the material of solderable.
15. device according to claim 11, wherein said second lead frame comprises copper.
16. device according to claim 11, wherein said second lead frame is determined the overall height of described individual package device.
17. device according to claim 12, wherein said mold compound comprises the non-conductive polymer encapsulating material.
18. device according to claim 17, wherein said non-conductive polymer encapsulating material is an epoxy resin.
19. device according to claim 11, the interior curve of wherein said second lead frame contains fluted.
20. a packaged semiconductor devices, it comprises:
(a) power MOSFET semiconductor device, it has drain terminal on a surface, and has source electrode and gate terminal on the apparent surface;
(b) lead frame under, source electrode and gate pad that its electricity with exposure is isolated;
(c) go up lead frame, it has upper surface and leg, and described leg extends towards described lead frame down from fin, and stops in being parallel to the flange of described upper surface, the bottom of described flange and the described bottom coplane of lead frame down; And
(d) encapsulating material, it is used to protect wafer, and is configured so that the described described upper surface of lead frame and the bottom-exposed of lower surface and described first lead frame of going up.
21. packaged semiconductor devices according to claim 20, the wherein said described drain terminal of going up lead frame and described semiconductor device electrically contacts and thermo-contact.
22. packaged semiconductor devices according to claim 20, wherein said leg is placed on the opposite side of described upper and lower lead frame.
CNA2006800460367A 2005-12-09 2006-12-11 Device and method for assembling a top and bottom exposed packaged semiconductor Pending CN101326636A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US74914505P 2005-12-09 2005-12-09
US60/749,145 2005-12-09
US11/608,626 2006-12-08

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CN101326636A true CN101326636A (en) 2008-12-17

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102714201A (en) * 2010-01-19 2012-10-03 维西埃-硅化物公司 Semiconductor package and method
CN102956509A (en) * 2011-08-31 2013-03-06 飞思卡尔半导体公司 Power device and method for packaging same
TWI411098B (en) * 2011-01-18 2013-10-01 Delta Electronics Inc Power semiconductor package structure and manufacturing method thereof
CN104956782A (en) * 2013-01-09 2015-09-30 德克萨斯仪器股份有限公司 Integrated circuit module
CN105428330A (en) * 2015-10-30 2016-03-23 杰群电子科技（东莞）有限公司 Semiconductor device and manufacturing method thereof
CN107481990A (en) * 2017-09-26 2017-12-15 深圳赛意法微电子有限公司 Lead frame, semiconductor devices and its packaging technology
US9957630B2 (en) 2013-07-19 2018-05-01 Kabushiki Kaisha Toshiba Pattern transfer mold and pattern formation method
CN109075151A (en) * 2016-04-26 2018-12-21 凌力尔特科技有限责任公司 The lead frame that mechanical engagement and electrically and thermally for component package circuit conduct

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102714201A (en) * 2010-01-19 2012-10-03 维西埃-硅化物公司 Semiconductor package and method
CN102714201B (en) * 2010-01-19 2015-12-09 维西埃-硅化物公司 Semiconductor packages and method
TWI411098B (en) * 2011-01-18 2013-10-01 Delta Electronics Inc Power semiconductor package structure and manufacturing method thereof
CN102956509A (en) * 2011-08-31 2013-03-06 飞思卡尔半导体公司 Power device and method for packaging same
CN104956782A (en) * 2013-01-09 2015-09-30 德克萨斯仪器股份有限公司 Integrated circuit module
CN104956782B (en) * 2013-01-09 2018-05-11 德克萨斯仪器股份有限公司 Integrated circuit modules
US9957630B2 (en) 2013-07-19 2018-05-01 Kabushiki Kaisha Toshiba Pattern transfer mold and pattern formation method
CN105428330A (en) * 2015-10-30 2016-03-23 杰群电子科技（东莞）有限公司 Semiconductor device and manufacturing method thereof
CN109075151A (en) * 2016-04-26 2018-12-21 凌力尔特科技有限责任公司 The lead frame that mechanical engagement and electrically and thermally for component package circuit conduct
CN107481990A (en) * 2017-09-26 2017-12-15 深圳赛意法微电子有限公司 Lead frame, semiconductor devices and its packaging technology

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Open date: 20081217