CN101320730B - Semiconductor chip with built-in test circuit - Google Patents
Semiconductor chip with built-in test circuit Download PDFInfo
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- CN101320730B CN101320730B CN2008101340363A CN200810134036A CN101320730B CN 101320730 B CN101320730 B CN 101320730B CN 2008101340363 A CN2008101340363 A CN 2008101340363A CN 200810134036 A CN200810134036 A CN 200810134036A CN 101320730 B CN101320730 B CN 101320730B
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Abstract
The invention provides a semiconductor chip of built-in testing circuit, comprising: an active circuit region; a sealing ring structure surrounding the active circuit region; a first circuit structure which is manufactured in a first corner of the semiconductor chip located at external side of the sealing ring structure, formed into an electric connection configuration with the sealing ring structure and provided with a first connection cushion; and a second circuit structure which is manufactured in a second corner of the semiconductor chip located at external side of the sealing ring structure, formed into an electric connection configuration with the sealing ring structure and provided with a second connection cushion.
Description
The application be that August 5, application number in 2005 are 200510089740.8 the applying date, denomination of invention divides an application for the patent application of " semiconductor chip of built-in detecting circuit ".
Technical field
The present invention relates to the reliability test field of semiconductor integrated circuit chip, relate in particular to the test circuit structure of building the chip corner place in a kind of in, can be used to assess the integrality of chip structure.
Background technology
Along with the microminiaturization as semiconductor elements such as transistors, the usefulness of semiconductor integrated circuit and density also significantly promote.When the manufacture level of semiconductor integrated circuit reaches time micron or how during the industrial grade of rice, resistance-capacitance postpones promptly to become the bottleneck whether usefulness of circuit can further promote.Electric capacity by line resistance that reduces binding circuit in the metal or reduction dielectric layer can make the resistance-capacitance delay issue improve.Wherein, aspect the line resistance of binding circuit, the chip manufacturing dealer has adopted the copper metal on technology, replace the higher aluminum metal of resistivity, and aspect the electric capacity that reduces dielectric layer, then look for the more dielectric material of low-k energetically in reducing metal.
Yet, compare with employed silicon oxide dielectric material of past, for example fluorine silex glass or undoped silicon glass etc., the mechanical strength of the dielectric material of the most low-k that adopts is still disliked deficiency at present.In addition, another problem of the dielectric material of low-k is that the cohesive force between the interface is poor, no matter be the interface between the dielectric material of two-layer identical low-k, or at the dielectric material of one deck low-k and the interface between another layer dielectric layer of different nature.When carrying out follow-up processing of wafers step, for example wafer cutting is because problem often takes place in the cohesive force deficiency of the dielectric material of low-k.
When carrying out the wafer cutting, cause wafer surface to meet with stresses owing to use mechanical cutting knife to grind pellet, therefore when wafer cuts or after the wafer cutting, can find that the interface between the dielectric material of low-k forms interface delamination (interface delamination) phenomenon or chip crack (chipcracking), and have influence on the reliability of integrated circuit (IC) chip.The mode that is used for monitoring this interface delamination or chip crack at present is to adopt so-called non-destructive scan-type ultrasonic waves microscope (Scanning Acoustic Tomography, abbreviate SAT as) technology, it can detect after the wafer cutting, or detects after chip is finished encapsulation.
Yet aforesaid scan-type ultrasonic waves microscopy but has its shortcoming, when for example after the wafer cutting, carrying out the SAT detection, less chip crack but can't utilize scan-type ultrasonic waves microscopy to detect out, this is that the limit of the chip crack size that can detect of scan-type ultrasonic waves microscopy is about about 1 micron usually owing to be subject to due to the detection limit of scan-type ultrasonic waves microscopy.In addition, detect,, but be difficult to but confirm that its occurrence positions is the interface between chip and encapsulating material even can detection out-of-bounds emaciated face layer if after chip is finished encapsulation, carry out SAT, or in the dielectric layer of chip inside itself.
Summary of the invention
Main purpose of the present invention is promptly providing the test circuit structure of building four fragile corners of chip in a kind of in, can be used to assess the integrality of chip structure, to solve the problem of existing skill.
According to a preferred embodiment of the invention, the invention provides a kind of semiconductor chip of built-in detecting circuit, comprise an active circuit zone; One surrounds the seal ring structure in this active circuit zone; One first circuit structure, it is produced on one first corner that this semiconductor chip is positioned at this seal ring structure outside, and this first circuit structure is electrically connected configuration with this seal ring structure formation, and wherein this first circuit structure has one first connection gasket; And a second circuit structure, it is produced on one second corner that this semiconductor chip is positioned at this seal ring structure outside, and this second circuit structure is electrically connected configuration with this seal ring structure formation, and wherein this second circuit structure has one second connection gasket.
According to another preferred embodiment of the invention, the semiconductor chip of a kind of built-in detecting circuit of the present invention comprises an active circuit zone; One surrounds the seal ring structure in this active circuit zone; One first circuit structure, it is produced on the corner that this semiconductor chip is positioned at this seal ring structure outside, and this first circuit structure do not constitute with this seal ring structure and be electrically connected configuration, and wherein this first circuit structure has one first connection gasket; An and second circuit structure, it is produced on this corner that this semiconductor chip is positioned at this seal ring structure outside, and near this first circuit structure, wherein this second circuit structure becomes to be electrically connected configuration with this first circuit structure, and this second circuit structure has one second connection gasket.
In order to make those skilled in the art can further understand feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing.Yet accompanying drawing is only for reference and aid illustration usefulness, is not to be used for the present invention is limited.
Description of drawings
Fig. 1 illustrates be build in the preferred embodiment of the present invention four corners of chip be used for assessing the chip structure integrality test circuit structure on look schematic diagram;
Fig. 2 illustrates is the generalized section shown in the tangent line I-I in Fig. 1;
What Fig. 3 illustrated is the generalized section of chip after finishing encapsulation that another preferred embodiment of the present invention has the built-in detecting circuit structure;
Fig. 4 illustrates is to build the generalized section that four corners of chip are used for assessing the test circuit structure of chip structure integrality in another preferred embodiment of the present invention in.
The main element symbol description
10 integrated circuit (IC) chip, 12 active circuit zones
14 seal rings, 16 test circuit zones
20 test circuit structure 20a, 20b test circuit structure
22 contact plunger 22a, 22b contact plunger
28 connection gasket 28a, 28b connection gasket
100 silicon base, 120 diffusion conductive regions
200 base plate for packaging, 228 connection gaskets
Embodiment
The present invention can be used to assess the integrality of chip structure relevant for the test circuit structure of building four fragile corners of chip in a kind of in.The dielectric interface delamination often occurs in the low dielectric constant dielectric materials, and it might produce in the middle of the wafer cutting process or after the wafer cutting.And on the position at four angles of each brilliant side or chip; can find that the dielectric interface delamination is the most serious; and the dielectric interface delamination more is deep into the central circuit zone of brilliant side or chip, even its periphery has brilliant side's seal ring (die seal ring) or crack to stop that ditch protects.
The most serious reason of upper dielectric layer interface, position delamination at four angles of each brilliant side or chip, be on the position at stress that wafer employed cutting knife of when cutting causes four angles concentrating on each brilliant side or chip especially, just make these locational dielectric interface delamination especially severes.
See also Fig. 1 and Fig. 2, wherein Fig. 1 illustrates be build in the preferred embodiment of the present invention four corners of chip be used for assessing the chip structure integrality test circuit structure on look schematic diagram, Fig. 2 illustrates is the generalized section shown in the tangent line I-I in Fig. 1.As Fig. 1 and shown in Figure 2, integrated circuit (IC) chip 10 comprises an active circuit zone 12, is surrounded wherein by a seal ring 14.Seal ring 14 is piled up mutually by the metal of many layers and interlayer connector and is formed, and this chip protection structure is common technology in this technical field, mainly is the stress rupture when being used for avoiding active circuit zone 12 to be subjected to the wafer cutting.Usually, seal ring 14 is an individual layer barrier wall structure, but also can be double-decker.
Aforesaid tamper seal ring structure 14 is when making active circuit 12, progressively upwards piles up with steps such as identical dielectric layer deposition step and metal deposition etchings to form.Usually can be earlier in semiconductor substrate; for example silicon substrate forms heavily doped region (not shown), and then tamper seal ring structure 14 is formed on the heavily doped region; and allow specific voltage, for example earthed voltage or VSS offer tamper seal ring structure 14 via heavily doped region.
Aforesaid active circuit 12 can comprise circuit elements such as transistor, electric capacity, doped diffusion region, memory array or metal interconnecting.Integrated circuit (IC) chip 10 also comprises four triangle test circuit zones 16 in seal ring 14 outsides, lays respectively at four corners (as four points of A, B, C, D that indicated among the figure) of integrated circuit (IC) chip 10.As shown in Figure 2, in each test circuit zone 16, then be formed with the test circuit structure 20 that is used for assessing the chip structure integrality.According to a preferred embodiment of the invention, test circuit structure 20 is just like the intraconnections circuit of upright snakelike shape, by the metal (as M1, M2, the M3 that is indicated among the figure) and the interlayer connector of different layers linked (as C1, V1, V2, the V3 that is indicated among the figure).One end of the test circuit structure 20 of upright snakelike shape can be contact plunger 22, and is connected with silicon base 100, and the other end then is a connection gasket 28.Note the protective layer that does not show inner layer dielectric layer especially and cover chip at last among the figure.
The test circuit structure 20 that one of principal character of the present invention is to be formed in the test circuit zone 16 is to constitute with seal ring 14 to be electrically connected configuration, can be by mode of connection in the metal, for example via ground floor metal (M1), as shown in Figure 2, still also can constitute the electrical connection configuration by the diffusion zones that are formed in the silicon base 100.
The mode that the present invention utilizes test circuit structure 20 to detect interface delaminations or chip crack can be that usefulness probe and external test circuitry are checked any two points in A, B, four points of C, D.For instance, if the connection gasket 28 of order simultaneously,, so can detect the defective existence in bounded emaciated face layer whether or chip crack by this because corresponding test circuit structure 20 constitutes the electrical connection configurations via seal ring 14 with probe contact A point and B.If the defective in bounded emaciated face layer or chip crack exists, then the circuit loop that constituted of the test circuit structure 20 of external test circuitry and chip, seal ring 14 then can be opened a way (open), does not pass through and do not have electric current.
See also Fig. 3, what it illustrated is the generalized section of chip after finishing encapsulation that another preferred embodiment of the present invention has the built-in detecting circuit structure.After the connection gasket 28 of test circuit structure 20 is finished encapsulation with base plate for packaging 200 with the Flip-Chip Using technology, the circuit loop test of the A of aforementioned chip, B, C, four points of D then be this moment by be located at base plate for packaging 200 and correspond to A, B, the C of chip, the connection gasket 228 of four points of D is finished.
See also Fig. 4, it illustrates is to build the generalized section that four corners of chip are used for assessing the test circuit structure of chip structure integrality in another preferred embodiment of the present invention in.As shown in Figure 4, integrated circuit (IC) chip 10 comprises an active circuit zone 12 equally, is surrounded wherein by a seal ring 14, and four test circuit zones 16, respectively in seal ring 14 outsides in 10 4 corners of chip.In each test circuit zone 16, then be formed with two test circuit structure 20a and 20b that are used for assessing the chip structure integrality.
Wherein, test circuit structure 20a is just like the intraconnections circuit of upright snakelike shape, linked by the metal and the interlayer connector of different layers, and the one end can be contact plunger 22a, and be electrically connected with diffusion conductive region 120 in being formed on silicon base 100, its other end is connection gasket 28a.Test circuit structure 20b is just like the intraconnections circuit of upright snakelike shape, metal and interlayer connector by different layers are linked, the one end can be contact plunger 22b, and is electrically connected with diffusion conductive region 120 in being formed on silicon base 100, and its other end is connection gasket 28b.Therefore, by being formed on the diffusion conductive region 120 in the silicon base 100, test circuit structure 20a and test circuit structure 20b are electrically connected mutually.According to this embodiment, test circuit structure 20a is electrically connected configuration with test circuit structure 20b is neither with seal ring 14 formations.In addition, these two test circuit structure 20a adjacent to each other also can be electrically connected via other metal level formation with 20b, are electrically connected and do not constitute via diffusion conductive region 120.
In this embodiment, the mode of utilizing test circuit structure 20a and 20b to detect interface delamination or chip crack then is that usefulness probe and external test circuitry are checked the some points in A, B, four points of C, D, just once checks a corner of chip.For instance, if the connection gasket 28a and the 28b of order simultaneously,, so can detect the defective existence in bounded emaciated face layer whether or chip crack by this because corresponding test circuit structure 20a constitutes mutually with 20b and be electrically connected configuration with probe contact A.If the defective in bounded emaciated face layer or chip crack exists, then the circuit loop that constituted of the test circuit structure 20a and the 20b of external test circuitry and chip then can be opened a way, and does not pass through and do not have electric current.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (3)
1. the semiconductor chip of a built-in detecting circuit comprises:
One active circuit zone;
One surrounds the seal ring structure in this active circuit zone;
One first circuit structure, it is produced on the corner that this semiconductor chip is positioned at this seal ring structure outside, and this first circuit structure do not constitute with this seal ring structure and be electrically connected configuration, and wherein this first circuit structure has one first connection gasket; And
One second circuit structure, it is produced on this corner that this semiconductor chip is positioned at this seal ring structure outside, and near this first circuit structure, wherein this second circuit structure becomes to be electrically connected configuration by a diffusion conductive region or a ground floor metal that is formed in the silicon base with this first circuit structure, and this second circuit structure has one second connection gasket.
2. the semiconductor chip of built-in detecting circuit as claimed in claim 1, wherein this seal ring structure is to be piled up mutually by the metal of multilayer and interlayer connector to form.
3. the semiconductor chip of built-in detecting circuit as claimed in claim 1, wherein this first circuit structure and this second circuit structure intraconnections circuit that all is upright snakelike shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101340363A CN101320730B (en) | 2005-08-05 | 2005-08-05 | Semiconductor chip with built-in test circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101340363A CN101320730B (en) | 2005-08-05 | 2005-08-05 | Semiconductor chip with built-in test circuit |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200510089740 Division CN100468721C (en) | 2005-08-05 | 2005-08-05 | Test circuit built-in semiconductor chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101320730A CN101320730A (en) | 2008-12-10 |
| CN101320730B true CN101320730B (en) | 2010-07-14 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2008101340363A Active CN101320730B (en) | 2005-08-05 | 2005-08-05 | Semiconductor chip with built-in test circuit |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102569259B (en) * | 2010-12-30 | 2015-07-29 | 中芯国际集成电路制造(上海)有限公司 | For test circuit and the method for testing thereof of testing chip before package |
| US20130009663A1 (en) * | 2011-07-07 | 2013-01-10 | Infineon Technologies Ag | Crack detection line device and method |
| US8796686B2 (en) * | 2011-08-26 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits with leakage current test structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5831330A (en) * | 1996-06-28 | 1998-11-03 | Winbond Electronics Corp. | Die seal structure for a semiconductor integrated circuit |
| US6365958B1 (en) * | 1998-02-06 | 2002-04-02 | Texas Instruments Incorporated | Sacrificial structures for arresting insulator cracks in semiconductor devices |
| CN1433059A (en) * | 2002-01-07 | 2003-07-30 | 三星电子株式会社 | Semiconductor device test system |
-
2005
- 2005-08-05 CN CN2008101340363A patent/CN101320730B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5831330A (en) * | 1996-06-28 | 1998-11-03 | Winbond Electronics Corp. | Die seal structure for a semiconductor integrated circuit |
| US6365958B1 (en) * | 1998-02-06 | 2002-04-02 | Texas Instruments Incorporated | Sacrificial structures for arresting insulator cracks in semiconductor devices |
| CN1433059A (en) * | 2002-01-07 | 2003-07-30 | 三星电子株式会社 | Semiconductor device test system |
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| Publication number | Publication date |
|---|---|
| CN101320730A (en) | 2008-12-10 |
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