CN101316160B - Multi-node synchronization sampling and data transmission method - Google Patents
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Abstract
The invention provides a multi-node synchronous sampling control and data transmission method, the steps are as follows:(1) an overall synchronizer that matches with the upper layer data processing equipment and the process variable acquisition control equipment (DAE) is constructed, the equipment produces an overall synchronous signal S1 by utilizing an outer sync source or a local timer; (2) the overall synchronous signal is accessed to one or more data communication equipment (DCE), which produce a synchronous signal S2 for each accessed process variable acquisition control equipment; (3) the absolute time scale in the signal S1 and the overall sampling counter are utilized to realize the secondary synchronous sampling on the process variable among the data communication equipment; (4)the acquisition control equipment (DAE) for acquiring and outputting the process variable detects the synchronous signal and order data after receiving the signal S2; (5) the acquisition control equipment dynamically adjusts the start time of the S2 signal according to Delta ti and realizes the long-distance multinode synchronous sampling.
Description
One, technical field
The present invention relates to be distributed in the method for synchronized sampling and real-time Data Transmission between a plurality of data acquisition nodes of different places.Especially in control of needs distributed capture and centralized data processing, to data sampling request strict synchronism, sampled data requires real-time Transmission, protecting electrical power system field and industrial control field that time delay is fixing.Specifically, the present invention is the method for multinode synchronous data collection and real-time Transmission.
Two, background technology
In relay protection of power system and industrial process control field; be the phase information of stick signal accurately; or asynchronous event carried out accurate Time-Series analysis; need carry out strict strange land to a certain group of process variable uniformly-spaced gathers synchronously; for the sampled data that improves system's processing capability in real time and asynchronous event response speed and need each process variable acquisition control device is sent on can be in real time, and the order configuration information of processing unit need mail to actuator or governor motion in real time.Some standards such as IEC61850-5 have just defined the sampled value synchronous accuracy of 3 grades: T3, T4 and T5.Wherein: the T3 class requirement is 25 μ s, is used for distribution line protection; The T4 class requirement is 4 μ s, is used for line protection; The T5 class requirement is 1 μ s, is used for metering [5].And equal interval sampling is that the back level is based on accurate synchronized sampling algorithm basis [4], the synchronous acquisition ratio is easier to realize when tested process variable can insert same harvester, but be positioned at different harvesters when these process variables, and these harvester physical distribution just there is not unified implementation method when being not together.
Present existing synchronized sampling control method mainly comprises following three kinds of methods:
1. follow the IEC61850-9-1 architecture,, produce the enabling signal of control ADC again by combiner, realize multinode sampling [3] by the synchronous a plurality of combiners in precision clock source.
2. based on the synchronous sampling system of IEEE1588 Precision Time Protocol PTP (Precision Time Protocol), synchronous by the dcs that satisfies multi-point being adopted the clock of multicasting technology terminal equipment carry out the microsecond level, and then realize sample-synchronous according to absolute time.
3.GPS same footwork.Utilize the GPS module to provide pulse per second (PPS) for different physical distribution nodes, the pulse per second (PPS) that each node sample is synchronized with the output of GPS module realizes the global synchronization sampling.
The weak point of present existing synchronized sampling control method:
1.IEC61850-9-1 architecture needs independently synchronizing channel, generally adopt the synchronous combiner of pulse per second (PPS), this architecture is not considered the transmission link effect length, and the direction of transfer of data is unidirectional, inapplicable when needs main and subordinate node interactive information, require high to synchronous Zhong Yuan and local clock.
If the cycle of Zhong Yuan is T synchronously, and the sampling period of actual ADC is Ta, for realizing that equal interval sampling should have
T=N * T
aIn the formula: N is a sampling number in period T
f
0=1/T=(1/NT
a)=f
aIn/N the formula: f
a=1/T
aBe the local node work clock
Because f
0, f
a, N is an integer, when sample rate N was high more, following formula can't accurately equate more, between the different nodes because f
aIn fact difference and frequency drift can't realize synchronous equal interval sampling.
2. based on the synchronous sampling method of IEEE1588, need to support the network hardware interface and the switching equipment of IEEE1588 agreement, increase extra cost.And, make it inapplicable synchronous acquisition and the control that physically distributes between a plurality of nodes far away because IEEE802.3 has requirement to Ethernet transmission range and Network Transmission time-delay.The IEEE1588 per second starts a synchronizing process, behind the synchronization failure of clock school, needs the relative error Δ t of repeated calculation both sides clock once more synchronously, and synchronizing relay is longer.
In addition, when high speed multinode acquisition control device was connected to same main controlled node, the network conflict aggravation influenced real-time Data Transmission during heavy duty, can not guarantee that each sampled data is transferred to data processing terminal under fixing time delay.
Influence 3.GPS be subjected to the number of satellite of being caught of GPS with footwork, and the restriction of factors such as natural environment and social environment, and need the relevant hardware support, and needing extra data transmission channel, cost is higher.List of references:
1. Gao Houlei, Jiang Shifang, He Jiali.Several sampling synchronization methods in the digital current differential protection. Automation of Electric Systems, 1996,20 (9).
2. Yang Wei Na, the honest and clean .PCM of Bao Wei system transmits the signal processing of relaying protection data, communication of power system, 1992 (2)
3. good Liu ten thousand of Yin Zhi is along a kind of synchronous realization new method of merge cells of following the IEC61850 standard of the inferior Qin of Yang Qi stress. Automation of Electric Systems .2004,28 (11) .-57-61
4. accurate synchronized sampling and the application Chinese journal of scientific instrument in the non-sine power measurement in November, 1984 thereof in wearing earlier
5.IEC?61850-5.Communication?Networks?and?Systems?in?Substations，Part?5：Communication?Requirements?for?Functions?and?Device?Models.2003.
6. good Liu ten thousand of Yin Zhi realizes the synchronous new technology Automation of Electric Systems of Substation Process Bus sampled value .2005,29 (13) .-60-63 along the inferior Qin of Yang Qi stress based on IEEE 1588
Three, summary of the invention
The present invention seeks to propose a kind ofly on a pair of full-duplex link, to have realized the method for synchronized sampling control and real-time Data Transmission, and solve between a plurality of acquisition controlling nodes of different physical distribution the extra time delay that is produced owing to physical link length and software protocol stack.
The present invention realizes by such scheme: multi-node synchronization sampling and data transmission method:
(1). make up a global synchronization device (hereinafter to be referred as GSE) that is complementary with upper layer data treatment facility and process variable acquisition control device, this equipment can utilize external synchronisation source, also can utilize local timer to produce a global synchronizing signal S1, its cycle is exactly the sampling period of process variable acquisition control device, comprises absolute time mark and overall sample counter in this signal by being coded in.
(2). global synchronizing signal is inserted the equipment that one or more (being determined by system scale) are referred to as communicator (hereinafter to be referred as DCE), this equipment is that the process layer acquisition control device of each access produces a synchronizing signal S2, the cycle of S2 is exactly the cycle of global synchronizing signal S1, but the startup of signal is constantly relevant with link between the corresponding harvester with it, promptly than S1 delay Δ t
i(i is the harvester numbering, i=1, and 2 ... n).Make it to carry the upper layer data treatment facility by coding and mail to corresponding acquisition control device control information and synchronizing signal signal S2.
(3). utilize absolute time mark and overall sample counter among the signal S1, the second synchronization of implementation procedure amount sampling between a plurality of communicators.
(4). be responsible for the process variable collection and carry out the acquisition control device of exporting (hereinafter to be referred as DAE) after receiving signal S2, detecting synchronizing signal and order data, start the collection of local process variable and return path signal S3 immediately to DCE under the control of synchronizing signal, promptly S3 is that strict clock is relevant with S2. by the coding to signal S3 make it to carry last one constantly sampled data and mail to the application data of upper layer data treatment facility.
(5). calculate communicator to acquisition control device DAE by formula 3-1, formula 3-2 and formula 3-3 when arriving in each overall signal
i(i=1,2, channel latency amount Δ t 3......)
i(establish link transmission and postpone to be t
Delay, and think that the physical link of transceive data is isometric), according to Δ t
iThe startup of dynamically adjusting the S2 signal realizes the synchronized sampling of remote multinode constantly.
t
Delay=(t
Rcv-t
Se-T
FH)/2 (formula 3-1)
Δ t=T
Dm-(t
Rcv-t
Se-T
FH)/2=T
Dm-t
Deay(formula 3-2)
T
Dm=max{t
Delay0, t
Delay1..., t
Delayn(formula 3-3)
In the formula: Δ t--channel delay amount
T
FH--synchronization frame head width
T
Dm--system's maximum link transmission delay, can estimate according to maximum link length
t
Se--special modality sends sync waveform constantly, t
Rcv--receive the moment of foldback data
Because sampled data returns under the control of sample-synchronous signal, obtain the time delay and the transmission bandwidth of stable real-time sampling data, in signal, carry control command and synchronizing signal simultaneously, realized with sample-synchronous on a pair of link and transfer of data by coding.
Acquisition control device of the present invention mails to the Frame of communicator, is made up of sampled data field and User Agreement field.The sampling field transmits sampled data last time at every turn, and protocol fields transmits higher layer protocol data units, constitutes two logic channels, and sampled data is a real-time Transmission, the transmission of protocol data non real-time.Same Frame is transmitted twice in a sampling interval, link layer controller determines to choose one of them according to the frame check sign indicating number, simplifies transmission mechanism and improves the channel error correcting capability.
Multi-node synchronization sampling control and data transmission method are fit to need to arrange acquisition control device in different places; the global data sampling needs strict synchronism, the sampled data propagation delay time is required the protecting electrical power system field and the industrial control field of the real-time intensive data processing of fixing distributed capture.
Characteristics of the present invention
(1). utilize a pair of data link to realize transfer of data and synchronized sampling, cost is low, good reliability.
(2). finish transfer of data in each sampling period, fixing constantly, need not to insert markers, can directly transmit sampled data, be convenient to high layer software and carry out depth analysis.
(3). calculate a plurality of Channel Transmission delays automatically and adjust each channel synchronization signal, guarantee precise synchronization between a plurality of nodes.
(4). sampled data is continuous to pass twice, improves the channel error correcting capability, reduces the expense that high level requests is retransmitted again
(5). data field is divided into real time data field and protocol data field, guarantees that real-time Data Transmission provides logic channel transmission upper-layer protocol data simultaneously.
(6). synchronization accuracy is not influenced by channel physical length, not influenced by external condition, can reach nanosecond.
(7). utilize coding generation synchronizing signal in violation of rules and regulations, the transmit leg synchronous points is the signal leading edge, and the back edge of recipient's synchronous points signal guarantees that synchronizing signal accurately detects.
(8). channel time delay quantity algorithm of the present invention and transmission and error control rule are effectively simple, and suitable design realizes based on FPGA, improves systematic function by parallel processing.
Description of drawings
Fig. 1 multi-node synchronization sampling control system structure chart
Fig. 2 global synchronization device synchronizing signal S1
Fig. 3 communicator synchronously/command signal S2 (S3)
Fig. 4 multi-node synchronization sampling system works sequential chart
Embodiment
1. the multinode synchro system constitutes
Typically multi-node synchronization sampling and data transmission system are as shown in Figure 1:
System has three-decker from bottom to top, and Level 1 is an acquisition control device, is responsible for process variable collection and control command and carries out, and process variable to be measured and execution/governor motion are connected on the acquisition control device.DAE log-on data sampling after receiving synchronous/order (Syn/Cmd) signal is carried out the corresponding command and is also transmitted sampled data.Level 2 comprises global synchronization device (hereinafter to be referred as GSE) and communicator (hereinafter to be referred as DCE), wherein synchronizer is responsible for producing global synchronizing signal by the sampling interval of high-rise requirement, responsible each acquisition control device synchronously of communicator and transparent forwarding are from the data of upper strata or lower floor, Level 3 is data processing equipment (hereinafter to be referred as DPE), is responsible for real time data processing and issues control command.The present invention only relates to Level 1 and Level 2. in the system
S among Fig. 1
0Be external synchronization signal, pass through S
0Can insert distant place synchronizing signal, enlarge system scale, realize a plurality of system synchronization samplings.S
1Be sampling/timing signal, produce the process variable sampling enabling signal that meets the upper layer device requirement by synchronizer, this signal comprises overall absolute time mark and sample counter simultaneously.S
2For communicator mail to acquisition control device synchronously/command signal, this signal comprises the protocol Data Unit that process variable sampling enabling signal and upper layer device mail to harvester.S
2For acquisition control device mails to communicator sampled data and protocol Data Unit, this signal comprises a lock-out pulse.By expanding equipment in Fig. 1 frame of broken lines, can enlarge local synchro system scale.
The present invention adopts the fixed length frame, and transmission delay is fixed, and the signal waveform that is used for transfer of data and Synchronization Control forms by synchronous head and data field subsequently, the additional error control frame check sign indicating number that is used for.
2. global synchronizing signal S
1
The synchronizing signal S of synchronizer output among Fig. 1
1Physical layer regularly and coding as shown in Figure 2, coding uses high level width means information, each symbol width is T
bT among the figure
hBe width of frame synchronization header, following closely after the synchronous head is data segment, T
0Be the width of code element logical zero, T
1Be the width of code element logical one, Ts is the sampling interval.T
h, T
0And T
1Be T
bFunction.Synchronizer sends synchronizing signal, t with interval T s
FsBe the frame starting point, it is T that the recipient is consecutively detected two width
hHigh level is thought and is detected frame synchronizing signal, t in the signature
SynBe the synchronous Detection Point of recipient, the low level of a symbol width is arranged before the frame synchronization head, can guarantee to detect synchronously.At signal S
1Data field in, comprise absolute time mark and one 8 s' sample counter.When system connects a plurality of communicator, utilize the sample counter of the overall situation to come the mark sampled data of a certain particular moment, can carry out double sampling according to the needs of data processing equipment.
3. synchronized sampling/data transfer signal S
2/ S
3
As shown in Figure 2, communicator downstream signal S among the present invention
2With harvester upward signal S
3Frame format identical, physical layer regularly and coding as Fig. 3.In the sampling interval, data are transmitted twice continuously, t among the figure
Fs0Be transmit leg frame starting point, t
SynBeing recipient's synchronizing signal Detection Point, is T by two continuous width
SynhThe high level marker frame begin, be T by a width
SynhThe high level mark subsequently with data retransmission, t
FslFor transmitting the initial moment for the second time.T among the figure
0Be synchronization point, t
1Be the initial moment of data re-transmission, t
2Be the next sampling interval, Ts is a complete time in sampling interval.The data fields of every frame begins t after one leading 1
DatExpression data fields zero hour, T
SpaceBe the time width of marking signal between leading 1, T
bIt is a data bit width.The data fields coding adopts graceful Chester coding, so that can join with the difference transceiver.
Because S of the present invention
2/ S
3Middle control frame signal does not adopt graceful Chester coding, and width is also roomy a lot of than data bit, so the recipient can recover synchronizing signal by the pulse duration detection method.
4. error control and protocol data transmission
As shown in Figure 3, among the present invention, signal S
2/ S
3Data field (t from Fig. 3
DatBeginning) be divided into following three parts, sampled data, protocol data and frame check part, as shown in table 1.
The data link layer frame format of table 1 signal S2/S3
| Sampled data | The User Agreement data | Frame check (CRC) |
Sampled data field of the present invention should be assembled by SGDMA (scatter gather DMA), perhaps when starting transmission, fill by the lowermost layer of protocol stack. utilize the User Agreement data field can constitute a non real-time logic channel, be used for transmitting monitor message between the high level of DAE and equity.As shown in table 2, a protocol data transmission may comprise a plurality of sampling intervals.
In the present invention, the bit wide ratio of sampled data and protocol data is by using decision, and frame check is that the whole frame of a protocol data of 16 CRC. may be formed by n the packet assembling of the protocol data shown in the table 20 to protocol data n-1, decides on concrete application.
Table 2 protocol data S2/S3 forms
Because the data of gathering must be sent in each sampling interval in real time, can not adopt the mechanism of the request repeat of makeing mistakes when high-speed sampling, and the mistake on the serial link can be corrected by a frame subsequently if not the autgmentability mistake.The same frame data of the present invention are in link layer running fire twice, and the recipient determines to choose correct one group according to frame check, if two groups of all wrong submissions are high-rise definite.
5. multi-node synchronization sampling system works principle
Mutual and the timing information of holonomic system work physical layer signal is that example has provided the working signal sequential between global synchronization device GSE and two acquisition control devices and the communicator with two acquisition control devices among Fig. 4 as shown in Figure 4.
Ts is the sampling period among Fig. 4, waveform Wav0 is the synchronizing signal of GSE to DCE, Wav00 is the synchronous/command waveform of communicator DCE to acquisition control device DAE0, and Wav01 is for receiving sync waveform through transmission delay DAE0, and Wav02 is that DCE receives the sampled data waveform from DAE0.Wav10 be communicator DCE to acquisition control device DAE1 synchronously/command waveform, Wavll receives sync waveform for the DAE0 side through transmission delay, Wav12 receives sampled data waveform from DAE1 for the DCE side joint.Similarly, if a DCE inserts a plurality of acquisition control devices, then data waveform on the physical link and transmission course and DAE0 and DAE1 are similar, no longer analyze.
6. channel time delay and synchronized sampling are realized
Among Fig. 4 at moment t
0Target sample-synchronous signal S when synchronizer GSE sends band
1, communicator calculates the same S of the synchronizing signal that mails to DAE0 and DAE1 according to last one link delay of determining constantly
1Retardation be Δ t
0With Δ t
1, and at moment t
1And t
2Produce each motor synchronizing/command signal S respectively
2, seeing that waveform Wav01 and Wavll. postpone through communication link, DAE0 and DAE1 are at moment t
sProduce local process variable and gather enabling signal, the data of a sampling instant on the while foldback are referring to waveform Wav02 and Wav12.Each sampling interval of channel delay amount calculates once, and computational methods are as follows:
As above Fig. 6 can calculate the amount of delay Δ t of passage i by formula 3-1, formula 3-2 and formula 3-3
i, being docked at the acquisition control device on the passage i, the synch command frame is at moment t
Fsi=t
0+ Δ t
i(i=0,1,2 ... .) send, the data sampling of establishing acquisition control device i is t constantly
IADC, t
DelayiBe the link transmission time-delay of passage i, T
FHBe the frame head width, composite type 3-1 and formula 3-2 have:
t
IADC=t
0+ Δ t
i+ t
Delayi+ T
FH=t
0+ T
Dm+ T
FH=t
5(formula 3-4)
The result of formula 3-4 is a constant, so if can guarantee that by i selector channel, last method selector channel retardation all acquisition control devices are at synchronization t
IADC(=t
0+ T
Dm+ T
FH) the log-on data sampling.
7. channel error code and data integrity monitor
Harvester of the present invention adopts graceful Chester coding to the data field of the signal S2/S3 between the communicator, and the decoding parts can monitor the signal integrity of each bit, and monitoring data frame integrality provides the frame fragment to detect simultaneously.By monitoring that data flow is come the monitoring channel working condition on the receive channel, to high layer software transmitting channel locking signal, so that take algorithms of different or control strategy according to the channel working condition.
Claims (6)
1. multi-node synchronization sampling is controlled and data transmission method, it is characterized in that step is as follows:
(1) makes up a global synchronization device that is complementary with upper layer data treatment facility and process variable acquisition control device (DAE), described global synchronization device utilizes external synchronisation source or local timer to produce a global synchronizing signal S1, its cycle is exactly the sampling interval of process variable acquisition control device, makes S1 carry absolute time mark and overall sample counter information by coding;
(2) global synchronizing signal is inserted one or more equipment that are referred to as communicator (DCE), communicator is that the process variable acquisition control device of each access produces a synchronizing signal S2, the cycle of S2 is identical with the cycle of global synchronizing signal S1, but the startup of S2 is constantly relevant with link between the corresponding process variable acquisition control device with it, promptly than S1 delay Δ t
i, i is process variable acquisition control device numbering, i=1, and 2 ... n; Make S2 carry the upper layer data treatment facility by coding and mail to corresponding process amount acquisition control device control command data information and synchronizing signal signal S2;
(3) utilize absolute time mark and overall sample counter among the signal S1, the second synchronization of implementation procedure amount sampling between a plurality of communicators;
(4) the process variable acquisition control device (DAE) of responsible process variable collection and execution output detects synchronizing signal and order data after receiving signal S2, under the control of synchronizing signal S2, start the collection of local process variable immediately and return data-signal S3, make it to carry the sampled data and the application data that mails to the upper layer data treatment facility in last sampling interval by coding S3 to communicator;
(5) when arriving communicator, each global synchronizing signal recomputates communicator to process variable acquisition control device DAE
i, i=1,2 ... the channel latency amount Δ t of n
i, according to Δ t
iThe startup of dynamically adjusting the S2 signal realizes the synchronized sampling of remote multinode constantly.
2. multi-node synchronization sampling control according to claim 1 and data transmission method is characterized in that: global synchronizing signal S1 uses high level width means coded message, and each symbol width is T
b, be T by a width
bLeading 0 and two continuous high level width be T
hPulse configuration frame synchronous head, additional data field subsequently, the high level width of logical zero is T
0, the high level width of logical one is T
1, T
h, T
0And T
1Be T
bFunction; The global synchronization device sends synchronizing signal S1 with interval T s, and it is T that the recipient is consecutively detected two width
hHigh level thinks and detects frame synchronizing signal, and is T with a back high level width
hThe trailing edge of pulse be labeled as the synchronous Detection Point of recipient.
3. multi-node synchronization sampling according to claim 1 control and data transmission method is characterized in that: synchronizing signal S2 is identical with the frame format of data-signal S3, are that leading 0 and two continuous high level width of Tp is T by a width
SynhPulse configuration frame synchronous head, a width is T behind the mark
SynhThe trailing edge of pulse is the synchronous Detection Point of recipient.
4. multi-node synchronization sampling control according to claim 1 and data transmission method, it is characterized in that: the Frame that mails to communicator at the process variable acquisition control device is made up of sampled data field and User Agreement field, the sampled data field transmits sampled data last time at every turn, the User Agreement field transmits the upper-layer protocol data cell, constitute two logic channels, sampled data is a real-time Transmission, the transmission of protocol data non real-time.
5. multi-node synchronization sampling control according to claim 3 and data transmission method, it is characterized in that: at the information frame of communicator and the exchange of process variable acquisition control device, same packet is transmitted twice in a sampling interval, be T by two continuous width
SynhThe high level marker frame begin, T
SpaceLow level and one leading 1 and subsequently data field constitute first packet; By a width is T
SynhThe high level mark subsequently with data retransmission, link layer controller determines to choose one of them packet according to the frame check sign indicating number, simplifies transmission mechanism and also improves the channel error correcting capability.
6. multi-node synchronization sampling according to claim 1 control and data transmission method is characterized in that: the link delay that communicator DCE determined according to global synchronizing signal S1 and last sampling interval calculates and mails to process variable acquisition control device DAE
iThe retardation of synchronizing signal S1 be Δ t
i, and at moment t
Fsi=t
0+ Δ t
iI=1,2 ... n sends synchronizing signal S2, wherein, and t
0In the moment for the global synchronization device sends global synchronizing signal S1, postpone DAE through communication link
iAt moment t
IADCProduce local process variable sampling enabling signal, the data of a sampling instant on the while foldback, retardation Δ t
iComputational methods as follows:
t
delay＝(t
rcv-t
se-T
FH)/2
Δt＝T
dm-(t
rcv-t
se-T
FH)/2＝T
dm-t
delay
T
dm＝max{t
delay0，t
delay1，...，t
delayn}
t
IADC=t
0+ Δ t
i+ t
Delayi+ T
FH=t
0+ T
Dm+ T
FH=constant
In the formula: Δ t--channel latency amount
T
FH--synchronization frame head width,
T
Dm--system's maximum link transmission delay, can estimate according to maximum link length
t
Se--special modality sends sync waveform constantly, t
Rcv--receive the moment of foldback data
t
Delay--link transmission postpones, and the physical link of establishing transceive data is isometric.
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