Drawings
FIG. 1 illustrates a panel structure of a conventional display;
FIG. 2 shows a driving waveform of FIG. 1 and a corresponding pixel voltage Vr、VgAnd Vb;
FIG. 3 is a schematic diagram of a panel structure of an image display system according to the present disclosure;
FIG. 4 shows a driving waveform (R) of FIG. 3
G
B) And a corresponding pixel voltage V
r、V
gAnd V
b;
FIG. 5 is a diagram of a panel structure shown in FIG. 3 with the addition of the liquid crystal capacitance of the pixel and the parasitic capacitance of the transistors in the pixel;
FIG. 6 shows a driving waveform (B) of FIG. 3
G
R) and a corresponding pixel voltage V
r、V
gAnd V
b;
FIG. 7 shows an embodiment of the present disclosure;
FIG. 8 is another embodiment of the present disclosure; and
fig. 9 shows an apparatus to which the present invention is applied.
Description of the figures
100-traditional panel; 102-a demultiplexer;
202. 204, 206-voltage coupling offset;
300 to the panel of the scheme;
702-a demultiplexer;
900 to an electronic device; 902-pixel matrix;
904-display panel; 906-an input unit;
b-blue pixels;
CKHr、CKHgand CKHb-a frequency signal;
Cgd-gate-drain parasitic capacitance of transistors within a pixel;
Clc-a liquid crystal capacitance of a pixel; CS control signal of demultiplexer;
Cst-a storage capacitor;
Cstr、Cstgand Cstb-storage capacitors for red, green and blue pixels;
Cst1、Cst2and Cst3-storage capacitors of the first, second and third pixels;
Data-Data voltage source;
D1、D2and D3-a data signal line;
Dr、Dgand Db-a data signal line;
g to green pixels;
P1、P2and P3-a pixel;
r-red pixels;
scan-scanning signal lines; SWr、SWgAnd SWb-a switch;
t-transistor; t is1、T2And T3-a transistor;
t1-t4-a point in time;
Vcom-voltage of the shared electrode;
Vfr、Vfgand VfbFeed-through voltages for red, green, and blue pixels;
Vr、Vgand VbRed, green, blue pixel voltages;
V1、V2and V3-first, second and third pixel voltages;
Δ V-the difference between the data voltage written into the pixel and the voltage of the common electrode;
ΔVgate-voltage variation of the Scan signal Scan; and
ΔVr、ΔVgand Δ Vb-voltage coupling offsets for red, green and blue pixels.
Detailed Description
Fig. 3 is a panel structure 300 of an image display system according to the present application, which includes a red pixel R, a green pixel G, and a blue pixel B. The red pixel R includes a red pixel electrode coupled to a voltage Vr) A transistor T and a storage capacitor Cstr. The green pixel G includes a green pixel electrode coupled to a voltage Vg) A transistor T and a storage capacitor Cstg. The blue pixel B includes a blue pixel electrode coupled to a voltage Vb) A transistor T and a storage capacitor Cstb. A Scan signal line Scan is coupled to the gate terminal of the transistor T for transmitting a Scan signal to turn on the transistor T. The drain terminals of the transistors T of the pixels R, G and B are respectively coupled to the data signal line Dr、DgAnd Db. To reduce the number of pins of the panel chip, the panel 300 also includes a demultiplexer 102, as in the conventional panel 100, which allows the pixels R, G and B to share a Data voltage source Data. The demultiplexer 102 comprises three switches SWr、SWgAnd SWbRespectively by a pulse signal CKHr、CKHgAnd CKHbAnd (4) controlling.
Compared with FIG. 1, the panel 300 is different from the conventional panel 100 in that each pixel uses the same storage capacitor CstThe panel 300 must have a dedicated storage capacitor C designed for each pixel R, G and Bstr、CstgAnd Cstb。
The driving waveforms and the voltage values V of the pixel electrodes shown in FIG. 4 are as follows
r、V
g、V
bIllustrating the storage capacitor C
str、C
stgAnd C
stbDesign summary ofCan be read. The pixels R, G and B are driven in the order of R
G
B. The signal from the Data voltage source Data will be at the time point t
1Writing the red pixel R at a time point t
2Writing the green pixel G and at a time point t
3The blue pixel B is written. This example assumes that the gamma setting parameters (gamma setting) are the same for each pixel and that the pixels R, G, B are driven with the same gray scale values. The pixel voltage V
rAt a time point t
1~t
2The locked voltage value will be equal to the pixel voltage V
gAt a time point t
2~t
3The locked voltage value will also be equal to the pixel voltage V
bAt a time point t
3~t
4The locked voltage value, the pixel voltage and a common level V
comThe difference is Δ V. The pixel electrodes are voltage-coupled to each other, the pixel voltage V being as described in the prior art
rWill follow the pixel voltage V
gAnd V
bVariation, there is a voltage coupling offset Δ V
r(ii) a And the pixel voltage V
gWill follow the pixel voltage V
bVariation, there is a voltage coupling offset Δ V
g。
Analyzing the circuit structure of the pixels R, G, B shown in FIG. 3, FIG. 5 also considers the liquid crystal capacitance C of each pixellcAnd the parasitic capacitance C of the grid and the drain of the transistor T in the pixelgd. When the Scan signal Scan turns off the transistor T, the voltage of the Scan signal Scan changes by Δ VgateWill let the pixel voltage V of the pixel R, G, Br、Vg、VbThen, the voltage is decreased, and the decreased amplitude is called feed-through voltage (feedthru). As shown in fig. 4, at a time point t4The pixel voltage Vr、Vg、VbWill respond to the voltage change DeltaVgateRespectively generate a feed-through voltage Vfr、VfgAnd Vfb. Observe the circuit of FIG. 5, canObtaining the feed-through voltage value Vfr、VfgAnd VfbComprises the following steps:
<math> <mrow> <msub> <mi>V</mi> <mi>fr</mi> </msub> <mo>=</mo> <mi>Δ</mi> <msub> <mi>V</mi> <mi>gate</mi> </msub> <mo>×</mo> <mfrac> <msub> <mi>C</mi> <mi>gd</mi> </msub> <mrow> <msub> <mi>C</mi> <mi>str</mi> </msub> <mo>+</mo> <msub> <mi>C</mi> <mi>lc</mi> </msub> <mo>+</mo> <msub> <mi>C</mi> <mi>gd</mi> </msub> </mrow> </mfrac> <mo>;</mo> </mrow></math> (formula 1)
<math> <mrow> <msub> <mi>V</mi> <mi>fg</mi> </msub> <mo>=</mo> <mi>Δ</mi> <msub> <mi>V</mi> <mi>gate</mi> </msub> <mo>×</mo> <mfrac> <msub> <mi>C</mi> <mi>gd</mi> </msub> <mrow> <msub> <mi>C</mi> <mi>str</mi> </msub> <mo>+</mo> <msub> <mi>C</mi> <mi>lc</mi> </msub> <mo>+</mo> <msub> <mi>C</mi> <mi>gd</mi> </msub> </mrow> </mfrac> <mo>;</mo> </mrow></math> And (formula 2)
<math> <mrow> <msub> <mi>V</mi> <mi>fb</mi> </msub> <mo>=</mo> <mi>Δ</mi> <msub> <mi>V</mi> <mi>gate</mi> </msub> <mo>×</mo> <mfrac> <msub> <mi>C</mi> <mi>gd</mi> </msub> <mrow> <msub> <mi>C</mi> <mi>stb</mi> </msub> <mo>+</mo> <msub> <mi>C</mi> <mi>lc</mi> </msub> <mo>+</mo> <msub> <mi>C</mi> <mi>gd</mi> </msub> </mrow> </mfrac> <mo>.</mo> </mrow></math> (formula 3)
The invention will be realized by designing the storage capacitor Cstr、CstgAnd CstbAdjusting the feed-through voltage Vfr、VfgAnd VfbTo compensate for the voltage coupling offset Δ VrAnd Δ VgAnd the color cast phenomenon of the screen is eliminated.
Referring to the illustrative example of FIG. 4, to eliminate the color shift of the screen, the feed-through voltage V is appliedfr、VfgAnd VfbThe following equation must be satisfied:
ΔV+ΔVr-Vfr=ΔV+ΔVg-Vfg=ΔV-Vfb。
therefore Vfr=ΔVr+Vfb(ii) a And Vfg=ΔVg+Vfb. Combining the above equations 1 and 2, the storage capacitance C of the blue pixel BstbThe voltage coupling offset Δ V has been set and has been simulated by a computerrAnd Δ VgOn the premise of the above-mentioned storage capacitor CstrAnd CstgThe design principle of (1) is as follows:
<math> <mrow> <msub> <mi>C</mi> <mi>str</mi> </msub> <mo>=</mo> <mfrac> <mrow> <mi>Δ</mi> <msub> <mi>V</mi> <mi>gate</mi> </msub> <mo>×</mo> <msub> <mi>C</mi> <mi>gd</mi> </msub> </mrow> <mrow> <mi>Δ</mi> <msub> <mi>V</mi> <mi>r</mi> </msub> <mo>+</mo> <msub> <mi>V</mi> <mi>fb</mi> </msub> </mrow> </mfrac> <mo>-</mo> <msub> <mi>C</mi> <mi>lc</mi> </msub> <mo>-</mo> <msub> <mi>C</mi> <mi>gd</mi> </msub> <mo>;</mo> </mrow></math> and
<math> <mrow> <msub> <mi>C</mi> <mi>stg</mi> </msub> <mo>=</mo> <mfrac> <mrow> <mi>Δ</mi> <msub> <mi>V</mi> <mi>gate</mi> </msub> <mo>×</mo> <msub> <mi>C</mi> <mi>gd</mi> </msub> </mrow> <mrow> <mi>Δ</mi> <msub> <mi>V</mi> <mi>g</mi> </msub> <mo>+</mo> <msub> <mi>V</mi> <mi>fb</mi> </msub> </mrow> </mfrac> <mo>-</mo> <msub> <mi>C</mi> <mi>lc</mi> </msub> <mo>-</mo> <msub> <mi>C</mi> <mi>gd</mi> </msub> <mo>;</mo> </mrow></math>
wherein VfbEstimated via equation 3.
However, if the pixel R is described above
G
B are different in driving sequence, and the storage capacitor C
str、C
stgAnd C
stbThe design principle of (a) must be adjusted accordingly. The driving sequence of the pixels R, G, B in FIG. 6 is B
G
And R is shown in the specification. The signal from the Data voltage source Data will be at the time point t
1Writing the blue pixel B at a time point t
2Write the green pixel G and at a time t
3The red pixel R is written. In order to eliminate screen color cast, the feed-through voltage V
fr、V
fgAnd V
fbThe following equation must be satisfied:
ΔV+ΔVb-Vfb=ΔV+ΔVg-Vfg=ΔV-Vfr。
therefore Vfb=ΔVr+Vfr(ii) a And Vfg=ΔVg+Vfr. Combining the above equations 2 and 3, the storage capacitance C of the red pixel RstrThe voltage coupling offset Δ V has been set and has been simulated by a computerbAnd Δ VgOn the premise of the above-mentioned storage capacitor CstbAnd CstgThe design principle of (1) is as follows:
<math> <mrow> <msub> <mi>C</mi> <mi>stb</mi> </msub> <mo>=</mo> <mfrac> <mrow> <mi>Δ</mi> <msub> <mi>V</mi> <mi>gate</mi> </msub> <mo>×</mo> <msub> <mi>C</mi> <mi>gd</mi> </msub> </mrow> <mrow> <mi>Δ</mi> <msub> <mi>V</mi> <mi>b</mi> </msub> <mo>+</mo> <msub> <mi>V</mi> <mi>fr</mi> </msub> </mrow> </mfrac> <mo>-</mo> <msub> <mi>C</mi> <mi>lc</mi> </msub> <mo>-</mo> <msub> <mi>C</mi> <mi>gd</mi> </msub> <mo>;</mo> </mrow></math> and
<math> <mrow> <msub> <mi>C</mi> <mi>stg</mi> </msub> <mo>=</mo> <mfrac> <mrow> <mi>Δ</mi> <msub> <mi>V</mi> <mi>gate</mi> </msub> <mo>×</mo> <msub> <mi>C</mi> <mi>gd</mi> </msub> </mrow> <mrow> <mi>Δ</mi> <msub> <mi>V</mi> <mi>g</mi> </msub> <mo>+</mo> <msub> <mi>V</mi> <mi>fr</mi> </msub> </mrow> </mfrac> <mo>-</mo> <msub> <mi>C</mi> <mi>lc</mi> </msub> <mo>-</mo> <msub> <mi>C</mi> <mi>gd</mi> </msub> <mo>;</mo> </mrow></math>
wherein VfrEstimated by equation 1.
From the illustrative examples illustrated in fig. 4 and 6 and the design of the storage capacitor, the following conclusions can be observed: any pixels sharing the same Scan signal line Scan and written with data voltages at different time points (e.g., R, G, B pixels at time point t1、t2And t3Write data voltage) can be compensated for voltage coupling offset using the techniques of the present invention.
FIG. 7 illustrates an embodiment of the present invention, wherein an image display system is described. The image display system comprises a first and a second pixel P1And P2A Scan signal line Scan, and a first and a second data signal lines D1And D2. The first pixel P1Includes a first transistor T1And a first storage capacitor Cst1. The first storage capacitor Cst1Via a first pixel electrode (voltage value is V)1) Coupled to the first transistor T1The source terminal of (1). The second pixel P2Comprises a second transistor T2And a second storage capacitor Cst2. The second storage capacitor Cst2Via a second pixel electrode (voltage value is V)2) Coupled to the second transistor T2The source terminal of (1). The Scan signal line Scan is coupled to the first and second transistors T1And T2A gate terminal for transmitting a scan signal to turn on the first and second transistors T1And T2. The first data signal line D1Coupled to the first transistor T1The drain terminal of. The second data signal line D2Coupled to the second transistor T2The drain terminal of. The embodiment of FIG. 7 will have a Data voltage signal Data input to the first Data signal line D via a demultiplexer 7021Or the second data signal line D2. Under the control of a control signal CS, the Data voltage signal Data is transmitted to the first Data signal line D at a first time1And is transmitted to the second data signal line D at a second time2. The first time is earlier than the second time.
At the second time, the voltage level V of the first pixel electrode1Follows the second pixel level V due to voltage coupling effect2And (6) changing. The first pixel voltage level V1Is called a voltage coupling offset. Stopping to conduct the first and second transistors T1And T2In this case, the voltage variation of the Scan signal line Scan will generate a feedthrough effect on the first pixel electrode, resulting in the first pixel level V1A first feedthrough voltage is displaced. Since the first feedthrough voltage value can pass through the first storage capacitance Cst1In this embodiment, the first storage capacitor C is designed according to the voltage coupling offsetst1The first feedthrough voltage is compensated for the voltage coupling offset.
The voltage variation of the Scan signal line Scan will also generate a feedthrough effect on the second pixel electrode, resulting in the second pixel level V2Displacing a second feed-through voltage. In another embodiment of the present invention, the first storage capacitor Cst1The design of (1) will make the first feedthrough voltage equal to the sum of the second feedthrough voltage and the voltage coupling offset. In another embodiment of the present invention, the first storage capacitor Cst1Will follow the following formula:
<math> <mrow> <msub> <mi>C</mi> <mrow> <mi>st</mi> <mn>1</mn> </mrow> </msub> <mo>=</mo> <mfrac> <mrow> <mi>Δ</mi> <msub> <mi>V</mi> <mi>gate</mi> </msub> <mo>×</mo> <msub> <mi>C</mi> <mrow> <mi>gd</mi> <mn>1</mn> </mrow> </msub> </mrow> <mrow> <mi>Δ</mi> <msub> <mi>V</mi> <mn>1</mn> </msub> <mo>+</mo> <msub> <mi>V</mi> <mrow> <mi>f</mi> <mn>2</mn> </mrow> </msub> </mrow> </mfrac> <mo>-</mo> <msub> <mi>C</mi> <mrow> <mi>lc</mi> <mn>1</mn> </mrow> </msub> <mo>-</mo> <msub> <mi>C</mi> <mrow> <mi>gd</mi> <mn>1</mn> </mrow> </msub> <mo>,</mo> </mrow></math>
wherein, Cgd1Is the first transistor T1C between the gate terminal and the drain terminal of the transistorlc1Is the first pixel P1Liquid crystal capacitance of, Δ VgateIs a voltage change of the Scan signal Scan. Δ V1The voltage coupling offset can be obtained by computer simulation in advance. Vf2Is the second feed-through voltage whose value can be obtained from the second storage capacitor Cst2The second transistor T2Between the gate terminal and the drain terminal ofgd2And the second pixel P2Liquid crystal capacitor Clc2Calculated to obtain
<math> <mrow> <mi>Δ</mi> <msub> <mi>V</mi> <mi>gate</mi> </msub> <mo>×</mo> <mfrac> <msub> <mi>C</mi> <mrow> <mi>gd</mi> <mn>2</mn> </mrow> </msub> <mrow> <msub> <mi>C</mi> <mrow> <mi>st</mi> <mn>2</mn> </mrow> </msub> <mo>+</mo> <msub> <mi>C</mi> <mrow> <mi>lc</mi> <mn>2</mn> </mrow> </msub> <mo>+</mo> <msub> <mi>C</mi> <mrow> <mi>gd</mi> <mn>2</mn> </mrow> </msub> </mrow> </mfrac> <mo>.</mo> </mrow></math>
In one embodiment, the liquid crystal capacitances of all pixels are the same, and the gate-drain parasitic capacitances of the transistors in all pixels are also the same. At this time, the first storage capacitor C designed by the present inventionst1Is smaller than the second storage capacitor Cst2。
The first and second pixels P
1And P
2May correspond to a portion of the pixels in fig. 3. At R
G
B, the first pixel P
1Corresponding to the green pixel G and the second pixel P
2Corresponding to the blue pixel B. In B
G
R, the first pixel P
1Corresponding to the green pixel G and the second pixel P
2Corresponding to the red pixel R.
Fig. 8 shows another embodiment of the present disclosure. Compared with FIG. 7, the image display system of FIG. 8 further includes a third pixel P3And a third data signal line D3. The third pixel P3Comprises a third transistor T3And a third storage capacitor Cst3. The third storage capacitor Cst3Via a third pixel electrode (voltage value is V)3) Coupled to the third transistor T3The source terminal of (1). The third transistor T3Is coupled to the third data signal line D3And its gate terminal is also coupled to the scanning signal line Scan. Under the control of a control signal CS, a Data voltage signal Data is transmitted to the first Data signal line D at a first time1And transmitted to the second data signal line D at a second time2And transmitted to the third data signal line D at a third time3. The first time is earlier than the second time, and the second time is earlier than the first time. In this embodiment, the first storage capacitor C is designed according to a voltage coupling offset of the first pixel electrodest1(so that the first feedthrough voltage can compensate the voltage coupling offset of the first pixel electrode), and the first storage capacitor C is designed according to a voltage coupling offset of the second pixel electrodest2So that the second feedthrough voltage can compensate the voltage coupling offset of the second pixel electrode.
The voltage variation of the Scan signal line Scan will also generate a feedthrough effect on the third pixel electrode, resulting in the third pixel level V3Displacing a third feedthrough voltage. In another embodiment of the present invention, the first storage capacitor Cst1Is designed such that the first feedthrough voltage is equal to the sum of the third feedthrough voltage and the voltage coupling offset of the first pixel electrode; and the second storage capacitor Cst2The second feedthrough voltage is equal to the sum of the third feedthrough voltage and the voltage coupling offset of the second pixel electrode. In another embodiment of the present invention, the first and second storage capacitors Cst1And Cst2Will follow the following formula:
<math> <mrow> <msub> <mi>C</mi> <mrow> <mi>st</mi> <mn>1</mn> </mrow> </msub> <mo>=</mo> <mfrac> <mrow> <mi>Δ</mi> <msub> <mi>V</mi> <mi>gate</mi> </msub> <mo>×</mo> <msub> <mi>C</mi> <mrow> <mi>gd</mi> <mn>1</mn> </mrow> </msub> </mrow> <mrow> <mi>Δ</mi> <msub> <mi>V</mi> <mn>1</mn> </msub> <mo>+</mo> <msub> <mi>V</mi> <mrow> <mi>f</mi> <mn>3</mn> </mrow> </msub> </mrow> </mfrac> <mo>-</mo> <msub> <mi>C</mi> <mrow> <mi>lc</mi> <mn>1</mn> </mrow> </msub> <mo>-</mo> <msub> <mi>C</mi> <mrow> <mi>gd</mi> <mn>1</mn> </mrow> </msub> <mo>,</mo> </mrow></math> and
<math> <mrow> <msub> <mi>C</mi> <mrow> <mi>st</mi> <mn>2</mn> </mrow> </msub> <mo>=</mo> <mfrac> <mrow> <mi>Δ</mi> <msub> <mi>V</mi> <mi>gate</mi> </msub> <mo>×</mo> <msub> <mi>C</mi> <mrow> <mi>gd</mi> <mn>2</mn> </mrow> </msub> </mrow> <mrow> <mi>Δ</mi> <msub> <mi>V</mi> <mn>2</mn> </msub> <mo>+</mo> <msub> <mi>V</mi> <mrow> <mi>f</mi> <mn>3</mn> </mrow> </msub> </mrow> </mfrac> <mo>-</mo> <msub> <mi>C</mi> <mrow> <mi>lc</mi> <mn>2</mn> </mrow> </msub> <mo>-</mo> <msub> <mi>C</mi> <mrow> <mi>gd</mi> <mn>2</mn> </mrow> </msub> </mrow></math>
wherein, Cgd1And Cgd2Respectively the first and the second transistor T1And T2C between the gate terminal and the drain terminal of the transistorlc1And Clc2Are the first and the second pixel P respectively1And P2Liquid crystal capacitance of, Δ VgateIs a voltage change of the Scan signal Scan. Δ V1And Δ V2The first and second pixel electrodesThe voltage coupling offset can be obtained by computer simulation in advance. Vf3Is the third feed-through voltage whose value can be obtained from the third storage capacitor Cst3The third transistor T3Between the gate terminal and the drain terminal ofgd3And the third pixel P3Liquid crystal capacitor Clc3Calculated to obtain
<math> <mrow> <msub> <mi>V</mi> <mrow> <mi>f</mi> <mn>3</mn> </mrow> </msub> <mo>=</mo> <mi>Δ</mi> <msub> <mi>V</mi> <mi>gate</mi> </msub> <mo>×</mo> <mfrac> <msub> <mi>C</mi> <mrow> <mi>gd</mi> <mn>3</mn> </mrow> </msub> <mrow> <msub> <mi>C</mi> <mrow> <mi>st</mi> <mn>3</mn> </mrow> </msub> <mo>+</mo> <msub> <mi>C</mi> <mrow> <mi>lc</mi> <mn>3</mn> </mrow> </msub> <mo>+</mo> <msub> <mi>C</mi> <mrow> <mi>gd</mi> <mn>3</mn> </mrow> </msub> </mrow> </mfrac> <mo>.</mo> </mrow></math>
In one embodiment, the liquid crystal capacitances of all pixels are the same, and the gate-drain parasitic capacitances of the transistors in all pixels are also the same. At this time, the first storage capacitor C designed by the present inventionst1Is smaller than the second storage capacitor Cst2And the second storage capacitor Cst2Is smaller than the third storage capacitor Cst3。
The first, second and third pixels P
1、P
2And P
3May correspond to the pixels in fig. 3. At R
G
B, the first pixel P1 corresponds to the red pixel R and the second pixel P
2Corresponding to the green pixel G and the third pixel P
3Corresponding to the blue pixel B. In B
G
R, the first pixel P
1Corresponding to the blue pixel B and the second pixel P
2Corresponding to the green pixel G and the third pixel P
3Corresponding to the red pixel R.
Fig. 9 illustrates an electronic device 900 that includes a pixel matrix 902, a display panel 904, and an input unit 906. The input unit 906 is coupled to the display panel 904 for receiving an image to be displayed on the display panel 904.
The scope of the invention includes the display panel 904, and the pixels mentioned in the present invention can constitute the pixel matrix 902. The scan signal lines and the data signal lines mentioned in the present invention are part of the display panel 904. In addition, the electronic device 900 is also included in the scope of the present invention. The electronic device 900 may be a mobile phone, a digital camera, a Personal Digital Assistant (PDA), a mobile computer, a desktop computer, a television, an automobile display, or a portable compact disc player.
Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.