CN101315762B

CN101315762B - Image display system

Info

Publication number: CN101315762B
Application number: CN2007101057261A
Authority: CN
Inventors: 陈政欣; 杨琛喻
Original assignee: Chi Mei Optoelectronics Corp
Current assignee: Chi Mei Optoelectronics Corp
Priority date: 2007-05-28
Filing date: 2007-05-28
Publication date: 2012-04-25
Anticipated expiration: 2027-05-28
Also published as: CN101315762A

Abstract

The invention provides an image display system which comprises a first pixel, a second pixel, a scanning signal line, a first data signal line and a second data signal line, wherein, the first pixel includes a first transistor coupled with an electrode of the first pixel and a first storage capacitor; the second pixel includes a second transistor coupled with the electrode of the second pixel and a second storage capacitor; whether the first transistor and the second transistor are conducted or not is determined by the scanning signal line; the first data signal line and the second data signal line respectively write a data voltage signal into the electrodes of the first pixel and the second pixel by the first transistor and the second transistor at a first time and a second time. The image display system of the invention is characterized in that: the first storage capacitor is designed according to voltage coupling offset generated by the electrode of the first pixel at the second time, so as to lead the first feed-through voltage of the electrode of the first pixel to compensate the voltage coupling offset.

Description

Image display system

Technical Field

The invention relates to an image display system, which solves the problem of color cast of the traditional image display system.

Background

FIG. 1 illustrates a conventional panel structure 100 of a display, which includes a red pixel R, a green pixel G, and a blue pixel B, each formed by a transistor T and a storage capacitor C_stAnd (4) forming. A Scan signal line Scan is coupled to the gate terminal of the transistor T for transmitting a Scan signal to turn on the transistor T. The drain terminals of the transistors T of the pixels R, G and B are respectively coupled to the data signal line D_r、D_gAnd D_b。

To reduce the number of pins of the panel chip, the panel 100 further includes a demultiplexer 102, so that the pixels R, G and B share a Data voltage source Data. The demultiplexer 102 comprises three switches SW_r、SW_gAnd SW_bRespectively by a pulse signal CKH_r、CKH_gAnd CKH_bAnd (5) controlling. FIG. 2 shows a driving waveform of the panel 100 and the corresponding pixel voltage V_r、V_gAnd V_b. In this illustrative example, the panel 100 employs a row inversion technique (row inversion). While the Scan signal Scan turns on the transistors T of the pixels R, G and B, the Data voltage source Data will transmit the Data voltages of the red, green, and blue pixels R, G and B in time sequence. The pulse signal CKH is used to transmit the Data voltage from the Data voltage source to the corresponding pixel_r、CKH_gAnd CKH_bSequentially activating the switches SW corresponding to the Data voltage sources Data_r、SW_gAnd SW_b. Pixel voltage V for observing red, green and blue pixels_r、V_g、V_bIt can be found that: the signal from the Data voltage source Data will be at the time point t₁Writing the red pixel R at a time point t₂Writing the green pixel G and at a time point t₃The blue pixel B is written. Since the pixel electrodes of the pixels R, G and B are voltage-coupled to each other, the pixel voltage V of the pixels R, G and B_r、V_g、V_bWill shift with each other. As shown, at a time point t₂Green pixel voltage V_gWill make the red pixel voltage V_rLifting (202) therewith; at a time point t₃Blue pixel voltage V_bWill make the green pixel voltage V_gThen, the voltage of the red pixel is increased (204) and the voltage V of the red pixel is further increased_rAnd then lifted (206). In this illustrative example, the pixel voltage V of the red pixel_rWill be subjected to the green and blue pixel voltages V_g、V_bThe most serious is its excursion.

In the example of fig. 2, the Data voltage source Data provides the same Data voltage to the pixels R, G and B. The panel 100 employs an nw (normal white) technique-transparent in the absence of applied voltage. In the NW panel, the larger the voltage difference between the pixel electrode and the common electrode (having Vcom), the darker the pixel, so the red pixel R with severe offset will be the darkest, and the blue pixel B without voltage coupling offset will be the brightest. The panel 100 will be bluish. If the panel 100 employs nb (normal black) technology, which is opaque when no voltage is applied and the pixel is brighter when the voltage difference between the pixel electrode and the common electrode is larger, the panel 100 will be reddish.

Disclosure of Invention

The present invention provides an image display system, which can not only reduce the number of pins of the chip by sharing the Data voltage source Data, but also eliminate the color shift problem of the panel 100, as in the panel 100.

Different from the conventional panel 100, all pixels use the same storage capacitor C_stThe present invention designs each pixel according to the voltage coupling offset generated by each pixel electrode due to the voltage coupling effectA dedicated storage capacitor.

As shown in FIG. 2, the Scan signal Scan will be at the time point t₄The transistors T of the pixels R, G and B are turned off. A voltage variation Δ V of the Scan signal Scan_gateWill be respectively applied to the pixel voltages V_r、V_gAnd V_bGenerating a feed-through voltage (V)_fr、V_fgAnd V_fb. Since the feedthrough voltage is related to the storage capacitance of the pixel. The invention designs a dedicated storage capacitor for each pixel by adjusting the feed-through voltage V_fr、V_fgAnd V_fbCompensating the pixel voltage V_r、V_g、V_bVoltage coupling offsets (202, 204, and 206 of fig. 2) due to voltage coupling effects.

In order to make the aforementioned and other objects, features, and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 illustrates a panel structure of a conventional display;

FIG. 2 shows a driving waveform of FIG. 1 and a corresponding pixel voltage V_r、V_gAnd V_b；

FIG. 3 is a schematic diagram of a panel structure of an image display system according to the present disclosure;

FIG. 4 shows a driving waveform (R) of FIG. 3

Figure S071A5726120070601D00002111931QIETU

G

Figure 2007101057261100002S071A5726120070601D00002111931QIETU

B) And a corresponding pixel voltage V_r、V_gAnd V_b；

FIG. 5 is a diagram of a panel structure shown in FIG. 3 with the addition of the liquid crystal capacitance of the pixel and the parasitic capacitance of the transistors in the pixel;

FIG. 6 shows a driving waveform (B) of FIG. 3

G

R) and a corresponding pixel voltage V_r、V_gAnd V_b；

FIG. 7 shows an embodiment of the present disclosure;

FIG. 8 is another embodiment of the present disclosure; and

fig. 9 shows an apparatus to which the present invention is applied.

Description of the figures

100-traditional panel; 102-a demultiplexer;

202. 204, 206-voltage coupling offset;

300 to the panel of the scheme;

702-a demultiplexer;

900 to an electronic device; 902-pixel matrix;

904-display panel; 906-an input unit;

b-blue pixels;

CKH_r、CKH_gand CKH_b-a frequency signal;

C_gd-gate-drain parasitic capacitance of transistors within a pixel;

C_lc-a liquid crystal capacitance of a pixel; CS control signal of demultiplexer;

C_st-a storage capacitor;

C_str、C_stgand C_stb-storage capacitors for red, green and blue pixels;

C_st1、C_st2and C_st3-storage capacitors of the first, second and third pixels;

Data-Data voltage source;

D₁、D₂and D₃-a data signal line;

D_r、D_gand D_b-a data signal line;

g to green pixels;

P₁、P₂and P₃-a pixel;

r-red pixels;

scan-scanning signal lines; SW_r、SW_gAnd SW_b-a switch;

t-transistor; t is₁、T₂And T₃-a transistor;

t₁-t₄-a point in time;

V_com-voltage of the shared electrode;

V_fr、V_fgand V_fbFeed-through voltages for red, green, and blue pixels;

V_r、V_gand V_bRed, green, blue pixel voltages;

V₁、V₂and V₃-first, second and third pixel voltages;

Δ V-the difference between the data voltage written into the pixel and the voltage of the common electrode;

ΔV_gate-voltage variation of the Scan signal Scan; and

ΔV_r、ΔV_gand Δ V_b-voltage coupling offsets for red, green and blue pixels.

Detailed Description

Fig. 3 is a panel structure 300 of an image display system according to the present application, which includes a red pixel R, a green pixel G, and a blue pixel B. The red pixel R includes a red pixel electrode coupled to a voltage V_r) A transistor T and a storage capacitor C_str. The green pixel G includes a green pixel electrode coupled to a voltage V_g) A transistor T and a storage capacitor C_stg. The blue pixel B includes a blue pixel electrode coupled to a voltage V_b) A transistor T and a storage capacitor C_stb. A Scan signal line Scan is coupled to the gate terminal of the transistor T for transmitting a Scan signal to turn on the transistor T. The drain terminals of the transistors T of the pixels R, G and B are respectively coupled to the data signal line D_r、D_gAnd D_b. To reduce the number of pins of the panel chip, the panel 300 also includes a demultiplexer 102, as in the conventional panel 100, which allows the pixels R, G and B to share a Data voltage source Data. The demultiplexer 102 comprises three switches SW_r、SW_gAnd SW_bRespectively by a pulse signal CKH_r、CKH_gAnd CKH_bAnd (4) controlling.

Compared with FIG. 1, the panel 300 is different from the conventional panel 100 in that each pixel uses the same storage capacitor C_stThe panel 300 must have a dedicated storage capacitor C designed for each pixel R, G and B_str、C_stgAnd C_stb。

The driving waveforms and the voltage values V of the pixel electrodes shown in FIG. 4 are as follows_r、V_g、V_bIllustrating the storage capacitor C_str、C_stgAnd C_stbDesign summary ofCan be read. The pixels R, G and B are driven in the order of R

G

B. The signal from the Data voltage source Data will be at the time point t₁Writing the red pixel R at a time point t₂Writing the green pixel G and at a time point t₃The blue pixel B is written. This example assumes that the gamma setting parameters (gamma setting) are the same for each pixel and that the pixels R, G, B are driven with the same gray scale values. The pixel voltage V_rAt a time point t₁～t₂The locked voltage value will be equal to the pixel voltage V_gAt a time point t₂～t₃The locked voltage value will also be equal to the pixel voltage V_bAt a time point t₃～t₄The locked voltage value, the pixel voltage and a common level V_comThe difference is Δ V. The pixel electrodes are voltage-coupled to each other, the pixel voltage V being as described in the prior art_rWill follow the pixel voltage V_gAnd V_bVariation, there is a voltage coupling offset Δ V_r(ii) a And the pixel voltage V_gWill follow the pixel voltage V_bVariation, there is a voltage coupling offset Δ V_g。

Analyzing the circuit structure of the pixels R, G, B shown in FIG. 3, FIG. 5 also considers the liquid crystal capacitance C of each pixel_lcAnd the parasitic capacitance C of the grid and the drain of the transistor T in the pixel_gd. When the Scan signal Scan turns off the transistor T, the voltage of the Scan signal Scan changes by Δ V_gateWill let the pixel voltage V of the pixel R, G, B_r、V_g、V_bThen, the voltage is decreased, and the decreased amplitude is called feed-through voltage (feedthru). As shown in fig. 4, at a time point t₄The pixel voltage V_r、V_g、V_bWill respond to the voltage change DeltaV_gateRespectively generate a feed-through voltage V_fr、V_fgAnd V_fb. Observe the circuit of FIG. 5, canObtaining the feed-through voltage value V_fr、V_fgAnd V_fbComprises the following steps:

(formula 1)

And (formula 2)

(formula 3)

The invention will be realized by designing the storage capacitor C_str、C_stgAnd C_stbAdjusting the feed-through voltage V_fr、V_fgAnd V_fbTo compensate for the voltage coupling offset Δ V_rAnd Δ V_gAnd the color cast phenomenon of the screen is eliminated.

Referring to the illustrative example of FIG. 4, to eliminate the color shift of the screen, the feed-through voltage V is applied_fr、V_fgAnd V_fbThe following equation must be satisfied:

ΔV+ΔV_r-V_fr＝ΔV+ΔV_g-V_fg＝ΔV-V_fb。

therefore V_fr＝ΔV_r+V_fb(ii) a And V_fg＝ΔV_g+V_fb. Combining the

above equations

1 and 2, the storage capacitance C of the blue pixel B_stbThe voltage coupling offset Δ V has been set and has been simulated by a computer_rAnd Δ V_gOn the premise of the above-mentioned storage capacitor C_strAnd C_stgThe design principle of (1) is as follows:

and

wherein V_fbEstimated via equation 3.

However, if the pixel R is described above

G

B are different in driving sequence, and the storage capacitor C_str、C_stgAnd C_stbThe design principle of (a) must be adjusted accordingly. The driving sequence of the pixels R, G, B in FIG. 6 is B

G

And R is shown in the specification. The signal from the Data voltage source Data will be at the time point t₁Writing the blue pixel B at a time point t₂Write the green pixel G and at a time t₃The red pixel R is written. In order to eliminate screen color cast, the feed-through voltage V_fr、V_fgAnd V_fbThe following equation must be satisfied:

ΔV+ΔV_b-V_fb＝ΔV+ΔV_g-V_fg＝ΔV-V_fr。

therefore V_fb＝ΔV_r+V_fr(ii) a And V_fg＝ΔV_g+V_fr. Combining the

above equations

2 and 3, the storage capacitance C of the red pixel R_strThe voltage coupling offset Δ V has been set and has been simulated by a computer_bAnd Δ V_gOn the premise of the above-mentioned storage capacitor C_stbAnd C_stgThe design principle of (1) is as follows:

and

wherein V_frEstimated by equation 1.

From the illustrative examples illustrated in fig. 4 and 6 and the design of the storage capacitor, the following conclusions can be observed: any pixels sharing the same Scan signal line Scan and written with data voltages at different time points (e.g., R, G, B pixels at time point t₁、t₂And t₃Write data voltage) can be compensated for voltage coupling offset using the techniques of the present invention.

FIG. 7 illustrates an embodiment of the present invention, wherein an image display system is described. The image display system comprises a first and a second pixel P₁And P₂A Scan signal line Scan, and a first and a second data signal lines D₁And D₂. The first pixel P₁Includes a first transistor T₁And a first storage capacitor C_st1. The first storage capacitor C_st1Via a first pixel electrode (voltage value is V)₁) Coupled to the first transistor T₁The source terminal of (1). The second pixel P₂Comprises a second transistor T₂And a second storage capacitor C_st2. The second storage capacitor C_st2Via a second pixel electrode (voltage value is V)₂) Coupled to the second transistor T₂The source terminal of (1). The Scan signal line Scan is coupled to the first and second transistors T₁And T₂A gate terminal for transmitting a scan signal to turn on the first and second transistors T₁And T₂. The first data signal line D₁Coupled to the first transistor T₁The drain terminal of. The second data signal line D₂Coupled to the second transistor T₂The drain terminal of. The embodiment of FIG. 7 will have a Data voltage signal Data input to the first Data signal line D via a demultiplexer 702₁Or the second data signal line D₂. Under the control of a control signal CS, the Data voltage signal Data is transmitted to the first Data signal line D at a first time₁And is transmitted to the second data signal line D at a second time₂. The first time is earlier than the second time.

At the second time, the voltage level V of the first pixel electrode₁Follows the second pixel level V due to voltage coupling effect₂And (6) changing. The first pixel voltage level V₁Is called a voltage coupling offset. Stopping to conduct the first and second transistors T₁And T₂In this case, the voltage variation of the Scan signal line Scan will generate a feedthrough effect on the first pixel electrode, resulting in the first pixel level V₁A first feedthrough voltage is displaced. Since the first feedthrough voltage value can pass through the first storage capacitance C_st1In this embodiment, the first storage capacitor C is designed according to the voltage coupling offset_st1The first feedthrough voltage is compensated for the voltage coupling offset.

The voltage variation of the Scan signal line Scan will also generate a feedthrough effect on the second pixel electrode, resulting in the second pixel level V₂Displacing a second feed-through voltage. In another embodiment of the present invention, the first storage capacitor C_st1The design of (1) will make the first feedthrough voltage equal to the sum of the second feedthrough voltage and the voltage coupling offset. In another embodiment of the present invention, the first storage capacitor C_st1Will follow the following formula:

wherein, C_gd1Is the first transistor T₁C between the gate terminal and the drain terminal of the transistor_lc1Is the first pixel P₁Liquid crystal capacitance of, Δ V_gateIs a voltage change of the Scan signal Scan. Δ V₁The voltage coupling offset can be obtained by computer simulation in advance. V_f2Is the second feed-through voltage whose value can be obtained from the second storage capacitor C_st2The second transistor T₂Between the gate terminal and the drain terminal of_gd2And the second pixel P₂Liquid crystal capacitor C_lc2Calculated to obtain

In one embodiment, the liquid crystal capacitances of all pixels are the same, and the gate-drain parasitic capacitances of the transistors in all pixels are also the same. At this time, the first storage capacitor C designed by the present invention_st1Is smaller than the second storage capacitor C_st2。

The first and second pixels P₁And P₂May correspond to a portion of the pixels in fig. 3. At R

G

B, the first pixel P₁Corresponding to the green pixel G and the second pixel P₂Corresponding to the blue pixel B. In B

G

R, the first pixel P₁Corresponding to the green pixel G and the second pixel P₂Corresponding to the red pixel R.

Fig. 8 shows another embodiment of the present disclosure. Compared with FIG. 7, the image display system of FIG. 8 further includes a third pixel P₃And a third data signal line D₃. The third pixel P₃Comprises a third transistor T₃And a third storage capacitor C_st3. The third storage capacitor C_st3Via a third pixel electrode (voltage value is V)₃) Coupled to the third transistor T₃The source terminal of (1). The third transistor T₃Is coupled to the third data signal line D₃And its gate terminal is also coupled to the scanning signal line Scan. Under the control of a control signal CS, a Data voltage signal Data is transmitted to the first Data signal line D at a first time₁And transmitted to the second data signal line D at a second time₂And transmitted to the third data signal line D at a third time₃. The first time is earlier than the second time, and the second time is earlier than the first time. In this embodiment, the first storage capacitor C is designed according to a voltage coupling offset of the first pixel electrode_st1(so that the first feedthrough voltage can compensate the voltage coupling offset of the first pixel electrode), and the first storage capacitor C is designed according to a voltage coupling offset of the second pixel electrode_st2So that the second feedthrough voltage can compensate the voltage coupling offset of the second pixel electrode.

The voltage variation of the Scan signal line Scan will also generate a feedthrough effect on the third pixel electrode, resulting in the third pixel level V₃Displacing a third feedthrough voltage. In another embodiment of the present invention, the first storage capacitor C_st1Is designed such that the first feedthrough voltage is equal to the sum of the third feedthrough voltage and the voltage coupling offset of the first pixel electrode; and the second storage capacitor C_st2The second feedthrough voltage is equal to the sum of the third feedthrough voltage and the voltage coupling offset of the second pixel electrode. In another embodiment of the present invention, the first and second storage capacitors C_st1And C_st2Will follow the following formula:

and

wherein, C_gd1And C_gd2Respectively the first and the second transistor T₁And T₂C between the gate terminal and the drain terminal of the transistor_lc1And C_lc2Are the first and the second pixel P respectively₁And P₂Liquid crystal capacitance of, Δ V_gateIs a voltage change of the Scan signal Scan. Δ V₁And Δ V₂The first and second pixel electrodesThe voltage coupling offset can be obtained by computer simulation in advance. V_f3Is the third feed-through voltage whose value can be obtained from the third storage capacitor C_st3The third transistor T₃Between the gate terminal and the drain terminal of_gd3And the third pixel P₃Liquid crystal capacitor C_lc3Calculated to obtain

In one embodiment, the liquid crystal capacitances of all pixels are the same, and the gate-drain parasitic capacitances of the transistors in all pixels are also the same. At this time, the first storage capacitor C designed by the present invention_st1Is smaller than the second storage capacitor C_st2And the second storage capacitor C_st2Is smaller than the third storage capacitor C_st3。

The first, second and third pixels P₁、P₂And P₃May correspond to the pixels in fig. 3. At R

G

B, the first pixel P1 corresponds to the red pixel R and the second pixel P₂Corresponding to the green pixel G and the third pixel P₃Corresponding to the blue pixel B. In B

G

R, the first pixel P₁Corresponding to the blue pixel B and the second pixel P₂Corresponding to the green pixel G and the third pixel P₃Corresponding to the red pixel R.

Fig. 9 illustrates an electronic device 900 that includes a pixel matrix 902, a display panel 904, and an input unit 906. The input unit 906 is coupled to the display panel 904 for receiving an image to be displayed on the display panel 904.

The scope of the invention includes the display panel 904, and the pixels mentioned in the present invention can constitute the pixel matrix 902. The scan signal lines and the data signal lines mentioned in the present invention are part of the display panel 904. In addition, the electronic device 900 is also included in the scope of the present invention. The electronic device 900 may be a mobile phone, a digital camera, a Personal Digital Assistant (PDA), a mobile computer, a desktop computer, a television, an automobile display, or a portable compact disc player.

Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. An image display system, comprising:

a first pixel including a first transistor and a first storage capacitor coupled to a source terminal of the first transistor via a first pixel electrode;

a second pixel including a second transistor and a second storage capacitor coupled to the source terminal of the second transistor via a second pixel electrode;

a scan signal line coupled to the gate terminals of the first and second transistors for transmitting a scan signal to turn on the first and second transistors;

a first data signal line coupled to the drain terminal of the first transistor for receiving a data voltage signal at a first time; and

a second data signal line coupled to the drain terminal of the second transistor for receiving the data voltage signal at a second time;

wherein the first time is earlier than the second time,

wherein the first storage capacitor is designed according to a voltage coupling offset of the first pixel electrode, so that a first feed-through voltage can compensate the voltage coupling offset,

wherein the first feed-through voltage is the voltage variation of the first pixel electrode along with the scanning signal,

wherein the first storage capacitor is designed to follow the following equation:

wherein,

C_st1is the capacitance value of the first storage capacitor,

C_gd1is the parasitic capacitance between the gate terminal and the drain terminal of the first transistor,

C_lc1is the liquid crystal capacitance of the first pixel,

ΔV_gatefor the voltage change of the scan signal,

ΔV₁coupling an offset to the voltage, and

V_f2for the purpose of this second feed-through voltage,

the voltage coupling offset is simulated by a computer.

2. The image display system of claim 1, wherein a voltage generated by the second pixel electrode in response to the scan signal is changed to a second feedthrough voltage.

3. The image display system of claim 2, wherein the first storage capacitor is configured such that the first feedthrough voltage is equal to the sum of the second feedthrough voltage and the voltage coupling offset.

4. The image display system of claim 1, wherein the second feedthrough voltage is derived by the following equation:

wherein,

C_st2is the capacitance value of the second storage capacitor,

C_gd2is a parasitic capacitance between the gate terminal and the drain terminal of the second transistor, an

C_lc2Is the liquid crystal capacitance of the second pixel.

5. The image display system of claim 1, wherein the first storage capacitor is smaller than the second storage capacitor.

6. The image display system of claim 1, further comprising a display panel including the first and second pixels, the scan signal line, and the first and second data signal lines.

7. The image display system of claim 6, further comprising an electronic device, comprising:

the display panel described above; and

an input unit coupled to the two panels of the display for receiving the image to be displayed by the display panel.

8. The image display system of claim 7, wherein the electronic device is a mobile phone, a digital camera, a personal digital assistant, a mobile computer, a desktop computer, a television, an automobile display, or a portable compact disc player.