CN101312174B - Line component - Google Patents
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- CN101312174B CN101312174B CN2007101075804A CN200710107580A CN101312174B CN 101312174 B CN101312174 B CN 101312174B CN 2007101075804 A CN2007101075804 A CN 2007101075804A CN 200710107580 A CN200710107580 A CN 200710107580A CN 101312174 B CN101312174 B CN 101312174B
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- Prior art keywords
- layer
- connection pad
- semiconductor
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- 239000010410 layer Substances 0.000 claims abstract description 333
- 239000004065 semiconductor Substances 0.000 claims abstract description 221
- 239000011241 protective layer Substances 0.000 claims abstract description 94
- 239000000758 substrate Substances 0.000 claims abstract description 63
- 229910052751 metal Inorganic materials 0.000 claims description 233
- 239000002184 metal Substances 0.000 claims description 233
- 239000000463 material Substances 0.000 claims description 101
- 229920000642 polymer Polymers 0.000 claims description 77
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 73
- 229910052802 copper Inorganic materials 0.000 claims description 64
- 239000010949 copper Substances 0.000 claims description 64
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 63
- 230000004888 barrier function Effects 0.000 claims description 56
- 239000013047 polymeric layer Substances 0.000 claims description 48
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 38
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 38
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 36
- 229910052737 gold Inorganic materials 0.000 claims description 36
- 239000010931 gold Substances 0.000 claims description 36
- 229910052759 nickel Inorganic materials 0.000 claims description 36
- 229910052710 silicon Inorganic materials 0.000 claims description 23
- 239000010703 silicon Substances 0.000 claims description 23
- 229910052782 aluminium Inorganic materials 0.000 claims description 22
- 239000004411 aluminium Substances 0.000 claims description 21
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 21
- 229910052763 palladium Inorganic materials 0.000 claims description 19
- 229910052697 platinum Inorganic materials 0.000 claims description 19
- 238000003475 lamination Methods 0.000 claims description 17
- 239000011521 glass Substances 0.000 claims description 14
- 239000011248 coating agent Substances 0.000 claims description 10
- 238000000576 coating method Methods 0.000 claims description 10
- 239000004642 Polyimide Substances 0.000 claims description 9
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 9
- 229920001721 polyimide Polymers 0.000 claims description 9
- 229910052709 silver Inorganic materials 0.000 claims description 9
- 239000004332 silver Substances 0.000 claims description 9
- 239000010936 titanium Substances 0.000 claims description 9
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 239000000203 mixture Substances 0.000 claims description 6
- 239000000919 ceramic Substances 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims description 4
- UMVBXBACMIOFDO-UHFFFAOYSA-N [N].[Si] Chemical compound [N].[Si] UMVBXBACMIOFDO-UHFFFAOYSA-N 0.000 claims 2
- OBNDGIHQAIXEAO-UHFFFAOYSA-N [O].[Si] Chemical compound [O].[Si] OBNDGIHQAIXEAO-UHFFFAOYSA-N 0.000 claims 2
- 239000004020 conductor Substances 0.000 abstract description 5
- 238000000034 method Methods 0.000 description 122
- 229920002120 photoresistant polymer Polymers 0.000 description 78
- 238000012545 processing Methods 0.000 description 59
- 230000008569 process Effects 0.000 description 43
- 238000000059 patterning Methods 0.000 description 36
- 238000011161 development Methods 0.000 description 20
- 238000004519 manufacturing process Methods 0.000 description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 19
- 239000002131 composite material Substances 0.000 description 17
- 238000005229 chemical vapour deposition Methods 0.000 description 16
- 238000005240 physical vapour deposition Methods 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 239000000428 dust Substances 0.000 description 14
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 12
- 238000007747 plating Methods 0.000 description 12
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 11
- 238000009713 electroplating Methods 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 11
- 239000002245 particle Substances 0.000 description 11
- 229910052702 rhenium Inorganic materials 0.000 description 11
- WUAPFZMCVAUBPE-UHFFFAOYSA-N rhenium atom Chemical compound [Re] WUAPFZMCVAUBPE-UHFFFAOYSA-N 0.000 description 11
- 229910052703 rhodium Inorganic materials 0.000 description 11
- 239000010948 rhodium Substances 0.000 description 11
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 description 11
- 229910052707 ruthenium Inorganic materials 0.000 description 11
- 239000000853 adhesive Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 10
- 229910044991 metal oxide Inorganic materials 0.000 description 10
- 150000004706 metal oxides Chemical class 0.000 description 10
- 239000003822 epoxy resin Substances 0.000 description 9
- 229920000647 polyepoxide Polymers 0.000 description 9
- 239000002002 slurry Substances 0.000 description 9
- 238000007772 electroless plating Methods 0.000 description 8
- 238000005538 encapsulation Methods 0.000 description 8
- 238000005520 cutting process Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- 239000002356 single layer Substances 0.000 description 7
- 239000011135 tin Substances 0.000 description 7
- 229910000906 Bronze Inorganic materials 0.000 description 6
- 239000004593 Epoxy Substances 0.000 description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000010974 bronze Substances 0.000 description 6
- 230000000295 complement effect Effects 0.000 description 6
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 6
- 238000003384 imaging method Methods 0.000 description 6
- 229920000052 poly(p-xylylene) Polymers 0.000 description 6
- 229920001296 polysiloxane Polymers 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 5
- 208000034189 Sclerosis Diseases 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 5
- 230000008859 change Effects 0.000 description 5
- 239000011651 chromium Substances 0.000 description 5
- 230000006378 damage Effects 0.000 description 5
- 230000005611 electricity Effects 0.000 description 5
- 239000011737 fluorine Substances 0.000 description 5
- 229910052731 fluorine Inorganic materials 0.000 description 5
- 238000007731 hot pressing Methods 0.000 description 5
- 230000003287 optical effect Effects 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229910052715 tantalum Inorganic materials 0.000 description 5
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 5
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 4
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 238000010030 laminating Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 238000007639 printing Methods 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 239000010432 diamond Substances 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 229920001971 elastomer Polymers 0.000 description 3
- 239000000806 elastomer Substances 0.000 description 3
- 239000013536 elastomeric material Substances 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000003973 irrigation Methods 0.000 description 3
- 230000002262 irrigation Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 150000001398 aluminium Chemical class 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 229910010272 inorganic material Inorganic materials 0.000 description 2
- 239000011147 inorganic material Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- JZMKGUPOUQRDMD-UHFFFAOYSA-N oxygen(2-) tetraethyl silicate titanium(4+) Chemical compound [O--].[O--].[Ti+4].CCO[Si](OCC)(OCC)OCC JZMKGUPOUQRDMD-UHFFFAOYSA-N 0.000 description 2
- 238000011536 re-plating Methods 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- -1 sodium (sodium) ion Chemical class 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- 229910052723 transition metal Inorganic materials 0.000 description 2
- 150000003624 transition metals Chemical class 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical compound [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 description 1
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910001074 Lay pewter Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 150000001298 alcohols Chemical class 0.000 description 1
- VRAIHTAYLFXSJJ-UHFFFAOYSA-N alumane Chemical compound [AlH3].[AlH3] VRAIHTAYLFXSJJ-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- AIOWANYIHSOXQY-UHFFFAOYSA-N cobalt silicon Chemical compound [Si].[Co] AIOWANYIHSOXQY-UHFFFAOYSA-N 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 239000003049 inorganic solvent Substances 0.000 description 1
- 229910001867 inorganic solvent Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011630 iodine Substances 0.000 description 1
- 229910052740 iodine Inorganic materials 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 230000035800 maturation Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 125000004469 siloxy group Chemical group [SiH3]O* 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- GPPXJZIENCGNKB-UHFFFAOYSA-N vanadium Chemical compound [V]#[V] GPPXJZIENCGNKB-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
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- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H01L2924/13—Discrete devices, e.g. 3 terminal devices
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- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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Abstract
The invention relates to a circuitry component comprising a first semiconductor substrate having at least one first metallic pad, a first protective layer, a first metallic layer, a second semiconductor substrate, a first wiring conductor and a second wiring conductor, wherein the first projective layer located on the first semiconductor substrate has at least one first opening exposing the first metallic pad, the first metallic layer located on the first projective layer is connected with the first metallic pad via the first opening and has a first wiring pad and a second wiring pad, the second semiconductor substrate located on the first semiconductor substrate exposes at least one lateral edge, the first wiring pad and the second wiring pad of the first semiconductor substrate and has at least one second opening exposing a second metallic pad, the first wiring conductor located on the first wiring pad is connected with a first external circuit, and the second wiring conductor located on the second wiring pad is connected to the second metallic pad of the second semiconductor substrate.
Description
Technical field
The present invention relates to a kind of circuit assembly structure, particularly about a kind of chip structure that can on chip, carry out doubles line processing procedure.
Background technology
In recent years, along with the continuous maturation and the development of manufacture of semiconductor technology, various dynamical electronic products are constantly weeded out the old and bring forth the new, and integrated circuit (Integrated Circuit, IC) integration of assembly (integration) also improves constantly.In the encapsulation procedure of integrated circuit package, considerable role is being played the part of in integrated circuit encapsulation (IC packaging), and integrated circuit encapsulation kenel can roughly be divided into routing bond package (Wire BondingPackage, WB), automatic bond package (Tape Automatic Bonding is with in subsides, TAB) with chip bonding (FlipChip, pattern such as FC), and every kind of packing forms all has its particularity and application.
Yet when the size of integrated circuit further during miniaturization, metal connecting structure on the integrated circuit is connected to other circuit or during system, aspect circuit performance, will can become disadvantageous impact gradually, when especially the parasitic capacitance of metal connecting structure and resistance increase, will seriously reduce the chip operation performance, increase with resistance such as parasitic capacitance (parasitic capacitance), will mean the decline of chip usefulness when the metal interconnect.Wherein, the most worth concern is along the pressure drop (voltage drop) between power bus (power buses) and the earth bus (ground buses), and the resistance capacitance in crucial signal path postpones (RC delay).In order to reduce resistance,, will cause the parasitic capacitance of these width metal lines to raise if use width metal lines.
In view of this, The present invention be directed to above-mentioned problem, propose a kind of processing procedure and structure thereof of circuit pack, effectively overcome the puzzlement of prior art.
Summary of the invention
Main purpose of the present invention is that a kind of circuit pack is being provided, and utilizes the mode of reshuffling circuit (RDL), makes chip overlapping with maximum overlapping area when folded establishing, and then overall volume is dwindled.
Another object of the present invention is that a kind of circuit pack is being provided, and utilizes the polymer projection to replace existing metal coupling, significantly to reduce material cost.
For achieving the above object, the technical solution used in the present invention comprises:
A kind of circuit pack is characterized in that, comprising: the one first semiconductor-based end,, the described first semiconductor-based end, had at least one first metallic pad; One first protective layer is positioned at at described first the semiconductor-based end, and described first protective layer has at least one opening and exposes described first metallic pad; One the first metal layer is positioned on described first protective layer and is electrically connected to described first metallic pad, and described the first metal layer has one first routing connection pad and one second routing connection pad; One first routing lead is positioned on the described first routing connection pad and is connected to one first external circuitry; And one second routing lead, be positioned on the described second routing connection pad and be connected to one second external circuitry.
For achieving the above object, the technical solution used in the present invention comprises:
A kind of circuit pack, it is characterized in that, comprise: the one first semiconductor-based end, one first protective layer is positioned at at described first the semiconductor-based end, at least one first opening of described first protective layer exposes one first connection pad at the described first semiconductor-based end, and a first metal layer is positioned on described first protective layer and via described first opening and connects described first connection pad, and described the first metal layer comprises several first routing connection pads; The one second semiconductor-based end, be positioned at at described first the semiconductor-based end and expose at least one side in the described first semiconductor-based end and the described first routing connection pad, and one second protective layer is positioned at at described second the semiconductor-based end, at least one second opening of described second protective layer exposes one second connection pad at the described second semiconductor-based end, and one second metal level is positioned on described second protective layer and via described second opening and connects described second connection pad, and described second metal level comprises several second routing connection pads; One the 3rd semiconductor-based end, be positioned at at described second the semiconductor-based end and expose at least one side in the described second semiconductor-based end and the described second routing connection pad, and one the 3rd protective layer is positioned at at the described the 3rd the semiconductor-based end, at least one the 3rd opening of described the 3rd protective layer exposes one the 3rd connection pad at described the 3rd semiconductor-based end, and one the 3rd metal level is positioned on described the 3rd protective layer and via described the 3rd opening and connects described the 3rd connection pad, and described the 3rd metal level comprises several the 3rd routing connection pads; One the 4th semiconductor-based end, be positioned at at the described the 3rd the semiconductor-based end and expose at least one side in the described the 3rd semiconductor-based end and described the 3rd routing connection pad, and one the 4th protective layer is positioned at at the described the 4th the semiconductor-based end, at least one the 4th opening of described the 4th protective layer exposes one the 4th connection pad at described the 4th semiconductor-based end, and one the 4th metal level is positioned on described the 4th protective layer and via described the 4th opening and connects described the 4th connection pad, and described the 4th metal level comprises several the 4th routing connection pads; Several routing leads, be positioned on the described first routing connection pad, the described second routing connection pad, described the 3rd routing connection pad and described the 4th routing connection pad, described first routing connection pad and the described second routing connection pad, the described second routing connection pad and described the 3rd routing connection pad, described the 3rd routing connection pad and described the 4th routing connection pad are interconnected via described routing lead; And an external circuitry, be connected to the described first routing connection pad, the described second routing connection pad, described the 3rd routing connection pad and described the 4th routing connection pad at least on one of them via described routing lead.
Compared with prior art, the beneficial effect that the present invention has is: not only overall volume is dwindled, and reduces material cost.
Description of drawings
The schematic diagram of Fig. 1 a to Fig. 1 d thin on-line composition and protective layer for the present invention forms;
Fig. 2 a to Fig. 2 p is the schematic diagram of the 1st execution mode of first embodiment of the invention;
Fig. 3 a to Fig. 3 m is the schematic diagram of the 2nd execution mode of first embodiment of the invention;
Fig. 4 a to Fig. 4 c is the schematic diagram of the 3rd execution mode of first embodiment of the invention;
Fig. 5 a to Fig. 5 k is the schematic diagram of the 1st execution mode of second embodiment of the invention;
Fig. 6 a to Fig. 6 j is the schematic diagram of the 2nd execution mode of second embodiment of the invention;
Fig. 7 a to Fig. 7 b is the schematic diagram of the 3rd execution mode of second embodiment of the invention;
Fig. 8 a to Fig. 8 k is the schematic diagram of the 4th execution mode of second embodiment of the invention;
Fig. 9 a to Fig. 9 g is the schematic diagram of the 5th execution mode of second embodiment of the invention;
Figure 10 a to Figure 10 h is the schematic diagram of the 6th execution mode of second embodiment of the invention.
Description of reference numerals: 10-substrate; The 12-component layer; The 14-MOS (metal-oxide-semiconductor) transistor; The 16-source electrode; The 18-drain; The 20-gate; 22-fine rule line structure; The thin line layer of 24-; 26-fine rule road dielectric layer; The 28-opening; The 30-conductive plug; The 32-connection pad; The 34-protective layer; The 36-opening; 38-sticks together/barrier layer; The 40-Seed Layer; The 42-photoresist layer; 42a-photoresist layer opening; The 44-metal level; 44a-routing connection pad; 44b-routing connection pad; The 46-polymeric layer; The 46a-opening; The 48-semiconductor chip; The 49-integrated circuit; 48a-first semiconductor chip; 48b-second semiconductor chip; The 50-adhesive agent; 52-first external circuitry; 52a-connects connection pad; 54-second external circuitry; 54a-connects connection pad; The 56-lead; The 58-polymer protective layer; The 59-integrated circuit; The 60-polymeric layer; The 60a-opening; 62-sticks together/barrier layer; The 64-Seed Layer; The 66-photoresist layer; 66a-photoresist layer opening; The 68-metal level; 68a-routing connection pad; 68b-routing connection pad; The 70-polymeric layer; The 70a-opening; The 72-semiconductor chip; 72a-first semiconductor chip; 72b-second semiconductor chip; The 74-adhesive agent; 76-first external circuitry; 76a-connects connection pad; 78-second external circuitry; 78a-connects connection pad; The 80-lead; The 81-polymer protective layer; The 82a-semiconductor chip; The 82b-semiconductor chip; The 82c-semiconductor chip; The 82d-semiconductor chip; The 84-first external circuitry plate; 86-second external circuitry; 88a-routing connection pad; 88b-routing connection pad; 90a-routing connection pad; 90b-routing connection pad; 92a-routing connection pad; 92b-routing connection pad; 94a-routing connection pad; 94b-routing connection pad; 84a-connects connection pad; 86a-connects connection pad; The 96-lead; The 97-polymer protective layer; The 100-integrated circuit; The 112-polymeric layer; The 112a-opening; 114-polymer projection; 116-sticks together/barrier layer; The 118-Seed Layer; The 120-photoresist layer; 120a-photoresist layer opening; The 122-metal level; 124-engages connection pad; The 126-semiconductor chip; The 128-external circuitry; 129-jointing metal layer; The 130-anisotropic conductive; 132-tin layer; 134-Sillim alloy-layer; 32 '-connection pad; 120b-photoresist layer opening; 136-routing connection pad; The extraneous substrate of 138-; 140-engages connection pad; 142-jointing metal layer; The 144-encapsulated layer; The 146-lead; 147-tin ball; The 148-polymer blocks; The 150-polymeric layer; 152-polymer projection; The 154-metal level; The 156-metal level; The 158-photoresist layer; 158a-photoresist layer opening; The 160-metal level.
Embodiment
The present invention is semiconductor circuits modular construction and processing procedure thereof; wherein among this invention, disclose several dissimilar semiconductor circuits modular construction and processing procedures thereof; each method that is disclosed and structure all are to be built in the semiconductor substrate; and on this semiconductor-based end, more be provided with a thin on-line composition and a protective layer; therefore at first explain orally this semiconductor-based end; after the structure and formation method of thin on-line composition and protective layer; carry out the explanation of various embodiments of the invention again; be that expression is positioned at above the something and contact with it in the present invention at preceding " top " speech of definition earlier that explains orally in addition; or expression is positioned at above the something but contact with it, and " on " word is that expression is positioned at above the something and contact with it in the present invention.
The semiconductor-based end:
See also shown in Fig. 1 a, a substrate (substrate) 10 is provided, substrate 10 is a silicon base (siliconsubstrate) normally, and this silicon base can be an essence (intrinsic) silicon base, a p type silicon base or a n type silicon base.For high performance chip, then be to use SiGe (SiGe) or silicon-on-insulator (Silicon-On-Insulator, SOI) substrate.Wherein, silicon-Germanium base comprises that a SiGe grows nonparasitically upon another plant layer (epitaxial layer) on the surface of silicon base, and in addition the silicon-on-insulator substrate then comprises an insulating barrier (being preferably silica) on a silicon base, and a silicon or the SiGe layer of growing nonparasitically upon another plant is formed on the insulating barrier.
Then see also shown in Fig. 1 b, in this substrate 10, form a component layer (device layer) 12, this component layer 12 generally includes at least one semiconductor subassembly (semiconductor device), and this component layer 12 is in the surface of substrate 10 and/or is on the surface.Wherein, semiconductor subassembly can be a MOS (metal-oxide-semiconductor) transistor (MOStransistor) 14, N type MOS (metal-oxide-semiconductor) transistor (NMOS transistor for example, n-channel MOS transistor) or P type MOS (metal-oxide-semiconductor) transistor (PMOS transistor, p-channel MOS transistor), and this MOS (metal-oxide-semiconductor) transistor 14 comprises one source pole 16, one drain 18 and a gate 20, and gate 20 polysilicon (polysilicon) normally, one compound crystal metal silication tungsten (tungsten polycide), one tungsten silicide (tungsten silicide), one titanium silicide (titanium silicide), an one cobalt silicon (cobalt silicide) or a silicide gate (salicide gate).In addition, semiconductor subassembly also can be two-carrier transistor (bipolar transistor), diffused metal oxide emiconductor (Diffused MOS, DMOS), Laterally Diffused Metal Oxide Semiconductor (Lateral Diffused MOS, LDMOS), Charged Coupled Device (Charged-Coupled Device, CCD), CMOS (Complementary Metal Oxide Semiconductor) (CMOS) sensing component, photodiode (photo-sensitive diode), resistor assembly (because polysilicon layer or diffusion region in the silicon base form).Utilize these semiconductor subassemblies can form various circuit, for example CMOS (Complementary Metal Oxide Semiconductor) (CMOS) circuit, N type metal-oxide-semiconductor (MOS) circuit, P type metal-oxide-semiconductor (MOS) circuit, two-carrier CMOS (Complementary Metal Oxide Semiconductor) (BiC MOS) circuit, CMOS semiconductor sensor circuit, diffused metal oxide emiconductor power circuit, Laterally Diffused Metal Oxide Semiconductor circuit etc.In addition, component layer 12 also comprise a NOR gate (NOR gate) or a NAND gate (NAND gate) outside, it also can be an inverter (inverter), one and lock (AND gate), one or the door (OR gate), one sram cell (SRAM cell), one DRAM (Dynamic Random Access Memory) unit (DRAM cell), one non-volatile memory cell (non-volatile memory cell), one flash cell (flash memory cell), one Erasable ﹠Programmable ROM unit (EPROM cell), one ROM unit (ROM cell), one magnetic RAM (magnetic RAM, MRAM) unit, one sensing amplifier (sense amplifier), one amplifier is calculated big device (operational amplifier, Op Amp, OPA), one adder (adder), one multiplexer (multiplexer), one duplexer (diplexer), one multiplier (multiplier), one analog/digital converter (A/D converter), one digital/analog converter (D/A converter), one CMOS (Complementary Metal Oxide Semiconductor) sensing component unit (CMOS sensorcell), one photosensitive diode (photo-sensitive diode), one CMOS (Complementary Metal Oxide Semiconductor), one two-carrier CMOS (Complementary Metal Oxide Semiconductor), one two-carrier circuit (bipolar circuit) or analog circuit (analog circuit).
Thin on-line composition:
See also shown in Fig. 1 c, on substrate 10 and component layer 12, form a fine rule line structure 22, this fine rule line structure 22 comprises several thin line layers (fine-line conductivity layer) 24, several fine rule road dielectric layers (fine-line dielectric layer) 26, several opening 28 and conductive plugs in the opening 28 (fine-line via plug) 30 at fine rule road dielectric layer 26, the thin line layer 24 at this external top is provided with at least one zone, and these zone definitions are connection pad 32.
In addition, the thickness of each thin line layer 24 is between 0.05 micron (μ m) is to 2 microns, and be preferable with the thickness between 0.2 micron to 1 micron, if in addition thin line layer 24 circuits, then its transverse design standard (width) is between 20 nanometers (nano-meter) are to 15 microns, and with between being preferable between 20 nanometers to 2 micron.
At first explain orally thin line layer 24 and be aluminium lamination, the aluminium lamination of thin line layer 24 normally utilizes physical vapour deposition (PVD) (Physical Vapor Deposition, PVD) mode forms, for example utilize the mode of sputter (sputtering) to form, then between a photoresist layer that (is preferably between 0.3 micron to 2 microns) between 0.1 micron to 4 microns this aluminium lamination is carried out patterning by deposit thickness, come this aluminium lamination is carried out a wet etching (wetetching) or a dry ecthing (dry etching), preferable mode is dry type electricity slurry (dry plasma) etching (comprising fluorine electricity slurry usually) again.In addition, alternatively under aluminium lamination form one and stick together/barrier layer (adhesion/barrier layer), wherein this stick together/barrier layer can be the formed composite bed of titanium, titanium-tungsten, titanium nitride or above-mentioned material; And on aluminium lamination the also alternative anti-reflecting layer (for example titanium nitride) that forms.In addition, opening 28 alternatives with chemical vapour deposition (CVD) (chemical vapor deposition, CVD) mode of tungsten metal is filled up, then again with cmp (chemical mechanical polish, CMP) mode is ground the tungsten metal level, to form conductive plug 30.
Then explain orally thin line layer 24 and be the copper layer, the copper layer of thin line layer 24 normally utilizes the mode of electroplating with damascene process (damascene process) to form, and it is described below: (1) deposition one bronze medal diffused barrier layer (for example layer of oxynitride or the nitride layer of thickness between 0.05 micron to 0.25 micron); (2) utilize plasma enhanced chemical vapor deposition (plasma enhanced CVD, PECVD), rotary coating (spin-on coating) or high density plasma enhanced chemical vapor deposition (High Density Plasma CVD, HDPCVD) the fine rule road dielectric layer 26 of mode deposit thickness between 0.1 micron to 2.5 microns, wherein this fine rule road dielectric layer 26 is to be the preferably with the thickness between 0.3 micron to 1.5 microns; (3) utilize the photoresist layer of deposit thickness between 0.1 micron to 4 microns to come patterning fine rule road dielectric layer 26, wherein the thickness of photoresist layer is again being the preferably between 0.3 micron to 2 microns, then this photoresist layer is exposed and development, make photoresist layer form several openings and/or be several irrigation canals and ditches, remove this photoresist layer again; (4) utilize the mode of sputter or chemical vapour deposition (CVD), deposition one is sticked together/barrier layer and a Seed Layer (seed layer).Wherein, this sticks together/and barrier layer comprises tantalum, tantalum nitride, titanium nitride, titanium or titanium-tungsten, or by the formed composite bed of above-mentioned material.In addition, this Seed Layer is a bronze medal layer normally, and this copper layer can be to utilize sputter copper metal, chemical vapour deposition (CVD) copper metal, or earlier with chemical vapour deposition (CVD) one bronze medal metal, and then the mode of sputter one bronze medal metal forms; (5) the bronze medal layer of electroplating thickness between 0.05 micron to 2 microns is the preferably with the bronze medal layer of electroplating thickness between 0.2 micron to 1 micron again wherein on this Seed Layer; (6) remove not in the opening of fine rule road dielectric layer 26 or copper floor, Seed Layer in the irrigation canals and ditches in the mode of grinding (preferable mode is a cmp) wafer and stick together/barrier layer, until expose be positioned at stick together/fine rule road dielectric layer 26 under the barrier layer till.After through cmp, the only remaining metal that is positioned at opening or irrigation canals and ditches, remaining metal then is used as metallic conductor (circuit or plane) or conductive plug 30 (connecting two adjacent thin line layers 24).In addition, also can utilize a dual damascene (double-damascene) processing procedure, in an electroplating process and a cmp, form conductive plug 30 and metallic circuit or metal flat simultaneously.Twice little shadow (photolithography) processing procedure and twice electroplating process are to be useful on the double-insert process.Between the step (3) of patterning one dielectric layer of double-insert process in above-mentioned single damascene process and the step (4) of depositing metal layers, increase the fabrication steps of more depositions and another dielectric layer of patterning.
Fine rule road dielectric layer 26 then is described, fine rule road dielectric layer 26 is to utilize the mode of chemical vapour deposition (CVD), plasma enhanced chemical vapor deposition, high density plasma enhanced chemical vapor deposition or spin coating (spin-on) to form.The material of fine rule road dielectric layer 26 comprises silica (silicon oxide), silicon nitride (silicon nitride), silicon oxynitride (silicon oxynitride), tetraethoxysilane (PECVDTEOS) with plasma enhanced chemical vapor deposition formation, spin-coating glass (SOG, Si oxide or siloxy group), fluorine silex glass (Fluorinated SilicateGlass, FSG) or a low-k (low-K) material, black diamond film (Black Diamond for example, it is the product of Applied Materials, and company's translated name is an Applied Materials), the dielectric material of the low-k of ULKCORAL (being the product of Novellus company) or SiLK (IBM Corporation).The silica that forms with plasma enhanced chemical vapor deposition, the tetraethoxysilane that forms with plasma enhanced chemical vapor deposition or have dielectric constant K between 3.5 to 4.5 with the oxide that high-density electric slurry forms; The fluorine silex glass that forms with plasma enhanced chemical vapor deposition or have dielectric constant values between 3.0 to 3.5 with the fluorine silex glass that high-density electric slurry forms, low dielectric constant dielectric materials then has the dielectric constant values between 1.5 to 3.5.Low dielectric constant dielectric materials, black diamond film for example, it is a porousness, and includes hydrogen, carbon, silicon and oxygen, its molecular formula is HwCxSiyOz.This fine rule road dielectric layer 26 generally includes inorganic material (inorganic material), in order to reach thickness greater than 2 microns.The thickness of each fine rule road dielectric layer 26 is between 0.05 micron to 2 microns.In addition, the opening 28 in the fine rule road dielectric layer 26 is to utilize the mode etched pattern photoresist layer of wet etching or dry ecthing to form, and wherein preferable etching mode is dry ecthing.The dry ecthing kind comprises fluorine electricity slurry (fluorineplasma).
Protective layer:
See also shown in Fig. 1 c, form a protective layer 34 on fine rule line structure 22, this protective layer 34 is being played the part of very important role in the present invention.Protective layer 34 is an important part in IC industry; outstanding as nineteen ninety by S.Wolf; and " the Silicon Processing in theVLSI era " the 2nd that issued by Lattice Press is described; protective layer 34 is to be defined as final layer in integrated circuit manufacture process, and is deposited on the surface on the whole of wafer.Protective layer 34 is an insulation, protective layer, can prevent the machinery and chemistry injury that are caused during assembling and encapsulation.Except preventing mechanical scratch, protective layer 34 also can prevent moving iron (mobile ion), such as being sodium (sodium) ion, and transition metal (transition metal), such as being gold, copper, penetrate into integrated circuit package to the below.In addition, protective layer 34 also can be protected the assembly of below and the intrusion that connection line (fine rule road metal structure and fine rule road dielectric layer) avoids being subjected to aqueous vapor (moisture).
See also shown in Fig. 1 d, form at least one opening 36 at this protective layer 34, the opening 36 of this protective layer 34 is to utilize the mode of wet etching or dry ecthing to form, and wherein is again preferred mode with the dry ecthing.In addition, the size of opening 36 is between 0.1 micron to 200 microns, and between 1 micron to 100 microns or between 5 microns to 30 microns, being the preferably, the shape of opening 36 can be circle, square, rectangle or polygon in addition, so the size of above-mentioned opening 36 is meant circular diameter dimension, foursquare size dimension, polygonal long-diagonal size or rectangular width dimensions, wherein rectangular length dimension then is between 1 micron to 1 centimetre, and between 5 microns to 200 microns, being preferable.
Wherein the opening 36 of protective layer 34 also has different sizes for component layer 12 set assembly differences, and generally speaking the size of the opening 36 of protective layer 34 is between 0.1 micron to 100 microns, and between 0.3 micron to 30 microns, being the preferably; If be that pressurizer, transformer and electrostatic storage deflection (ESD) protection circuit are set in the component layer 12, the size of this opening 36 is bigger, and its scope is between 1 micron to 150 microns, and between 5 microns to 100 microns, being preferable.In addition, opening 36 exposes the connection pad (metal pad) 32 of thin line layer 24 the superiors, in order to be electrically connected the circuit or the plane of protective layer 36 tops (over-passivation).
Above-described organization definition is wafer (wafer), Silicon Wafer (silicon wafer) for example, be to use the integrated circuit manufacture process technology of different generations to make, for example 1 micron, 0.8 micron, 0.6 micron, 0.5 micron, 0.35 micron, 0.25 micron, 0.18 micron, 0.25 micron, 0.13 micron, 90 nanometers (nm), 65 nanometers, 45 nanometers, 35 nanometers, 25 nanometer technologies define and the generation of these integrated circuit manufacture process technology is gate length (gate length) or effective channel lengths (channel length) with MOS (metal-oxide-semiconductor) transistor 14.
The size of wafer is such as being or etc. at 5 o'clock, 6 o'clock, 8 o'clock, 12 o'clock at 18 o'clock.Substrate 10 is to use micro-photographing process to make, and this micro-photographing process comprises coating (coating), exposure (exposing) and (developing) photoresistance that develops.Be used in the photoresistance of making substrate 10, its thickness is between 0.1 micron to 0.4 micron, and with five times of (5X) stepping exposure machines (stepper) or scanning machine (scanner) this photoresistance that exposes.Wherein, the multiple of stepping exposure machine be meant when light beam from a light shield (normally with quartz constitute) when being projected on the wafer, figure on the light shield dwindles the ratio on wafer, and five times (5X) is meant that promptly pattern proportion on the light shield is five times of pattern proportion on the wafer.Priority of use is advanced the technical scanning machine of integrated circuit manufacture process from generation to generation, normally dwindles with four times of (4X) dimension scales and improves resolution.The employed light beam wavelength of stepping exposure machine or scanning machine be 436 nanometers (g-line), 365 nanometers (i-line), 248 nanometers (deep UV (ultraviolet light), DUV), 193 nanometers (DUV), 157 nanometers (DUV) or 13.5 nanometers (extremely short ultraviolet light, EUV).In addition, the little shadow technology of profit formula (high-indeximmersion) invaded in high index also can be in order to finish the thin line layer 24 on the wafer.
In addition, wafer is to make in having the dust free room (clean room) of grade 10 (class10) or better (for example grade 1).The dust free room of grade 10 allows the maximum dust particle number of every cubic feet per Foot to be: the dust particle that contains more than or equal to 1 micron is no more than 1, the dust particle that contains more than or equal to 0.5 micron is no more than 10, the dust particle that contains more than or equal to 0.3 micron is no more than 30, the dust particle that contains more than or equal to 0.2 micron is no more than 75, the dust particle that contains more than or equal to 0.1 micron is no more than 350, and the dust free room of grade 1 then allows the maximum dust particle number of every cubic feet per Foot to be: the dust particle that contains more than or equal to 0.5 micron is no more than 1, the dust particle that contains more than or equal to 0.3 micron is no more than 3, the dust particle that contains more than or equal to 0.2 micron is no more than 7, the dust particle that contains more than or equal to 0.1 micron is no more than 35.
Wherein when using copper as thin line layer 24; then need to use a metal top layer (metal cap) (not shown) to protect protective layer 34 copper connection pads 32 that opening 36 exposes; make this connection pad 32 avoid being subjected to oxidation and erosion damage, and can be used as the routing joint of follow-up chip.This metal top layer comprises an aluminium (aluminum) layer, a gold medal (gold) layer, a titanium (Ti) layer, a titanium-tungsten layer, a tantalum (Ta) layer, tantalum nitride (TaN) layer or a nickel (Ni) layer.Wherein, when metal top layer is an aluminium lamination, then between copper connection pad and metal top layer, be formed with a barrier layer (barrier layer), and this barrier layer comprises titanium, titanium-tungsten, titanium nitride, tantalum, tantalum nitride, chromium (Cr) or nickel.
Above-mentioned is the semiconductor-based end 10 of the present invention; the explanation of fine rule line structure 22 and protective layer 34; below explain orally several dissimilar embodiment of the present invention; embodiments of the invention are structure (over-passivationscheme) and processing procedures of making on the protective layer; structure on the protective layer includes the encapsulation of stacking-type in the present invention; the subsides band of polymer projection engages (tape automated bonded automatically; TAB); COG (chip on glass); coil type crystal grain engages (Tape Carrier Package; TCP); the packaged type of COF (chip on film); and utilize the polymer projection to cover crystalline substance (Flip Chip; FC) technology is engaged on another extraneous substrate, below explains orally structure and the processing procedure of each embodiment respectively.
The following in addition manifold material of embodiment that is explained orally is identical with processing procedure; the material of the same components among therefore following each embodiment and the embodiment and processing procedure are with regard to not in addition repeat specification; for example the connection pad 32 among the Yi Xia embodiment be aluminium material connection pad as an illustration; but the material of connection pad 32 also can be a copper; difference is when the material of connection pad 32 includes the copper metal; the connection pad that contains the copper metal 32 that must use a metal top layer (for example aluminium lamination) to come protective layer 34 openings 36 to be exposed allows the connection pad 32 that contains the copper metal avoid being subjected to oxidation and erosion damage.And when metal top layer is an aluminium lamination, between connection pad 32 and aluminium lamination, being formed with a barrier layer (barrierlayer), this barrier layer comprises titanium, titanium-tungsten, titanium nitride, tantalum, tantalum nitride, chromium (Cr) or nickel.Beneath content is to describe with the situation that does not have metal top layer, so has the knack of described operator when the explanation that can rely on the following example, implements according to this in the mode that adds metal top layer.
The 1st execution mode of first embodiment:
At first see also shown in Fig. 2 a; form one stick together/barrier layer (adhesion/barrier layer) 38 is on the protective layer above the whole substrate 10 34 and connection pad 32; this substrate 10 in the present invention is meant Silicon Wafer (siliconwafer), and this sticks together/and the material of barrier layer 38 can be titanium, tungsten, cobalt, nickel, titanium nitride, titanium-tungsten, vanadium, chromium, copper, chrome copper, tantalum, tantalum nitride, the formed alloy of above-mentioned material or the composite bed of being made up of above-mentioned material.In addition, stick together/barrier layer 38 can utilize the mode of plating (electroplating), electroless-plating (electroless plating), chemical vapour deposition (CVD) or physical vapour deposition (PVD) (for example sputter) to form, be preferable generation type with physical vapour deposition (PVD) again wherein, metal sputtering processing procedure for example.In addition this stick together/thickness of barrier layer 38 is between 0.02 micron to 0.8 micron, and is preferable with the thickness between 0.05 micron to 0.2 micron.
See also shown in Fig. 2 b, then form thickness between a Seed Layer (seed layer) 40 of (preferred thickness is between between 0.1 micron to 0.7 micron) between 0.005 micron to 2 microns sticking together/barrier layer 38 on, and the mode that forms Seed Layer 40 is such as the mode that is sputter, evaporation, physical vapour deposition (PVD), plating or electroless-plating (electroless plating).This Seed Layer 40 helps the setting of follow-up metallic circuit, so the material of Seed Layer 40 can change to some extent with the material of follow-up metallic circuit.For example, when electroplate forming the metal level of copper material on the Seed Layer 40, the material of Seed Layer 40 is to be good with copper; When electroplating the metal level that forms golden material on the Seed Layer 40, the material of Seed Layer 40 is with Jin Weijia; When electroplate forming the metal level of palladium material on the Seed Layer 40, the material of Seed Layer 40 is to be good with palladium; When electroplate forming the metal level of platinum product matter on the Seed Layer 40, the material of Seed Layer 40 is to be good with platinum; When electroplate forming the metal level of rhodium material on the Seed Layer 40, the material of Seed Layer 40 is to be good with rhodium; When electroplating the metal level that forms the ruthenium material on the Seed Layer 40, the material of Seed Layer 40 is good with ruthenium; When electroplate forming the metal level of rhenium material on the Seed Layer 40, the material of Seed Layer 40 is to be good with rhenium; When electroplate forming the metal level of nickel material on the Seed Layer 40, the material of Seed Layer 40 is to be good with nickel.
See also shown in Fig. 2 c, form a photoresist layer 42 on Seed Layer 40, and by the exposure (exposure) and this photoresist layer 42 of (development) processing procedure patterning that develops, forming photoresist layer opening 42a photoresist layer 42 in and expose the Seed Layer 40 that is positioned at above the connection pad 32, and in the process of formation photoresist layer opening 42a such as being that exposure machine (steppers) or scanning machine (scanners) with one times (1X) carries out exposure imaging.
Wherein this photoresist layer 42 has two kinds of patterns, and it is: (1) wet film photoresistance (liquid Photo resist), it is to utilize single or multiple rotary coating mode or printing (printing) mode to form.The thickness of this wet film photoresistance is between 3 microns to 60 microns, and between 5 microns to 40 microns, being the preferably; And (2) dry film photoresistance (dry film Photo resist), it is to utilize laminating type (laminating method) to form.The thickness of this dry film photoresistance is between 30 microns to 300 microns, and between 50 microns to 150 microns, being preferable.In addition, photoresistance can be eurymeric (positive-type) or minus (negative-type), and is obtaining on the better resolution, is preferable with the thick photoresistance of eurymeric (positive-type thick Photo resist) then.Utilize an alignment machine (aligner) or one times of (1X) stepping exposure machine this photoresistance that exposes.This one times (1X) is meant that when being projected on the wafer, the figure on the light shield dwindles the ratio on wafer from a light shield (normally constituting with quartz or glass) when light beam, and is identical with pattern proportion on wafer at the pattern proportion on the light shield.Alignment machine or one times of employed light beam wavelength of stepping exposure machine are 436 nanometers (g-line), 397 nanometers (h-line), 365 nanometers (i-line), g/h line (in conjunction with g-line and h-line) or g/h/i line (combining g-line, h-line and i-line).Use light beam wavelength can revolve in the exposure of optically active polymer (photo senstive polymer) at thick photoresistance or thick sense, bigger luminous intensity (light intensity) is provided as one times of stepping exposure machine (or one times of alignment machine) of g/h line or g/h/i line; In addition, the shape of the opening 42a of this patterning photoresist layer 42 also can comprise coil shape, square, circular, polygon or irregularly shaped.
See also shown in Fig. 2 d and Fig. 2 e, form a metal level 44 on the Seed Layer 40 that opening 42a is exposed with plating mode, metal level 44 is such as being gold, copper, silver, palladium, platinum, rhodium, ruthenium, the single-layer metal layer structure of rhenium or nickel or composite metal layer structure, the thickness of this metal level 44 is between 1 micron to 20 microns, preferable thickness can be between 1.5 microns to 15 microns, and the combination of composite metal layer structure comprises copper/nickel/gold, copper/gold, copper/nickel/palladium and copper/nickel/combinations such as platinum, this metal level 44 is individual layers in this embodiment, and the material of metal level 44 is gold.Two zones of definition are gone up on these metal level 44 surfaces, this two zone is respectively routing connection pad 44a and routing connection pad 44b, this routing connection pad 44a, 44b can provide the purposes of routing in successive process, this routing connection pad 44a, 44b sees it from birds-eye perspective (Fig. 2 e), routing connection pad 44a, the 44b position is the position that is different from connection pad 32, wherein can be provided with at least one driving component in the substrate 10 of routing connection pad 44a or routing connection pad 44b below, this driving component comprises diode, transistor etc., driving component existing detailed introduction in said modules layer 12, just do not repeated to discuss at this, routing connection pad 44a in addition, one of them position of 44b can be positioned at the position of connection pad 32 tops, shown in Fig. 2 f, routing connection pad 44a, the 44b position can not change simultaneously and to some extent along with user's demand.
See also shown in Fig. 2 g, remove patterning photoresist layer 42, wherein remove patterning photoresist layer 42 with an organic solvent mode remove, for example acetone, alcohols etc. also can use the inorganic solvent mode to remove, for example sulfuric acid and hydrogen peroxide (H in addition
2SO
4, H
2O
2) etc., moreover the also available high pressure oxygen of this patterning photoresist layer 42 (O
2) mode of burning removes.
See also shown in Fig. 2 h, remove not the Seed Layer below metal level 44 40, stick together/barrier layer 38, wherein when if the material of Seed Layer 44 is gold, then can utilize the etching solution that contains iodine to remove, and remove stick together/mode of barrier layer 38 is divided into dry-etching and Wet-type etching, wherein dry-etching uses the high pressure argon gas to splash etching, and Wet-type etching is sticking together/and when barrier layer 38 is titanium-tungsten, then can use hydrogen peroxide to remove.
See also shown in Fig. 2 i; then forming a polymeric layer 46 is positioned on protective layer 34 and the metal level 44; and by exposure (exposure); (development) processing procedure and this polymeric layer 46 of etch process patterning develop; make this polymeric layer 46 form several openings 46a; this opening 46a exposes the routing connection pad 44a on the metal level 44; 44b; then carry out heat hardening; make this polymeric layer 46 sclerosis; the temperature of this hardening process be between 150 the degree (℃) to 300 the degree (℃) between; and the material of this polymeric layer 46 is optional from polyimides (polyimide; PI); benzyl ring butylene (benzocyclobutene; BCB); Parylene (parylene); epoxy-based material (epoxy-based material) one of them; epoxy resin or for example by the photoepoxySU-8 that SotecMicrosystems provided of the Renens that is positioned at Switzerland; elastomeric material (elastomer), for example silicone (silicone).Wherein this polymeric layer 46 is senses when revolving the optical activity material, can only utilize micro-photographing process (need not etch process) to come this polymeric layer 46 of patterning.
See also shown in Fig. 2 j, Fig. 2 j has only routing connection pad 44a, 44b different with Fig. 2 i, and Fig. 2 j illustrates that once more the position of routing connection pad 44a, 44b can change to some extent according to user or product design demand.
See also shown in Fig. 2 k, cutting step is carried out in substrate 10, produce several semiconductor chips (chip) 48.
So far finish the making explanation of semiconductor chip 48, beneath various structures with protective layer 34 belows among integrated circuit 49 representative graph 2a to Fig. 2 i.Also promptly comprise substrate 10, component layer 12, MOS (metal-oxide-semiconductor) transistor 14, source electrode 16, drain 18, gate 20, fine rule line structure 22, fine rule road dielectric layer 26, conductive plug 30 etc. with integrated circuit 49.
See also shown in Fig. 2 l and Fig. 2 m, these semiconductor chips 48 comprise one first semiconductor chip 48a and one second semiconductor chip 48b; Wherein the first semiconductor chip 48a and the second semiconductor chip 48b may come comfortable same substrate 10 or different base 10, or the first semiconductor chip 48a and the second semiconductor chip 48b may be identical or different in structural design; Utilize an adhesive agent 50 (for example epoxy resin) that the first semiconductor chip 48a is sticked together on one first external circuitry 52 again, this first external circuitry 52 comprise printed circuit board (PCB), metal substrate, glass substrate, flexible base plate, ceramic substrate and silicon substrate one of them, in this embodiment first external circuitry 52 are printed circuit board (PCB)s, and this first external circuitry 52 has several and connects connection pad 52a.
Utilize adhesive agent 50 that the second semiconductor chip 48b lower surface is sticked together folded being located on the polymeric layer 46 of the first semiconductor chip 48a equally, wherein the first semiconductor chip 48a has 1% to 10% area exposure at least, and the area that the first semiconductor chip 48a exposes comprises routing connection pad 44a and the routing connection pad 44b of the first semiconductor chip 48a.
See also shown in Fig. 2 n, utilize adhesive agent 50 that one second external circuitry, 54 lower surfaces are sticked together folded being located on the polymeric layer 46 of the second semiconductor chip 48b equally, this second external circuitry 54 can be selected from printed circuit board (PCB), metal substrate, glass substrate, flexible base plate, ceramic substrate and silicon substrate one of them, this second external circuitry 54 is silicons in this embodiment, and this second external circuitry 54 has several and connects connection pad 54a.
See also shown in Fig. 2 o, utilize the routing processing procedure to form several leads 56 on the routing connection pad 44a and routing connection pad 44b of the first semiconductor chip 48a, on the routing connection pad 44a of the second semiconductor chip 48b and the routing connection pad 44b, on the connection connection pad 52a of first external circuitry 52, on the connection connection pad 54a of second external circuitry 54, the routing connection pad 44a of the first semiconductor chip 48a is interconnected with the connection pad 52a that is connected of first external circuitry 52, the routing connection pad 44b of the first semiconductor chip 48a and the routing connection pad 44a of the second semiconductor chip 48b are interconnected, the routing connection pad 44b of the second semiconductor chip 48b is interconnected with the connection pad 54a that is connected of second external circuitry 54, wherein have the routing connection pad 44a of the second semiconductor chip 48b of a little part, the connection connection pad 54a of second external circuitry 54 of part interconnects (not shown) with the connection pad 52a that is connected of first external circuitry 52 of part.
See also shown in Fig. 2 p; the first semiconductor chip 48a, the second semiconductor chip 48b, first external circuitry 52 and second external circuitry 54 of finishing the routing processing procedure are carried out encapsulation procedure; form a polymer protective layer 58 and be coated on the first semiconductor chip 48a, the second semiconductor chip 48b, first external circuitry 52 and second external circuitry 54, the material of this polymer protective layer 58 is such as being epoxy resin.
The 2nd execution mode of first embodiment:
The structure of the structure of this 2nd execution mode and manufacture method and the 1st execution mode and manufacture method are quite similar; the material of the same components among therefore following each embodiment and the embodiment and processing procedure be with regard to not in addition repeat specification, wherein with the various structures of protective layer 34 belows among integrated circuit 59 representative graph 3a to Fig. 3 g and Fig. 3 i to Fig. 3 m.Also promptly comprise substrate 10, component layer 12, MOS (metal-oxide-semiconductor) transistor 14, source electrode 16, drain 18, gate 20, fine rule line structure 22, fine rule road dielectric layer 26, conductive plug 30 etc. with integrated circuit 59.
See also shown in Fig. 3 a; forming a polymeric layer 60 is positioned on the protective layer 34; and, making this polymeric layer 60 form several openings 60a by exposure (exposure), develop (development) processing procedure and this polymeric layer 60 of etch process patterning, this opening 60a exposes connection pad 32.
See also shown in Fig. 3 b, then form one stick together/barrier layer (adhesion/barrier layer) 62 is on the polymeric layer above the whole substrate 10 60 and connection pad 32; Then form again thickness between a Seed Layer (the seed layer) 64 of (preferred thickness is between between 0.1 micron to 0.7 micron) between 0.005 micron to 2 microns on whole sticking together/barrier layer 62.
See also shown in Fig. 3 c, form a photoresist layer 66 on Seed Layer 64, and by the exposure (exposure) and this photoresist layer 66 of (development) processing procedure patterning that develops, forming photoresist layer opening 66a photoresist layer 66 in and expose the Seed Layer 64 that is positioned at above the connection pad 32, and in the process of formation photoresist layer opening 66a such as being that exposure machine (steppers) or scanning machine (scanners) with one times (1X) carries out exposure imaging.
See also shown in Fig. 3 d and Fig. 3 e, with plating mode form a metal level 68 in opening 66a with Seed Layer 64 on, metal level 68 is such as being gold, copper, silver, palladium, platinum, rhodium, ruthenium, the single-layer metal layer structure of rhenium or nickel or composite metal layer structure, the thickness of this metal level 68 is between 1 micron to 20 microns, preferable thickness can be between 1.5 microns to 15 microns, and the combination of composite metal layer structure comprises copper/nickel/gold, copper/gold, copper/nickel/palladium and copper/nickel/combinations such as platinum, this metal level 68 is individual layers in this embodiment, and the material of metal level 68 is gold.Two zones of definition are gone up on these metal level 68 surfaces, this two zone is respectively routing connection pad 68a and routing connection pad 68b, this routing connection pad 68a, 68b can provide the purposes of routing in successive process, this routing connection pad 68a, 68b see it from birds-eye perspective, routing connection pad 68a, 68b position are the positions that is different from connection pad 32, wherein can be provided with at least one driving component in the substrate 10 of routing connection pad 68a or routing connection pad 68b below, this driving component is existing detailed introduction in said modules layer 12, is not just repeated to discuss at this.
See also shown in Fig. 3 f, remove patterning photoresist layer 66 and remove not the Seed Layer below metal level 68 64, stick together/barrier layer 62.
See also shown in Fig. 3 g, then forming a polymeric layer 70 is positioned on polymeric layer 60 and the metal level 68, and by exposure (exposure), development (development) processing procedure and this polymeric layer 70 of etch process patterning, make this polymeric layer 70 form several openings 70a, this opening 70a exposes routing connection pad 68a, the 68b on the metal level 68, then carry out heat hardening, make this polymeric layer 70 sclerosis.
See also shown in Fig. 3 h, cutting step is carried out in substrate 10, produce several semiconductor chips (chip) 72.
See also shown in Fig. 3 i and Fig. 3 j, these semiconductor chips 72 comprise one first semiconductor chip 72a and one second semiconductor chip 72b; Wherein the first semiconductor chip 72a and the second semiconductor chip 72b may come comfortable same substrate 10 or different base 10, or the first semiconductor chip 72a and the second semiconductor chip 72b may be identical or different in structural design; Utilize an adhesive agent 74 (for example epoxy resin) that the first semiconductor chip 72a is sticked together on one first external circuitry 76 again, this first external circuitry 76 has several and connects connection pad 76a.
Utilize adhesive agent 74 that the second semiconductor chip 72b lower surface is sticked together folded being located on the polymeric layer 70 of the first semiconductor chip 72a equally, wherein the first semiconductor chip 72a has 1% to 10% area exposure at least, and the area that the first semiconductor chip 72a exposes comprises routing connection pad 68a and the routing connection pad 68b of the first semiconductor chip 72a.
See also shown in Fig. 3 k, utilize adhesive agent 74 that one second external circuitry, 78 lower surfaces are sticked together folded being located on the polymeric layer 70 of the second semiconductor chip 72b equally, this second external circuitry 78 can be selected from printed circuit board (PCB), metal substrate, glass substrate, flexible base plate, ceramic substrate and silicon substrate one of them, this second external circuitry 78 is silicons in this embodiment, and this second external circuitry 78 has several and connects connection pad 78a.
See also shown in Fig. 3 l, utilize the routing processing procedure to form several leads 80 on the routing connection pad 68a and routing connection pad 68b of the first semiconductor chip 72a, on the routing connection pad 68a of the second semiconductor chip 72b and the routing connection pad 68b, on the connection connection pad 76a of first external circuitry 76, on the connection connection pad 78a of second external circuitry 78, the routing connection pad 68a of the first semiconductor chip 72a is interconnected with the connection pad 76a that is connected of first external circuitry 76, the routing connection pad 68b of the first semiconductor chip 72a and the routing connection pad 68a of the second semiconductor chip 72b are interconnected, the routing connection pad 68b of the second semiconductor chip 72b is interconnected with the connection pad 78a that is connected of second external circuitry 78, wherein have the routing connection pad 68a of the second semiconductor chip 72b of a little part, the connection connection pad 78a of second external circuitry 78 of part interconnects (not shown) with the connection pad 76a that is connected of first external circuitry 76 of part.
See also shown in Fig. 3 m; the first semiconductor chip 72a, the second semiconductor chip 72b, first external circuitry 76 and second external circuitry 78 of finishing the routing processing procedure are carried out encapsulation procedure; form a polymer protective layer 81 and be coated on the first semiconductor chip 72a, the second semiconductor chip 72b, first external circuitry 76 and second external circuitry 78, the material of this polymer protective layer 81 is such as being epoxy resin.
The 3rd execution mode of first embodiment:
The structure of the structure of this 3rd execution mode and manufacture method and the 2nd execution mode and manufacture method are quite similar, and the material of the same components among therefore following each embodiment and the embodiment and processing procedure are with regard to not in addition repeat specification.
The structure of the 2nd execution mode is by 2 semiconductor chip 72a and 72b is folded is located on the one first external circuitry plate 76, and be arranged on the semiconductor chip 72b of upper strata by another second external circuitry 78, via several leads 80 2 semiconductor chip 72a and 72b, the first external circuitry plate 76 and second external circuitry 78 are interconnected.The structure of the 3rd execution mode is shown in Fig. 4 a, Fig. 4 a then is by four semiconductor chip 82a, 82b, 82c, 82d, the first external circuitry plate 84 and second external circuitry 86 are formed, wherein form four semiconductor chip 82a, 82b, 82c, the processing procedure of 82d and material are as the processing procedure and the material (shown in Fig. 3 a to Fig. 3 h) of the 2nd execution mode, have routing connection pad 88a and routing connection pad 88b via the made semiconductor chip 82a of the processing procedure of the 2nd execution mode, semiconductor chip 82b has routing connection pad 90a and routing connection pad 90b, semiconductor chip 82c has routing connection pad 92a and routing connection pad 92b, semiconductor chip 82d has routing connection pad 94a and routing connection pad 94b, and the first external circuitry plate 84 has the connection pad of connection 84a, and second external circuitry 86 also has the connection pad of connection 86a.
Also be to utilize adhesive agent that semiconductor chip 82a is arranged on the first external circuitry plate 84 earlier in processing procedure, then utilizing adhesive agent in regular turn semiconductor chip 82b to be folded equally is located on the semiconductor chip 82a again, semiconductor chip 82c is folded to be located on the semiconductor chip 82b, semiconductor chip 82d is folded to be located on the semiconductor chip 82c, second external circuitry, 86 folded being located on the semiconductor chip 82d, semiconductor chip 82a wherein, semiconductor chip 82b and semiconductor chip 82c have 1% to 10% area exposure at least, semiconductor chip 82d then has 1%～70% area exposure at least, and semiconductor chip 82a, semiconductor chip 82b, the surface that semiconductor chip 82c and semiconductor chip 82d are exposed also makes routing connection pad 88a simultaneously, 88b, routing connection pad 90a, 90b, routing connection pad 92a, 92b and routing connection pad 94a, 94b exposes.
See also shown in Fig. 4 b, utilize the routing processing procedure to form several leads 96 on the routing connection pad 88a and routing connection pad 88b of semiconductor chip 82a, on the routing connection pad 90a of semiconductor chip 82b and the routing connection pad 90b, on the routing connection pad 92a of semiconductor chip 82c and the routing connection pad 92b, on the routing connection pad 94a of semiconductor chip 82d and the routing connection pad 94b, the connection connection pad 84a of the first external circuitry plate 84 is connected on the connection pad 86a with second external circuitry 86, the routing connection pad 88a of semiconductor chip 82a is interconnected with the connection pad 84a that is connected of first external circuitry 84, the routing connection pad 88b of semiconductor chip 82a and the routing connection pad 90a of semiconductor chip 82b are interconnected, the routing connection pad 90b of semiconductor chip 82b and the routing connection pad 92a of semiconductor chip 82c are interconnected, the routing connection pad 92b of semiconductor chip 82c and the routing connection pad 94a of semiconductor chip 82d are interconnected, the routing connection pad 94b of semiconductor chip 82d is interconnected with the connection pad 86a that is connected of second external circuitry 86.
Wherein the connection connection pad 86a of part second external circuitry 86 interconnects with the connection pad 84a that is connected of the first external circuitry plate 84, and the routing connection pad 92a of the semiconductor chip 82c of the routing connection pad 90a of the semiconductor chip 82b of part, part interconnects (not shown) with the routing connection pad 94a of the semiconductor chip 82d of part with the connection pad 84a that is connected of the first external circuitry plate 84.
See also shown in Fig. 4 c; semiconductor chip 82a, 82b, 82c, 82d, the first external circuitry plate 84 and second external circuitry 86 of finishing the routing processing procedure are carried out encapsulation procedure; form a polymer protective layer 97 and be coated on semiconductor chip 82a, 82b, 82c, 82d, the first external circuitry plate 84 and second external circuitry 86, the material of this polymer protective layer 97 is such as being epoxy resin.
The 1st execution mode of second embodiment:
In the structure of this embodiment, substrate 10, component layer 12, MOS (metal-oxide-semiconductor) transistor 14, source electrode 16, drain 18, gate 20, fine rule line structure 22, fine rule road dielectric layer 26, conductive plug 30 etc. replace with integrated circuit 100, and each structure in the integrated circuit 100 and processing procedure be in above-mentioned enforcement complete description, so the just not in addition repeat specification of each structure in the integrated circuit among the embodiment 100 and processing procedure.
See also shown in Fig. 5 a, form a polymeric layer 112 on protective layer on the whole integrated circuit 100 34 and connection pad 32.
See also shown in Fig. 5 b; and by exposure (exposure); (development) processing procedure and this polymeric layer 112 of etch process patterning develop; make this polymeric layer 112 form several opening (not shown) and several polymer projections (polymer bump) 114 (only demonstrating 1 in the icon); opening exposes protective layer 34 and connection pad 32; then carry out heat hardening; make this polymer projection 114 sclerosis; the temperature of this hardening process be between 150 the degree (℃) to 300 the degree (℃) between; and the material of this polymer projection 114 is optional from polyimides (polyimide; PI); benzyl ring butylene (benzocyclobutene; BCB); Parylene (parylene); epoxy-based material (epoxy-based material) one of them; epoxy resin or for example by the photoepoxySU-8 that SotecMicrosystems provided of the Renens that is positioned at Switzerland; elastomeric material (elastomer), for example silicone (silicone).When this polymeric layer 112 is that sense is when revolving the optical activity material, can only utilize micro-photographing process (need not etch process) to come this polymeric layer 112 of patterning, and the thickness of this polymer projection 114 is between 5 microns to 50 microns, and the maximum transverse size of polymer projection 114 is between 10 microns to 60 microns.
See also shown in Fig. 5 c, form one stick together/barrier layer (adhesion/barrier layer) 116 is on the protective layer 34 on the whole integrated circuit 100, connection pad 32 and polymer projection 114.In addition, stick together/barrier layer 116 can utilize the mode of plating (electroplating), electroless-plating (electroless plating), chemical vapour deposition (CVD) or physical vapour deposition (PVD) (for example sputter) to form, be preferable generation type with physical vapour deposition (PVD) again wherein, metal sputtering processing procedure for example.In addition this stick together/thickness of barrier layer 116 is between 0.02 micron to 0.8 micron, and is preferable with the thickness between 0.05 micron to 0.2 micron.
See also shown in Fig. 5 d, then form thickness between a Seed Layer (seed layer) 118 of (preferred thickness is between between 0.1 micron to 0.7 micron) between 0.005 micron to 2 microns sticking together/barrier layer 116 on, and the mode that forms Seed Layer 118 is such as the mode that is sputter, evaporation, physical vapour deposition (PVD), plating or electroless-plating (electroless plating).This Seed Layer 118 helps the setting of follow-up metallic circuit, so the material of Seed Layer 118 can change to some extent with the material of follow-up metallic circuit.For example, when electroplate forming the metal level of copper material on the Seed Layer 118, the material of Seed Layer 118 is to be good with copper; When electroplating the metal level that forms golden material on the Seed Layer 118, the material of Seed Layer 118 is with Jin Weijia; When electroplate forming the metal level of palladium material on the Seed Layer 118, the material of Seed Layer 118 is to be good with palladium; When electroplate forming the metal level of platinum product matter on the Seed Layer 118, the material of Seed Layer 118 is to be good with platinum; When electroplate forming the metal level of rhodium material on the Seed Layer 118, the material of Seed Layer 118 is to be good with rhodium; When electroplating the metal level that forms the ruthenium material on the Seed Layer 118, the material of Seed Layer 118 is good with ruthenium; When electroplate forming the metal level of rhenium material on the Seed Layer 118, the material of Seed Layer 118 is to be good with rhenium; When electroplate forming the metal level of nickel material on the Seed Layer 118, the material of Seed Layer 118 is to be good with nickel.
See also shown in Fig. 5 e, form a photoresist layer 120 on Seed Layer 118, and by the exposure (exposure) and this photoresist layer 120 of (development) processing procedure patterning that develops, forming several photoresist layer openings 120a (only demonstrating 1 in the icon) in photoresist layer 120 and expose the Seed Layer 118 that is positioned at above connection pad 32 and the polymer projection 114, and in the process that forms photoresist layer opening 120a such as being that exposure machine (steppers) or scanning machine (scanners) with one times (1X) carries out exposure imaging.
Wherein this photoresist layer 120 has two kinds of patterns, and it is: (1) wet film photoresistance (liquid Photo resist), it is to utilize single or multiple rotary coating mode or printing (printing) mode to form.The thickness of this wet film photoresistance is between 3 microns to 60 microns, and between 5 microns to 40 microns, being the preferably; And (2) dry film photoresistance (dry film Photo resist), it is to utilize laminating type (laminating method) to form.The thickness of this dry film photoresistance is between 30 microns to 300 microns, and between 50 microns to 150 microns, being preferable.In addition, photoresistance can be eurymeric (positive-type) or minus (negative-type), and is obtaining on the better resolution, is preferable with the thick photoresistance of eurymeric (positive-type thick Photo resist) then.Utilize an alignment machine (aligner) or one times of (1X) stepping exposure machine this photoresistance that exposes.This one times (1X) is meant that when being projected on the wafer, the figure on the light shield dwindles the ratio on wafer from a light shield (normally constituting with quartz or glass) when light beam, and is identical with pattern proportion on wafer at the pattern proportion on the light shield.Alignment machine or one times of employed light beam wavelength of stepping exposure machine are 436 nanometers (g-line), 397 nanometers (h-line), 365 nanometers (i-line), g/h line (in conjunction with g-line and h-line) or g/h/i line (combining g-line, h-line and i-line).Use light beam wavelength can revolve in the exposure of optically active polymer (photo senstive polymer) at thick photoresistance or thick sense, bigger luminous intensity (light intensity) is provided as one times of stepping exposure machine (or one times of alignment machine) of g/h line or g/h/i line; In addition, the shape of the opening 120a of this patterning photoresist layer 120 also can comprise coil shape, square, circular, polygon or irregularly shaped.
See also shown in Fig. 5 f, form a metal level 122 on the Seed Layer 118 that opening 120a is exposed with plating mode, this metal level 122 is coated polymer projection 114 2 lip-deep Seed Layer 118 at least, and this metal level 122 is such as being gold, copper, silver, palladium, platinum, rhodium, ruthenium, the single-layer metal layer structure of rhenium or nickel or composite metal layer structure, the thickness of this metal level 122 is between 1 micron to 20 microns, preferable thickness can be between 1.5 microns to 15 microns, and the combination of composite metal layer structure comprises copper/nickel/gold, copper/gold, copper/nickel/palladium and copper/nickel/combinations such as platinum, this metal level 122 is individual layers in this embodiment, and the material of metal level 122 is gold, metal level 122 surface definition one zone that is positioned at polymer projection 114 tops is for engaging connection pad 124, and this engages connection pad 124 and can be used on the connection external circuitry.
See also shown in Fig. 5 g, remove patterning photoresist layer 120 and remove not the Seed Layer below metal level 122 118, stick together/barrier layer 116.
See also shown in Fig. 5 h, integrated circuit 100 is carried out cutting step, produce several semiconductor chips (chip) 126, the joint connection pad 124 of semiconductor chip 126 can engage (tape automatedbonded automatically via pasting band, TAB), COG (chip on glass), coil type crystal grain engage (Tape Carrier Package, TCP) or the mode of COF (chip on film) be connected on the external circuitry 128, this extraneous circuit 128 has at least one jointing metal layer 129, engages connection pad 124 and is connected to jointing metal layer 129.
Shown in Fig. 5 i, this enforcement embodiment is connected to external circuitry 128 in the COG mode, utilizes anisotropic conductive 130 the joint connection pad 124 of semiconductor chip 126 to be connected to the jointing metal layer 129 of external circuitry 128.
See also shown in Fig. 5 j, this enforcement embodiment is if be connected to external circuitry 128 in the COF mode, then utilize anisotropic conductive 130 the joint connection pad 124 of semiconductor chip 126 to be connected to the jointing metal layer 129 of external circuitry 128 equally, the mode that another kind of COF engages, see also shown in Fig. 5 k, to be the mode of utilizing hot pressing be engaged to the joint connection pad 124 of semiconductor chip 126 on the external circuitry 128 of stanniferous this mode, rely on hot pressing to make the gold of joint connection pad 124 and the tin layer on the jointing metal layer 129 132 produce Sillim's alloy-layers 134 and firm engagement, the mode that this kind relies on hot pressing to engage also may be used on pasting band and engages (tape automatedbonded automatically, TAB) engage with coil type crystal grain (Tape Carrier Package, TCP) on.
The 2nd execution mode of second embodiment:
The structure of the structure of this 2nd execution mode and manufacture method and the 1st execution mode and manufacture method are quite similar, and the material of the same components among therefore following each embodiment and the embodiment and processing procedure are with regard to not in addition repeat specification.
See also shown in Fig. 6 a; the 2nd execution mode and the 1st execution mode discrepancy are that the integrated circuit 100 of the 2nd execution mode has two connection pads 32,32 ', form polymeric layer 112 equally on the protective layer on the whole integrated circuit 100 34 and connection pad 32,32 '.
See also shown in Fig. 6 b; and by exposure (exposure), development (development) processing procedure and this polymeric layer 112 of etch process patterning; make this polymeric layer 112 form several polymer projections (polymerbump) 114 (only demonstrating 1 in the icon); and expose protective layer 34 and connection pad 32,32 '; then carry out heat hardening, make this polymer projection 114 sclerosis.When this polymer projection 114 is that sense is when revolving the optical activity material, can only utilize micro-photographing process (need not etch process) to come this polymer projection 114 of patterning, and the thickness of this polymer projection 114 is between 5 microns to 50 microns, and the maximum transverse size of polymer projection 114 is between 10 microns to 60 microns.
See also shown in Fig. 6 c; formation sticks together/barrier layer (adhesion/barrier layer) 116 the protective layer 34 on the whole integrated circuit 100, connection pad 32,32 ' and polymer projection 114 on; this sticks together/and the thickness of barrier layer 116 is between 0.02 micron to 0.8 micron, and be preferable with the thickness between 0.05 micron to 0.2 micron.
See also shown in Fig. 6 d, then form thickness between the Seed Layer (seed layer) 118 of (preferred thickness is between between 0.1 micron to 0.7 micron) between 0.005 micron to 2 microns sticking together/barrier layer 116 on.
See also shown in Fig. 6 e, form photoresist layer 120 on Seed Layer 118, and, photoresist layer 120 in, also expose respectively and be positioned at connection pad 32,32 ' and the Seed Layer 118 of polymer projection 114 tops to form several photoresist layer openings 120a, 120b by the exposure (exposure) and this photoresist layer 120 of (development) processing procedure patterning that develops.
See also shown in Fig. 6 f, form metal level 122 at opening 120a with plating mode, on the Seed Layer 118 that 120b exposed, this metal level 122 is coated polymer projection 114 2 lip-deep Seed Layer 118 at least, and metal level 122 is such as being gold, copper, silver, palladium, platinum, rhodium, ruthenium, the single-layer metal layer structure of rhenium or nickel or composite metal layer structure, the thickness of this metal level 122 is between 1 micron to 20 microns, preferable thickness can be between 1.5 microns to 15 microns, and the combination of composite metal layer structure comprises copper/nickel/gold, copper/gold, copper/nickel/palladium and copper/nickel/combinations such as platinum, this metal level 122 is individual layers in this embodiment, and the material of metal level 122 is gold, definition two zones, metal level 122 surface are respectively one and engage a connection pad 124 and a routing connection pad 136, engaging connection pad 124 is to be positioned on the polymer projection 114, and routing connection pad 136 is positioned on the connection pad 32 ', and this joint connection pad 124 can be used on routing connection pad 136 and is connected external circuitry.
See also shown in Fig. 6 g, remove patterning photoresist layer 120 and remove not the Seed Layer below metal level 122 118, stick together/barrier layer 116.
See also shown in Fig. 6 h and Fig. 6 i, integrated circuit 100 is carried out cutting step, produce several semiconductor chips (chip) 126, the joint connection pad 124 of semiconductor chip 126 can be via covering crystalline substance (Flip Chip, FC) technology is engaged on another extraneous substrate 138, this extraneous substrate 138 is such as being semiconductor chip, when this extraneous substrate 138 is semiconductor chip, this extraneous substrate 138 has several and engages connection pad 140, on joint connection pad 140, has a jointing metal layer 142, the material of this jointing metal layer 142 comprises gold, copper, silver, palladium, platinum, rhodium, ruthenium, rhenium, the single-layer metal layer structure of tin or nickel or composite metal layer structure, this jointing metal layer 142 can change to some extent along with the material of metal level 122, when for example the material of metal level 122 is gold, the material of jointing metal layer 142 is metal levels of gold or stanniferous, then utilize and cover crystalline substance (Flip Chip, FC) technology is with extraneous substrate 138 folded being located on the semiconductor chip 126, wherein the mode of Jie Heing can adopt the mode of hot pressing, jointing metal layer 142 and metal level 122 are produced to be merged or alloy (gold/gold engages or gold-ashbury metal) joint, and between extraneous substrate 138 and semiconductor chip 126, form an encapsulated layer 144 with its coating, the material of this encapsulated layer 144 is polymerizable material, such as being epoxy resin.136 of routing connection pads form a lead 146 via the routing processing procedure and are connected on another external circuitry (not shown) in addition.
See also shown in Fig. 6 j, routing connection pad 136 is connected to another external circuitry except utilizing the formed lead 146 of routing processing procedure in addition, also can be connected on the tin ball 147 of external circuitry, the thickness of this tin ball 147 is between 50 microns to 300 microns, and this connected mode can utilize the mode of hot pressing to engage.
The 3rd execution mode of second embodiment:
The structure and the manufacture method of the structure of this 3rd execution mode and manufacture method and the 2nd execution mode and the 1st execution mode are quite similar, and the material of the same components among therefore following each embodiment and the embodiment and processing procedure are with regard to not in addition repeat specification.
See also shown in Fig. 7 a and Fig. 7 b, the 3rd execution mode only is that with the 2nd execution mode discrepancy the position of routing connection pad 136 is different, it is seen from birds-eye perspective (Fig. 7 b) in the position of the routing connection pad 136 of the 3rd execution mode, routing connection pad 136 positions are the positions that are different from connection pad 32 ', wherein can be provided with at least one driving component in the substrate 10 in the integrated circuit 100 of routing connection pad 136 belows, this driving component comprises diode, transistor etc., driving component existing detailed introduction in said modules layer 12 is not just repeated to discuss at this.
The 4th execution mode of second embodiment:
The structure and the manufacture method of the structure of this 4th execution mode and manufacture method and the 3rd execution mode and the 1st execution mode are quite similar, and the material of the same components among therefore following each embodiment and the embodiment and processing procedure are with regard to not in addition repeat specification.
See also shown in Fig. 8 a, form polymeric layer 112 equally on the protective layer on the whole integrated circuit 100 34 and connection pad 32 and connection pad 32 '.
See also shown in Fig. 8 b; and by exposure (exposure); (development) processing procedure and this polymeric layer 112 of etch process patterning develop; make this polymeric layer 112 form several openings 112a and several polymer blocks (polymer island) 142; opening 112a exposes protective layer 34; connection pad 32 and connection pad 32 '; then carry out heat hardening; make polymer blocks 148 sclerosis; the temperature of this hardening process be between 150 the degree (℃) to 300 the degree (℃) between; and the material of this polymer blocks 148 is optional from polyimides (polyimide; PI); benzyl ring butylene (benzocyclobutene; BCB); Parylene (parylene); epoxy-based material (epoxy-based material) one of them; for example epoxy resin or the photoepoxySU-8 that is provided by the Sotec Microsystems of the Renens that is positioned at Switzerland; elastomeric material (elastomer), for example silicone (silicone).When this polymeric layer 112 revolves the optical activity material for sense, can only utilize micro-photographing process (need not etch process) to come this polymeric layer 112 of patterning, and the thickness of this polymer blocks 148 is between 5 microns to 50 microns.
See also shown in Fig. 8 c and Fig. 8 d, then form another polymeric layer 150 in polymer blocks 148 and opening 112a, the material of this polymeric layer 150 is identical with polymeric layer 112, and by exposure (exposure), this polymeric layer 150 of (development) processing procedure and etch process patterning that develops forms several polymer projections (polymer bump) 152 (only demonstrating 1 in the icon), when this polymeric layer 150 revolves the optical activity material for sense, can only utilize micro-photographing process (need not etch process) to come this polymeric layer 150 of patterning, and the thickness of this polymer projection is between 5 microns to 50 microns, and the maximum transverse size of polymer projection 152 is between 10 microns to 60 microns.
See also shown in Fig. 8 e, form stick together/barrier layer (adhesion/barrier layer) 116 is on the connection pad 32 on the whole integrated circuit 100, connection pad 32 ', polymer projection 152 and polymer blocks 148.
See also shown in Fig. 8 f, then form thickness between the Seed Layer (seed layer) 118 of (preferred thickness is between between 0.1 micron to 0.7 micron) between 0.005 micron to 2 microns sticking together/barrier layer 116 on.
See also shown in Fig. 8 g, form photoresist layer 120 on Seed Layer 118, and by the exposure (exposure) and this photoresist layer 120 of (development) processing procedure patterning that develops, forming several photoresist layer openings 120a in photoresist layer 120 and expose the Seed Layer 118 that is positioned at connection pad 32, connection pad 32 ', polymer projection 152 and polymer blocks 148 tops, and in the process that forms photoresist layer opening 120a such as being that exposure machine (steppers) or scanning machine (scanners) with one times (1X) carries out exposure imaging.
See also shown in Fig. 8 h, form metal level 122 on the Seed Layer 118 that opening 120a is exposed with plating mode, this metal level 122 is coated polymer projection 152 2 lip-deep Seed Layer 118 at least, and metal level 122 is such as being gold, copper, silver, palladium, platinum, rhodium, ruthenium, the single-layer metal layer structure of rhenium or nickel or composite metal layer structure, the thickness of this metal level 122 is between 1 micron to 20 microns, preferable thickness can be between 1.5 microns to 15 microns, and the combination of composite metal layer structure comprises copper/nickel/gold, copper/gold, copper/nickel/palladium and copper/nickel/combinations such as platinum, this metal level 122 is individual layers in this embodiment, and the material of metal level 122 is gold, metal level 122 surface definition one zone that is positioned at polymer projection 152 tops is for engaging connection pad 124, this engages connection pad 124 and can be used on the connection external circuitry, and metal level 122 surface definition one zone that is positioned at polymer blocks 148 tops is routing connection pad 136, this routing connection pad 136 is connecting external circuitry via the routing processing procedure, wherein be positioned at polymer blocks 148 stress that the available buffer routing is produced when the routing processing procedure under the routing connection pad 136, substrate 10 for thinner thickness has enough buffering effects, can prevent the substrate 10 of integrated circuit 100, the driving component of component layer 12 damages when the routing processing procedure, this embodiment is different with the position of connection pad 32 ' by the routing connection pad 136 of upper viewing view sight in addition, but routing connection pad 136 also can be positioned at connection pad 32 ' top, does not just increase the weight of to cover argumentation at this.
See also shown in Fig. 8 i, remove patterning photoresist layer 120 and remove not the Seed Layer below metal level 122 118, stick together/barrier layer 116.
See also shown in Fig. 8 j, integrated circuit 100 is carried out cutting step, produce several semiconductor chips (chip) 126.
See also shown in Fig. 8 k, this Fig. 8 k is similar to above-mentioned Fig. 6 i, be with semiconductor chip 126 via cover crystalline substance (Flip Chip, FC) technology is engaged on another extraneous substrate 138, wherein the explanation of Jie Heing is as above-mentioned 6i figure explanation, so just do not repeated to discuss at this.
The 5th execution mode of second embodiment:
The structure of the structure of the 5th execution mode and manufacture method and the 4th execution mode and manufacture method are quite similar, the structure of this 4th execution mode is the variation of the 1st execution mode, and the material of the same components among therefore following each embodiment and the embodiment and processing procedure are with regard to not in addition repeat specification.
See also shown in Fig. 9 a, the 5th execution mode and the 4th execution mode difference are exposure (exposure), the step of (development) processing procedure and this polymeric layer 112 of etch process patterning and heat hardening of developing, is to form polymer blocks 148 and polymer projection 114 simultaneously at the 5th execution mode in this two step, also identical with the thickness of polymer projection 114 with regard to polymer blocks 148, and the thickness of this polymer blocks 148 and polymer projection 114 is between 5 microns to 50 microns.
See also shown in Fig. 9 b, form in regular turn stick together/barrier layer (adhesion/barrier layer) 116 and thickness between the Seed Layer (seedlayer) 118 of (preferred thickness is between between 0.1 micron to 0.7 micron) between 0.005 micron to 2 microns on the connection pad 32 on the whole integrated circuit 100, connection pad 32 ', polymer projection 114 and polymer blocks 148.
See also shown in Fig. 9 c, form photoresist layer 120 on Seed Layer 118, and by the exposure (exposure) and this photoresist layer 120 of (development) processing procedure patterning that develops, forming several photoresist layer openings 120a in photoresist layer 120 and expose the Seed Layer 118 that is positioned at connection pad 32, connection pad 32 ', polymer projection 114 and polymer blocks 148 tops, and in the process that forms photoresist layer opening 120a such as being that exposure machine (steppers) or scanning machine (scanners) with one times (1X) carries out exposure imaging.
See also shown in Fig. 9 d, form metal level 122 on the Seed Layer 118 that opening 120a is exposed with plating mode, this metal level 122 is coated polymer projection 114 2 lip-deep Seed Layer 118 at least, metal level 122 is such as being gold, copper, silver, palladium, platinum, rhodium, ruthenium, the single-layer metal layer structure of rhenium or nickel or composite metal layer structure, the thickness of this metal level 122 is between 1 micron to 20 microns, preferable thickness can be between 1.5 microns to 15 microns, and the combination of composite metal layer structure comprises copper/nickel/gold, copper/gold, copper/nickel/palladium and copper/nickel/combinations such as platinum, this metal level 122 is individual layers in this embodiment, and the material of metal level 122 is gold, metal level 122 surface definition one zone that is positioned at polymer projection 114 tops is for engaging connection pad 124, this engages connection pad 124 and can be used on the connection external circuitry, and metal level 122 surface definition one zone that is positioned at polymer blocks 148 tops is routing connection pad 136, this routing connection pad 136 is connecting external circuitry via the routing processing procedure, wherein be positioned at polymer blocks 148 stress that the available buffer routing is produced when the routing processing procedure under the routing connection pad 136, substrate 10 for thinner thickness has enough buffering effects, can prevent the substrate 10 of integrated circuit 100, the driving component of component layer 12 damages when the routing processing procedure, this embodiment is different with the position of connection pad 32 ' by the routing connection pad 136 of upper viewing view sight in addition, but routing connection pad 136 also can be positioned at connection pad 32 ' top, does not just add at this and repeats to discuss.
See also shown in Fig. 9 e, remove patterning photoresist layer 120 and remove not the Seed Layer below metal level 122 118, stick together/barrier layer 116.
See also shown in Fig. 9 f, integrated circuit 100 is carried out cutting step, produce several semiconductor chips (chip) 126.
See also shown in Fig. 9 g, this Fig. 9 g is similar to above-mentioned Fig. 6 i, be with semiconductor chip 126 via cover crystalline substance (Flip Chip, FC) technology is engaged on another extraneous substrate 138, wherein the explanation of Jie Heing is as above-mentioned 6i figure explanation, so just do not repeated to discuss at this.
The 6th execution mode of second embodiment:
The structure of the structure of the 6th execution mode and manufacture method and the 1st execution mode and manufacture method are quite similar, the structure of this 6th execution mode is the variation of the 1st execution mode, and the material of the same components among therefore following each embodiment and the embodiment and processing procedure are with regard to not in addition repeat specification.
This embodiment is Fig. 5 e processing procedure of the 1st execution mode of continuing, after finishing Fig. 5 e, see also shown in Figure 10 a, form a metal level 154 on the Seed Layer 118 that opening 120a is exposed with plating mode, metal level 154 is such as being copper, the thickness of this metal level 154 is between 1 micron to 20 microns, and preferable thickness can be between 1.5 microns to 15 microns.
See also shown in Figure 10 b, then re-plating one metal level 156 is on metal level 154, and the material of this metal level 156 is such as being nickel, and the thickness of this metal level 156 is between 0.1 micron to 20 microns, and preferable thickness can be between 1 micron to 15 microns.
See also shown in Figure 10 c, form another photoresist layer 158 on photoresist layer 120, metal level 156, and by the exposure (exposure) and this photoresist layer 158 of (development) processing procedure patterning that develops, forming several photoresist layer openings 158a in photoresist layer 158 and expose the metal level 156 that is positioned at above the polymer projection 114, and in the process that forms photoresist layer opening 158a such as being that exposure machine (steppers) or scanning machine (scanners) with one times (1X) carries out exposure imaging.
The another kind of mode that forms photoresist layer 158 also can be removed original photoresist layer 120 earlier earlier, form photoresist layer 158 again on Seed Layer 118 and metal level 156, and by the exposure (exposure) and this photoresist layer 158 of (development) processing procedure patterning that develops, to form photoresist layer opening 158a in photoresist layer 158 and expose the metal level 156 that is positioned at above the polymer projection 114, shown in Figure 10 d.
Shown in the hookup 10e, re-plating one metal level 160 is on the metal level 156 that photoresist layer opening 158a is exposed, the material of this metal level 160 is such as being to contain tin metal, leypewter, sn-ag alloy, SAC alloy-layer, lead-free solder etc., the thickness of this metal level 160 is between 1 micron to 300 microns, and preferable thickness can be between 5 microns to 200 microns.
See also shown in Figure 10 f, remove patterning photoresist layer 158, photoresist layer 120, and remove not the Seed Layer below metal level 156 118, stick together/barrier layer 116.
See also shown in Figure 10 g, carry out heating processing again, make metal level 160 arrive fusing point and interior conglomerate.
See also shown in Figure 10 h, cutting step is carried out in substrate 10, produce several semiconductor chips (chip) 126, the metal level 160 on the semiconductor chip 126 can be engaged on another extraneous substrate.
More than explanation is just illustrative for the purpose of the present invention, and it is nonrestrictive, those of ordinary skills understand, under the situation of the spirit and scope that do not break away from claim and limited, can make many modifications, variation or equivalence, but but all will fall within the claim restricted portion of the present invention.
Claims (29)
1. a circuit pack is characterized in that, comprising:
The semiconductor chip;
The one first semiconductor-based end, be positioned at described semiconductor chip top, the described first semiconductor-based end, had at least one first metallic pad, and the described first semiconductor-based end comprise several thickness between first dielectric layer between 0.05 micron to 2 microns and several thickness the first thin line layer between 0.05 micron to 2 microns, described first dielectric layer has a plurality of first passages hole, the described first thin line layer is positioned at one of them top of described first dielectric layer, and the described first thin line layer relies on described first passage hole to be electrically connected to each other;
One first protective layer, be positioned at at described first the semiconductor-based end, and described first protective layer has at least one opening and exposes described first metallic pad, and the material of described first protective layer comprises a nitrogen silicon compound and an oxygen silicon compound one of them or its combination;
One the first metal layer, be positioned at described first protective layer top and be electrically connected to described first metallic pad, and described the first metal layer has one first routing connection pad and one second routing connection pad, described first routing connection pad and the described second routing connection pad all are electrically connected to described first metallic pad, and the thickness of described the first metal layer is between 1 micron to 20 microns;
One first sticks together/barrier layer, between described the first metal layer and described first metallic pad;
One Seed Layer, stick together described first/barrier layer and described the first metal layer between, and described Seed Layer is identical material with described the first metal layer;
One silicon is positioned at described first protective layer top;
One first routing lead, an end connect the described first routing connection pad, and the other end then connects described semiconductor chip; And
One second routing lead, an end connect the described second routing connection pad, and the other end then connects described silicon.
2. circuit pack according to claim 1 is characterized in that: the bottom of the described first thin line layer is the copper layer, and top layer is an aluminium lamination.
3. circuit pack according to claim 1 is characterized in that: the described first thin line layer comprises an aluminium lamination or the copper layer of thickness between 0.05 micron to 2 microns.
4. circuit pack according to claim 1 is characterized in that: also comprise a printed circuit board (PCB), and described semiconductor chip is positioned at described printed circuit board (PCB) top.
5. circuit pack according to claim 1 is characterized in that: the material of described the first metal layer comprises gold.
6. circuit pack according to claim 1 is characterized in that: the material of described the first metal layer comprises copper.
7. circuit pack according to claim 1 is characterized in that: the material of described the first metal layer comprises silver, platinum, palladium and nickel one of them or its combination.
8. circuit pack according to claim 1 is characterized in that: comprise that also a polymer protective layer coats described semiconductor chip, the described first routing lead, the described second routing lead and described silicon.
9. circuit pack according to claim 1 is characterized in that: be in diverse location by the described first routing connection pad of birds-eye perspective sight and the described second routing connection pad and described first metallic pad.
10. circuit pack according to claim 1 is characterized in that: described first stick together/barrier layer comprises a titanium-tungsten layer or the titanium coating of thickness between 0.02 micron to 0.8 micron.
11. circuit pack according to claim 1 is characterized in that: the described first semiconductor-based end, comprised a driving component, and described driving component is positioned at described first routing connection pad or described second routing connection pad below.
12. circuit pack according to claim 11 is characterized in that: described driving component comprises transistor.
13. circuit pack according to claim 1 is characterized in that: also be provided with a polymeric layer between described first protective layer and the described the first metal layer.
14. circuit pack according to claim 1 is characterized in that: also be provided with a polyimide compound layer between described first protective layer and the described the first metal layer, its thickness is between 2 microns to 100 microns.
15. circuit pack according to claim 1 is characterized in that: also be provided with a polymeric layer on the described the first metal layer, its thickness is between 2 microns to 100 microns.
16. a circuit pack is characterized in that, comprising:
The one first semiconductor-based end, one first protective layer is positioned at at described first the semiconductor-based end, at least one first opening of described first protective layer exposes one first connection pad at the described first semiconductor-based end, and a first metal layer is positioned on described first protective layer and via described first opening and connects described first connection pad, and described the first metal layer comprises several first routing connection pads;
The one second semiconductor-based end, be positioned at at described first the semiconductor-based end and expose at least one side in the described first semiconductor-based end and the described first routing connection pad, and one second protective layer is positioned at at described second the semiconductor-based end, at least one second opening of described second protective layer exposes one second connection pad at the described second semiconductor-based end, and one second metal level is positioned on described second protective layer and via described second opening and connects described second connection pad, and described second metal level comprises several second routing connection pads;
One the 3rd semiconductor-based end, be positioned at at described second the semiconductor-based end and expose at least one side in the described second semiconductor-based end and the described second routing connection pad, and one the 3rd protective layer is positioned at at the described the 3rd the semiconductor-based end, at least one the 3rd opening of described the 3rd protective layer exposes one the 3rd connection pad at described the 3rd semiconductor-based end, and one the 3rd metal level is positioned on described the 3rd protective layer and via described the 3rd opening and connects described the 3rd connection pad, and described the 3rd metal level comprises several the 3rd routing connection pads;
One the 4th semiconductor-based end, be positioned at at the described the 3rd the semiconductor-based end and expose at least one side in the described the 3rd semiconductor-based end and described the 3rd routing connection pad, and one the 4th protective layer is positioned at at the described the 4th the semiconductor-based end, at least one the 4th opening of described the 4th protective layer exposes one the 4th connection pad at described the 4th semiconductor-based end, and one the 4th metal level is positioned on described the 4th protective layer and via described the 4th opening and connects described the 4th connection pad, and described the 4th metal level comprises several the 4th routing connection pads;
Several routing leads, be positioned on the described first routing connection pad, the described second routing connection pad, described the 3rd routing connection pad and described the 4th routing connection pad, described first routing connection pad and the described second routing connection pad, the described second routing connection pad and described the 3rd routing connection pad, described the 3rd routing connection pad and described the 4th routing connection pad are interconnected via described routing lead; And
One external circuitry is connected to the described first routing connection pad, the described second routing connection pad, described the 3rd routing connection pad and described the 4th routing connection pad at least on one of them via described routing lead.
17. circuit pack according to claim 16, it is characterized in that: the described first semiconductor-based end, the described second semiconductor-based end, the described the 3rd semiconductor-based end and the described the 4th semiconductor-based end, comprise a thin on-line composition respectively, and described thin on-line composition comprises:
Several thickness lay respectively at the described first semiconductor-based end, the described second semiconductor-based end, the described the 3rd semiconductor-based end and the described the 4th semiconductor-based end, and described dielectric layer have a plurality of access openings less than 3 microns dielectric layer; And
Several thickness are less than 3 microns thin line layer, and described thin line layer is to be positioned at described dielectric layer on one of them, and wherein said thin line layer relies on described access opening to be electrically connected to each other.
18. circuit pack according to claim 17 is characterized in that: described thin line layer comprises an aluminium lamination or the copper layer of thickness between 0.05 micron to 2 microns.
19. circuit pack according to claim 16 is characterized in that: the material of described first protective layer, described second protective layer, described the 3rd protective layer and described the 4th protective layer comprises a nitrogen silicon compound and an oxygen silicon compound one of them or its combination.
20. circuit pack according to claim 16 is characterized in that: the material of described the first metal layer, described second metal level, described the 3rd metal level and described the 4th metal level comprises gold.
21. circuit pack according to claim 16 is characterized in that: the material of described the first metal layer, described second metal level, described the 3rd metal level and described the 4th metal level comprises copper, silver, platinum, palladium and nickel one of them or its combination.
22. circuit pack according to claim 16 is characterized in that: described the first metal layer, described second metal level, described the 3rd metal level and described the 4th metal layer thickness are respectively between 1 micron to 20 microns.
23. circuit pack according to claim 16 is characterized in that: described the first metal layer, described second metal level, described the 3rd metal level and described the 4th metal layer thickness are respectively between 1.5 microns to 15 microns.
24. circuit pack according to claim 16 is characterized in that: be respectively equipped with one between described the first metal layer and described first connection pad, described second metal level and described second connection pad, described the 3rd metal level and described the 3rd connection pad and described the 4th metal level and described the 4th connection pad and stick together/barrier layer.
25. circuit pack according to claim 24 is characterized in that: described sticking together/barrier layer comprises a titanium-tungsten layer or the titanium coating of thickness between 0.02 micron to 0.8 micron.
26. circuit pack according to claim 25 is characterized in that: be respectively equipped with a Seed Layer between described sticking together/barrier layer and described the first metal layer, second metal level, the 3rd metal level and the 4th metal level.
27. circuit pack according to claim 16 is characterized in that: described external circuitry comprise printed circuit board (PCB), metal substrate, glass substrate, flexible base plate, ceramic substrate and semiconductor chip one of them.
28. circuit pack according to claim 16; it is characterized in that: be respectively equipped with one first polymeric layer between described first protective layer and described the first metal layer, described second protective layer and described second metal level, described the 3rd protective layer and described the 3rd metal level and described the 4th protective layer and described the 4th metal level; a described polymer layer of thickness is between 2 microns to 100 microns, and it comprises polyimide compound.
29. circuit pack according to claim 16, it is characterized in that: be respectively equipped with a second polymer layer on described the first metal layer, described second metal level, described the 3rd metal level and described the 4th metal level, described the second polymer layer thickness is between 2 microns to 100 microns, and it comprises polyimide compound.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6667189B1 (en) * | 2002-09-13 | 2003-12-23 | Institute Of Microelectronics | High performance silicon condenser microphone with perforated single crystal silicon backplate |
| CN1253939C (en) * | 2002-02-10 | 2006-04-26 | 台湾积体电路制造股份有限公司 | Jointing washer structure on semiconductor substrate |
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| CN1253939C (en) * | 2002-02-10 | 2006-04-26 | 台湾积体电路制造股份有限公司 | Jointing washer structure on semiconductor substrate |
| US6667189B1 (en) * | 2002-09-13 | 2003-12-23 | Institute Of Microelectronics | High performance silicon condenser microphone with perforated single crystal silicon backplate |
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